Let Vgf and Vgb de- note the front and back gate voltages while tsi, tof and tob represent the silicon lm thickness, front gate oxide thickness, and back gate oxide ...
1
Design and Optimization of Double-Gate SOI MOSFETs for Low Voltage Low Power Circuits Liqiong Wei, Zhanping Chen, and Kaushik Roy 1285 EE Building, Purdue Univ., W. Lafayette, IN 47907
Introduction: With the growing use of portable and wireless electronic systems, design of high performance, low-voltage, low-power digital devices and circuits has become an important concern in today's VLSI applications [1]. Double-gate (DG) fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET has ideal subthreshold slope, high drive current and superb short channel e ect immunity, which makes it very attractive in lowvoltage, low-power, and high-performance CMOS designs [2]. In this paper, by solving Poisson equation, we propose a general model which has been veri ed by SOI-SPICE simulations. Based on this model, DGSOI MOSFETs are compared with conventional single gate FD SOI (SGSOI) MOSFETs, and the design and optimization of DGSOI MOSFETs in terms of circuit delay, power dissipation and power delay product are presented. In our analysis, we focus on the FD DGSOI transistors without volume inversion, where the classical method is still valid. Modeling: Consider a DGSOI MOSFET. Let Vgf and Vgb denote the front and back gate voltages while tsi , tof and tob represent the silicon lm thickness, front gate oxide thickness, and back gate oxide thickness, respectively. Without loss of generality, we assume that tof tob. If tof = tob , the transistor is regarded as a symmetric DGSOI MOSFET. Natural length scale () is used to characterize short channel e ect (SCE) [7]. To be free of SCE, the minimum channel length of a transistor should satisfy Lmin = m, where m is determined by the speci c application. Generally, m is between 5 and 10. Byqsolving 2-dimensional Poisson equation, we can obtain = 2(1+ ) , where = oxsi ttofsi + ttofob and = 2 oxsi tob tsi + t2si . There are two extreme (1) for SGSOI MOSFET p si tofconditions: (tob 1), = ox t , (2) for symmetric DGSOI MOSsi p FET (tob = tof ), = 2siox tof tsi. The natural length scales of SGSOI and symmetric DGSOI MOSFETs at di erent tof and tsi are given in table I. The Lmin of symmetric DGSOI MOSFETs is about 30% smaller than that of SGSOI MOSFETs. Consider a DGSOI NMOSFET. The front gate threshold voltage with depleted back surface (Vtf;depb ) and front gate threshold voltage with inverted back surface (Vtf;invb ) can be expressed by the following equations Vtf;depb (Vgb) = Vfbf +
(1 + )(2F ) ? (Vgb ? Vfbb ) + 2 qN siA
A tsi Vtf;invb = Vfbf + 2F + q N 2Cof
(1) (2)
where Vfbf and Vfbb are the front channel and back channel at band voltages, respectively. F is Fermi Potential. NA is channel doping and Cof is the front gate capacitance per unit area. Back gate threshold voltage with front surface depleted (Vtb;depf (Vgf )) and back gate threshold voltage with front surface inverted (Vtb;invf ) can be obtained similarly. For SGSOI MOSFETs, tob 1 and Vgb = 0. The back surface is depleted, and hence, the threshold voltage is Vth;soi = Vfbf + 2F + q NCAoftsi . Figure 1 shows the relationship between the front gate threshold voltage (Vtf ) and Vgb . The stars represent the results obtained by SOI-SPICE [4] simulations while the solid lines represent the results for our model. The back gate thresholds(Vtb ) at di erent Vgf are given in gure 2. The threshold voltage of the corresponding SGSOI MOSFET is 0.38V. Vtf;0 and Vtb;0 represent the front gate threshold voltage at zero bias Vgb and back gate threshold voltage at zero bias Vgf , respectively. Due to the
strongly coupled front gate and back gate surface potentials, the front gate threshold voltages of DGSOI MOSFETs decrease by 1 times the increase in Vgb . When Vgb is large enough to make the back surface inverted, the inversion layer on the back surface acts as a barrier between front and back gates and Vtf will be pinned to Vtf;invb . Vtb varies with Vgf in the same way. For a DGSOI MOSFET, Vgf = Vgb . Suppose the gate voltage varies from 0 to Vg . Vtf denotes the intersection of the threshold line and the line Vgb = Vtf . If Vg < Vtf , DGSOI MOSFET is in the subthreshold regime. If Vtf Vg < Vtb;invf , the front channel will conduct. In this case, Vtf changes from Vtf;0 to Vtf;dep (Vg ). If Vg is larger than Vtb;invf , both channels will contribute to the conduction. Vtf will change from Vtf;0 to Vtf;invb while Vtb from 0 to Vtb;invf . Hence, the threshold voltage of DGSOI MOSFETs can be dynamically changed, which in turn bene ts the circuit performance. When the transistor is \o ", the threshold voltage is high to suppress the leakage. If it is \on", the low threshold voltage improves speed. Another advantage of dynamic thresholds of DGSOI MOSFETs is with regard to supply voltage scaling. For a CMOS circuit, Vdd should be larger than twice the threshold voltage. For DGSOI MOSFET, the minimum supply voltage (Vmin ) can be obtained from the intersection of the threshold line and the line Vgb = 2Vtf , which is smaller than 2Vtf;0 . When Vmin Vdd Vtb;invf , the transistor is a DGDT SOI MOSFET [5], which is an asymmetric DGSOI MOSFET with front channel conducting and back gate acting as a controlling gate for Vtf . If Vdd is larger than Vtb;invf , the device is regarded as a double channel MOSFET. For a DGSOI NMOSFET, the saturation current(Ion ) is 0
0
0
Ion
=
Ion
=
(Vdd ? Vtf;vdd )2 Weff Cof sat L for Vdd < Vtb;invf (3) 2L 1 + (Vdd ? Vtf;vdd )= 2veff Weff Cof (Vdd ? Vtf;invb )2 sat L + 2L 1 + (Vdd ? Vtf;invb)= 2veff Weff Cob (Vdd ? Vtb;invf )2 sat L for Vdd Vtb;invf (4) 2L 1 + (Vdd ? Vtb;invf )= 2veff
where Vtf;vdd = Vtf;depd (Vdd ). Since DGSOI MOSFET has nearly ideal subthreshold slope, the subthreshold current (Ioff ) can be expressed by Vtb;0 Vtf;0 Vdd Vdd Ioff = If 0 e? VT (1 ? e? VT ) + Ib0 e? VT (1 ? e? VT ) (5)
Table II shows the modeling and simulation results of Ion and Ioff for DGSOI at di erent tob . The thinner the back gate oxide thickness, the larger the Ion and Ioff . Design and Optimization: The propagation delay of a Vdd (1+2:2 Wn ) [3]. CMOS inverter can be expressed as tpd C4LIon Wp where CL is the load capacitance, Wn and Wp are the channel widths of NMOS and PMOS transistors. Since the junction capacitance of FD SOI MOSFET is very small [2], the load capacitance can be regarded as the sum of gate capacitance and interconnect capacitance (CL = Cg + Cint ). For SGSOI inverters, Cg = (Wn + Wp )LCof . Now, for DGSOI inverters, Cg = Cgf + Cgb = (Wn + Wp )L(Cof + Cob ). In our simulation, we assume Cint = kint Cgf , where kint is de ned as the interconnect coecient. Figure 3 shows the propagation delay ratios of DGSOI inverters to those of SGSOI inverters. The performance improvement for DGSOI is more signi cant for lower supply voltage and This research was supported in part by Intel and DARPA (F33615-95-C-1625) higher interconnect conditions.
2
Natural length scales of SGSOI and symmetric DGSOI MOSFETs
Vgb
Vtf,0
0.3
tsi=50nm tof=5nm W/L=1.8/0.25 Na=4.2e17cm−3 VFBF=VFBB=−1 Vds=0.05V
2Vtf=
TABLE I
Vtf=Vgb
0.32
0.28
Vtf’ 0.26
___
MODEL
* *
SOI-SPICE
0.22
to
b=
40
to
0.2
nm
b=
30
nm 20 b= to
0.18
0.16
nm
m
% 29.15 29.35 29.37 29.23 29.41 29.21
Vtf (V)
0.24
0n
SGSOI 0.0247 0.0276 0.0303 0.0349 0.0391 0.0428
(m) Symmetric DGSOI 0.0175 0.0195 0.0214 0.0247 0.0276 0.0303
=1
tsi (nm) 40 50 60 40 50 60
tob
tof (nm) 5 5 5 10 10 10
0.14
Vtf,invb
Vtb,invf
Vmin 0.12
0
0.2
0.4
0.6
0.8 V
1 (V)
1.2
1.4
1.6
1.8
2
0.45
0.5
gb
Fig. 1. Vtf vs. Vgb
TABLE II
Ion & Ioff (tsi = 50nm;tof = 5nm; W=L = 1:8=0:25;Vdd = 1V )
Vtb,0
50nm 3.4e-4A 3.3e-4A 6.7e-11A 6.9e-11A
2
Vtb,invf
tob=40nm
1.5
tb
MODEL SOISPICE MODEL SOISPICE
tob 40nm 3.6e-4A 3.4e-4A 1.1e-10A 9.8e-11A
V (V)
Ion Ioff
30nm 3.9e-4A 3.6e-4A 2.1e-10A 1.7e-10A
tsi=50nm tof=5nm W/L=1.8/0.25 −3 Na=4.2e17cm VFBF=VFBB=−1 Vds=0.05V
2.5
tob=30nm
1
tob=20nm
0.5
[1] [2] [3] [4] [5] [6] [7]
References
Chandrakasan, et al., IEEE JSSC, April 1992, pp473. Colinge, \Silicon-on-Insulator Technology: Materials to VLSI", Kluwer. C. Hu, in Low Power Design Methodologies, pp21-36, 1996. J.G. Fossum, et al.,\SOISPICE-4 User's Guide", Univ. of Florida L. Wei, et al., IEEE International SOI Conference, pp82-83, 1997. S. Venkatesan, et al., IEEE Elec. Dev. Let., Vol.13, NO.1, pp44-46, 1992 R. Yan, et al., IEEE Tran. on Elec. Dev., Vol.39, No.7, pp1704-1710, 1992
0.05
0.1
0.15
0.2
0.25 V (V)
0.3
0.35
0.4
gf
Fig. 2. Vtb vs. Vgf 0.8
0.75
0.7
tpd(DGSOI)/tpd(SGSOI)
0.65
0.6
0.55
0.5
0.45
o k =2, Vdd=1V int * kint=0.2, Vdd=1V + kint=2, Vdd=0.8V x k =0.2, Vdd=0.8V
0.4
int
0.35
0.3
5
10
15
20
25
30
35
40
45
50
tob (nm)
Fig. 3. tpd (DGSOI)/tpd (SGSOI)(tsi =50nm, tof =5nm, L=0.25m) −8
7
x 10
Total Power Dyn Power Leak Power
6
Power Dissipation(W)
5 activity=0.03 k =0.2 int
Vdd=1V tsi=50nm tof=5nm L=0.25µ m f =100MHz
4
clk
3
2
1
0
5
10
15
20
25
30
35
40
45
50
tob (nm)
Fig. 4. Power Dissipations of a DGSOI inverter 1.1 Vdd=1V tsi=50nm tof=5nm L=0.25µ m activity=0.3 f =100MHz
1
clk
0.9
PDP(DGSOI) / PDP(SGSOI)
In CMOS digital circuits, power dissipation consists of dynamic and static components. With a thick tob in DGSOI, the back gate capacitance is very small and the load capacitance is almost the same as that of SGSOI. Scaling tob will increase the power dissipation. Figure 4 shows the total power of an inverter at 0.03 activity (the probability of switching) and 100MHz frequency. It can be seen that the leakage power is high for the symmetric DGSOI circuit because of the low threshold voltage. Power delay product(PDP) is a common measure of circuit performance. For symmetric DGSOI circuits, even though the propagation delay is small due to its high drive current, its power dissipation is high. For DGDT SOI circuits, propagation delays are larger than symmetric DGSOI circuits while consuming less power. Figure 5 shows the ratio of PDP of DGSOI inverters to that of SGSOI inverters. The tsi and tof are 50nm and 5nm, respectively. Channel length is 0:25m and switching activity is 0.3. The inverters work at 1V supply voltage and 100MHz frequency. If the interconnect capacitance is small (kint = 0:2), DGDT SOI circuit is a better choice. Its PDP is about 80% of that of the corresponding conventional FD SOI inverter. When interconnect capacitance is dominant, the symmetric DGSOI circuit shows more bene ts. The power delay product of symmetric DGSOI circuits can be around 50% of that of the conventional fully-depleted SOI circuit. Conclusions: In this paper, we present a general analytical model of double gate fully depleted SOI MOSFETs. Results show that the minimum channel length of DGSOI MOSFETs can be 30% smaller than that of conventional single gate FD SOI MOSFETs and the threshold voltage of DGSOI MOSFETs can be controlled dynamically. This in turn improves the performance of the circuits and bene ts the supply voltage scaling, making it a good candidate for deep submicron low voltage low power circuits. Using this model, the delay, power and power delay product of DGSOI circuits are analyzed. Symmetric DGSOI shows the fastest speed and highest power dissipation. Considering power delay product, if the interconnect capacitance is small, DGDT SOI circuit seems to be a better choice. Its PDP is about 80% of that of the corresponding conventional FD SOI inverter. When interconnect capacitance is dominant, the symmetric DGSOI circuit shows more bene ts. The power delay product of symmetric DGSOI circuits can be around 50% of that of the conventional fully-depleted SOI circuit.
tob=10nm Vtf’ 0
0.8
0.7
0.6
0.5
0.4
5
10
15
20
25
30
35
40
45
50
tob (nm)
Fig. 5. PDP(DGSOI)/PDP(SGSOI)(kint varies from 0.2 to 4 from top to down, the step is 0.4)
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