Quasi-Resonant DC-Link Inverter With a Reduced ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Quasi-Resonant DC-Link Inverter With a Reduced Number of Active Elements Slawomir Mandrek and Piotr J. Chrzan, Member, IEEE

Abstract—In this paper, a new scheme of a parallel quasiresonant dc-link inverter (PQRDCLI) for electrical drive applications is described. Principles of the soft-switching inverter operation for bidirectional energy transmission are presented. A PQRDCLI analysis with the aid of simulations and experimental tests is carried out. The circuit features relatively simple topological structure and moderate overcurrent stress of components. A robust control strategy of the quasi-resonant circuit operation with an inverter output voltage dv/dt limitation has been achieved. Index Terms—AC–AC power conversion, ac motor drives, electromagnetic interference (EMI), inverters, resonant power conversion, zero-voltage switching (ZVS).

I. I NTRODUCTION

T

HE FUNDAMENTAL topology of voltage-source inverters is usually based on a bridge scheme consisting of six bilateral semiconductor switches. Usefulness of this class of converters, particularly in electrical drive applications, has been confirmed by numerous advantages, e.g., relatively simple topology, available modulation strategies, robust detection of failures, and fast commutation rates. However, during commutation, an undesirably high rate of change at the power transistors may provoke harmful environmental phenomena such as: 1) electromagnetic interference (EMI) emissions (conducted and radiated); 2) increase of bearing currents; 3) overvoltage spikes at motor terminals. A solution diminishing these effects has been attained in a series of papers by Divan et al. [3], [4], particularly through the development of active clamped resonant dc-link inverter topologies, where the bus line voltage decreases resonantly to zero, enabling soft zero-voltage switching (ZVS) of inverter states. In order to control the inverter voltage by pulsewidth modulation techniques, further progress has been obtained by the quasi-resonant dc-link inverter (QRDCLI) structures, where an initial instant of each resonant cycle is commanded externally from the microcontroller [2], [5], and [10]. Detailed comparative studies of losses in hard commuted inverters and QRDCLI inverters show that, in quasi-resonant inverters, lower Manuscript received November 19, 2005; revised July 28, 2006. S. Mandrek is with the Gdańsk Shiprepair Yard “Remontowa,” 80-958 Gdańsk, Poland (e-mail: [email protected]). P. J. Chrzan is with the Department of Electrical and Control Engineering, Gdańsk University of Technology, 80-952 Gdańsk, Poland (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2007.895143

load ripple currents or lower total losses can be obtained [15]. By optimizing usually contradictory QRDCLI objectives such as circuit complexity, control accuracy, minimal reactive energy storage, and stress of components, various schemes have been recently proposed [1], [6]–[8], [14], [16], [19]. Quasi-resonant topologies were also presented in multilevel inverters and other topologies as an attractive solution for the reduction of losses and EMI [17], [18], [20], [21]. In this paper, a new alternative scheme of parallel QRDCLI auxiliary circuit is described (Fig. 1). The presented topology consists of only two transistors with parallel diodes: a resonant inductor and a capacitor. The PQRDCLI allows ZVS for inverter transistors and also gives ZVS/zero-current switching (ZCS) for auxiliary circuit transistors T1 and T2 . The main advantage of proposed topology is its simplicity in comparison with other topologies with comparable features [9]. The developed circuit is analyzed for the bidirectional operation and for the QRDCLI objectives with the aid of the TCad circuit simulator [11]–[13] and the experimental prototype. II. P RINCIPLE OF O PERATION The parallel quasi-resonant circuit is located in the dc-link of an indirect frequency converter. It consists of two input electrolytic capacitors C1 and C2 connected in series, which is usually the case due to a relatively low electrolytic capacitor voltage breakdown. The inverter is separated from the dc voltage source Udc by the bilateral switch based on transistor T1 with diode D1 . The capacitor midpoint is connected to the inductor L to form a quasi-resonant circuit with the capacitor Cf through the following auxiliary switching devices: transistor T2 with diode D2 or diode D3 . The rectifier is represented by the voltage source Udc with a series capacitor bank consisting of C1 and C2 as follows: UC2 = k · Udc

(1)

where the dividing factor k is defined as k=

C1 . C1 + C2

Assuming that the leakage inductance of the machine is much larger than the resonant inductance L, the inverter load circuit can be modeled by a current source Io during switching intervals. Thus, the circuit analysis, without loss of generality, is based on a scheme depicted in Fig. 2, where inverter transistors TF 1 ÷ TF 6 have been replaced by the Tf transistor with the parallel diode Df .

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MANDREK AND CHRZAN: QUASI-RESONANT DC-LINK INVERTER WITH A REDUCED NUMBER OF ACTIVE ELEMENTS

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Fig. 1. Indirect frequency converter with a parallel quasi-resonant circuit (P—rectifier with breaking chopper Rh , Th ; V—parallel quasi-resonant circuit; F—inverter).

Fig. 2.

Simulation equivalent circuit of the PQRDCLI.

When in the motor mode, electric energy is transmitted to the inverter, the resonant cycle consists of the following intervals. Mode 0 [−∞, t0 ]: The PQRDCLI operates in a steady state. Until instant t0 , transistor T1 is turned on while T2 is turned off. The inverter input voltage uf remains equal to Udc with zero inductor current iL = 0 [Fig. 3(a)]. Mode 1 [t0 , t1 ]: After transistor T2 is turned on at the ZCS conditions, it conducts linearly increasing inductor current iL in the circuit C1 –T1 –T2 –L (Fig. 2). That is, iL (t > t0 ) = −

(1 − k)Udc (t − t0 ). L

(2)

Sufficient energy required for the resonant operation must be stored in the inductor L [Fig. 3(b)]. For a constant discharge current Ip of capacitor Cf , the turn-on instant t0 of transistor T2 precedes the switching-off of transistor T1 at t1 according to the following circuit conditions: iL (t1 ) ≤ Io − Ip .

(3)

Mode 2 [t1 , t2 ]: The transistor T1 turn-off instant at the ZVS conditions initiates a resonant discharge of the input capacitor Cf [Fig. 3(c)]. The capacitor voltage and inductor current are given as follows: uf (t > t1 ) = k · Udc + (iL (t1 ) − Io ) ·

L sin ω(t − t1 ) Cf

+ (1 − k) · Udc cos ω(t − t1 )

(4)

iL (t > t1 ) = (iL (t1 ) − I0 ) cos ω(t − t1 ) −

(1 − k) · Udc sin ω(t − t1 ) + I0 L Cf

(5)

Fig. 3. Equivalent subcircuits for the motor mode. (a) M0. (b) M1. (c) M2. (d) M3. (e) M4. (f) M5. (g) M6. (h) M7. (i) M8. (j) M9. (k) M10.

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Fig. 5. Equivalent subcircuits for the generator mode. (a) M0. (b) M1. (c) M2. (d) M3. (e) M4. (f) M5. (g) M6. (h) M7.

Fig. 4. Transient waveforms at the motor mode: Io = 5 A; Udc = 60 V; and k = 2/3.

where the resonance frequency is defined as ω=

1 . LCf

iL (t > t4 ) =

As iCf ∼ = Ip , an approximately constant rate of change of the capacitor voltage uf is assured (Fig. 4). Mode 3 [t2 , t3 ]: At moment t2 , the capacitor voltage uf = 0. Transistors of the inverter bridge (Tf ) are switched on and T2 is switched off at the ZVS conditions. Load current Io flows through the Df diode, increasing the resonant inductor current in the circuit L–C1 /C2 –D3 . The mode finishes when the inductor current iL crosses the zero value [Fig. 3(d)]. That is, iL (t > t2 ) = iL (t2 ) +

k · Udc (t − t2 ). L

(6)

Mode 4 [t3 , t4 ]: Because the instant t3 positive current iL starts recharging the inductor L, we have iL (t > t3 ) =

k · Udc (t − t3 ) L

while the load current is being fed by two subcircuits consisting of diodes Df and D2 [Fig. 3(e)]. Mode 5 [t4 , t5 ]: As iL > Io , inverter transistors Tf start to conduct [Fig. 3(f)]. During this period, inductor L is loaded to an energy necessary for rebuilding the capacitor Cf voltage and, respectively, to (6) and (7), which yields

(7)

k · Udc (t − t4 ) + Io . L

(8)

Mode 6 [t5 , t6 ]: By switching off Tf at instant t5 , when iL (t5 ) ≥ Ip + Io

(9)

the inverter bridge is set to a new state, and the energy of inductor L is transferred to the resonant capacitor Cf [Fig. 3(g)]. That is, k · Udc iL (t > t5 ) = sin ω(t − t5 ) L Cf

(10) + (iL (t5 ) − Io ) cos ω(t − t5 ) + Io L · sin ω(t − t5 ) uf (t > t5 ) = k · Udc + (iL (t5 ) − Io ) · Cf + k · Udc cos ω(t − t5 ).

(11)


Fig. 6.

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Transient waveforms at the generator mode: Io = −5 A; Udc = 60 V; and k = 2/3.

Mode 7 [t6 , t7 ]: At instant t6 , when the capacitor voltage uf is built up to the voltage-source value Udc , diode D1 is turned on. Discharging of inductor energy is performed in the circuit L–D2 –D1−C1 [Fig. 3(h)]. That is, iL (t > t6 ) = iL (t6 ) −

(1 − k) · Udc (t − t6 ). L

(12)

During this mode, transistor T1 is switched on at ZVS conditions.

Mode 8 [t7 , t8 ]: The current in T1 starts to flow when the inductor current iL is lower than the load current Io . At this period, the inductor current decreases linearly to zero (12) [Fig. 3(i)]. Mode 9 [t8 , t9 ]: In order to balance the capacitor C1 /C2 voltage divider during which transistor T2 is turned on, a recharging inductor current iL is initiated in the circuit C1 –T1 –T2 –L [Fig. 3(j)]. That is, iL (t > t8 ) = −

(1 − k)Udc (t − t8 ). L

(13)

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Fig. 8.

Voltage comparators configuration.

Fig. 9.

Test circuit of the PQRDCLI topology.

Fig. 7. Gate control strategy.

Mode 10 [t9 , t10 ]: After transistor T2 is turned off, the inductor current iL decreases to zero in the circuit L–C2 –D3 [Fig. 3(k)]. That is, iL (t > t9 ) = iL (t9 ) +

k · Udc (t − t10 ). L

(14)

Simulation transients of the above resonant cycle intervals are illustrated in Fig. 4. During the generator mode, the negative load current Io feeds the dc-link circuit [Fig. 5(a)]. This mode is active—continuously for the case of generator-type load transmitting energy from the inverter to dc source or temporarily during bipolar voltage modulation at the reactive energy current pulses recharging input capacitor Cf . Quasi-resonant cycles are controlled by switching state instants of consecutive circuit topologies (Fig. 5). Periods of the M5 and M7 are enlarged to balance an equal charge and discharge of the capacitors C1 and C2 . Simulation transients depicted in Fig. 6 can be described, respectively, as the motor mode equations (2)–(12), assuming a change in the direction of the load current Io . III. C ONTROL S TRATEGY Every operation of the quasi-resonant circuit is initiated by a command signal from the voltage modulator. First, the auxiliary transistor T2 is turned on in advance of the ∆tf period, before disconnecting the main transistor T1 , which is turned off with a constant rate of ∆tf max (Fig. 7). The forward period ∆tf is a linear function of the load current Io , i.e., ∆tf =

L (Ip − Io ). (1 − k)Udc

(15)

After initiation of the resonant cycle, a decrease of the dclink voltage uf to zero is triggered by the voltage comparator Uf _enb as depicted in Fig. 8. Consequently, the return to the inverter rated supply is sensed by the comparator Udc_enb , enabling transistor T1 to be gated on at ZVS conditions. In the motor mode, inverter transistors Tf are gated on during the zero voltage period tZVM to conduct an increasing inductor current iL up to the predetermined limit value (9). Following Fig. 4, we have iL (t5 ) − iL (t2 ) = 2Ip

(16)

hence, tZVM =

L 2Ip . kUdc

(17)

Initiation of modes M9–M10 by a second turned-on instant of T2 is not critical; however, to properly balance the input C1 –C2 divider, the capacitor midpoint voltage control is needed. Similarly, in the generator mode, in order to assure an equal charge and discharge of the capacitors C1 –C2 , the sequencing of M5–M7 (Fig. 6) should stabilize the inductor current iL mean value over the whole commutation cycle at zero value. From this condition, the zero-voltage period tZVG becomes dependent on the load current Io . That is, tZVG =

L 2 (Ip + |Io |) . kUdc

(18)

IV. E XPERIMENTAL R ESULTS The experimental unit consists of the proposed topology of the PQRDCLI circuit fed from a double power supply unit 2 × Udc to enable bidirectional load current tests (Fig. 9). In order to validate the circuit analysis, the three-phase inverter bridge has been replaced by the Tf transistor with the parallel diode Df pair. Loading conditions constitute the series inductor L0 with a half bridge switching leg. The control system is implemented by the fixed-point TMS320F2407A DSP with a gate array logic (GAL) interface. Programming of the DSP is implemented in the C and assembler languages using Texas Instruments assembly language tools. The design range of parameters and specifications were selected for potential automotive applications (Table I). The systematic experimental study has proved that the stable PQRDCLI operation is insensitive to load


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TABLE I PROTOTYPE PQRDCLI POWER STAGE SPECIFICATIONS

Fig. 10. Photograph showing the PQRDCLI laboratory setup.

variations (Fig. 10). Recording of waveforms is realized with the aid of the digital oscilloscope Tektronix TDS 3032 using wideband current and voltage probes. Some key experimental results in Fig. 11 illustrate waveforms of input inverter voltages uf and inductor currents iL corresponding to motor and generator load conditions, respectively. The rate of change of the inverter voltage does not exceed 250 V/µs. The validity and precision of the gate control strategy, as described in Section III, is confirmed.

V. C ONCLUSION A new PQRDCLI, consisting of only two additional transistors, has been proposed for bidirectional applications in the motor and regenerative modes. A systematic study has indicated a high performance of the PQRDCLI operation, which was developed in a relatively simple topological structure. Another circuit feature, independent of energy direction transmission, is a moderate overcurrent/overvoltage stress of components. The control strategy ensures two main objectives: inverter output voltage dU/dt limitation and stable duration of zero voltage interval independent of load current Io at the motor mode operation. A robust gate control strategy has been implemented in a DSP-based solution. In the presented topology, the PQRDCLI

Fig. 11. Input inverter voltage uf and inductor current iL waveforms. (a) Motor mode (Io = +5 A). (b) Generator mode (Io = −5 A).

switches commutate under ZVS or ZCS conditions, assuring a controlled reduction of the rate of change of the inverter voltage, which is expected to limit EMI emissions.

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Slawomir Mandrek was born in Lidzbark Warmiński, Poland, in 1969. He received the M.Sc. degree in power electronics from Gdańsk University of Technology, Gdańsk, Poland, in 1994, where he is currently working toward the Ph.D. degree in power electronics. From 1996 to 2001, he was with the Electrotechnical Institute, Gdańsk Branch. In 2001, he joined the Gdańsk Shiprepair Yard “Remontowa,” Gdańsk. His research interests include power electronics, motion control, new topologies of power converters, and computer simulation.

Piotr J. Chrzan (M’04) was born in Sopot, Poland, in 1954. He received the M.Sc., Ph.D., and Dr.Sc. degrees from Gdańsk University of Technology, Gdańsk, Poland, in 1978, 1988, and 1999, respectively. Since 1980, he has been with the Faculty of Electrical and Control Engineering, Gdańsk University of Technology. He has visited several times the Laboratoire d’Electrotechnique de Grenoble (LEG), Grenoble, France, as an Invited Researcher. He has held several Visiting Professor positions at the Institut National Polytechnique de Toulouse (LEEI-ENSEEIHT), Toulouse, France, and the University of Poitiers (LAII-ESIP), Poitiers, France. He is currently a Professor and the Chair of Power Electronics and Electrical Machines, Gdańsk University of Technology. His research interests include aerospace electrical systems, modeling and control of electrical machines, power converters, and electromagnetic compatibility. He is a member of the Editorial Committee of the Revue Internationale de Génie Electrique.