Real-Time Mitigation of Short-Range Leakage in ... - IEEE Xplore

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2016.2609467, IEEE Transactions on Circuits and Systems II: Express Briefs IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–II EXPRESS BRIEFS, SEPTEMBER 2016

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Real-Time Mitigation of Short-Range Leakage in Automotive FMCW Radar Transceivers Alexander Melzer, Student Member, IEEE, Florian Starzer, Herbert Jäger, Member, IEEE, and Mario Huemer, Senior Member, IEEE

Abstract—Frequency modulated continuous wave (FMCW) radar systems suffer from permanent leakage of the transmit signal into the receive path. Besides leakage within the radar device itself, an unwanted object placed in front of the antennas causes so-called short-range (SR) leakage. In an automotive application, for instance, it originates from signal reflections of the car’s own bumper. Particularly the residual phase noise (PN) of the downconverted SR leakage signal causes a severe degradation of the achievable sensitivity. In an earlier work we proposed a SR leakage cancelation concept feasible for integration in a monolithic microwave integrated circuit (MMIC). In this work we present a hardware prototype that holistically proves our concept with discrete components. The fundamental theory and properties of the concept are proven with measurements. Further, we propose a digital design for real-time operation of the cancelation algorithm on a field programmable gate array (FPGA). Ultimately, by employing measurements with a bumper mounted in front of the antennas, we show that the leakage canceler significantly improves the sensitivity of the radar. Index Terms—Millimeter wave radar, digital integrated circuits, delay lines, MMICs.

I. I NTRODUCTION

I

N contrast to pulse based radar systems, frequency modulated continuous wave (FMCW) based systems suffer from permanent leakage of the transmit signal into the receive path. For leakage within the radar device itself, this issue is known as DC-offset. Several approaches have been proposed to mitigate such [1,2]. Differently, in this work we investigate so-called short-range (SR) leakage. It describes unwanted signal reflections from an object located right in front of the radar antennas. In an automotive application, this kind of leakage originates from signal reflections of the car’s own bumper. Due to the increased propagation delay compared to the DC-offset and the strong reflection in amplitude [3], the residual phase noise (PN) of the downconverted SR leakage signal dominates the overall system noise floor. This leads to a sensitivity and range degradation. Manuscript received June 21, 2016; revised August 24, 2016; accepted September 9, 2016. This work has been funded by the Linz Center of Mechatronics (LCM) GmbH as part of a K2 project. K2 projects are financed using funding from the Austrian COMET K2 program. The COMET K2 projects at LCM are supported by the Austrian federal government, the federal state of Upper Austria, the Johannes Kepler University and all of the scientific partners which form part of the COMET K2 consortium. A. Melzer and M. Huemer are with the Institute of Signal Processing, Johannes Kepler University Linz, 4040 Linz, Austria, email: [email protected] and [email protected]. F. Starzer and H. Jäger are with DICE Danube Integrated Circuit Engineering GmbH & Co. KG, 4040 Linz, Austria, email: [email protected], [email protected].

In [4] we identified the PN to be the major issue within the SR leakage. Specifically in today’s automotive radars, which require high sweep slopes for reasons of resolution, the PN is affected [5]. Consequently, several attempts exist to improve the PN of frequency generating circuits, see e.g. [6]. Nonetheless, these approaches have their limitations, such that leakage cancelation techniques are required. In [7] we proposed a concept to mitigate the SR leakage within a monolithic microwave integrated circuit (MMIC). The concept utilizes an artificial on-chip target (OCT), which makes use of an economically implementable delay line within the circuit. In contrast to [8], the time delay of the OCT is considered with only a fraction of the delay of the SR leakage. Despite this constraint almost perfect leakage cancelation is achieved. This includes the dominant, high-frequent residual PN present in the downconverted intermediate frequency (IF) signal. Ultimately, this improves the overall receiver sensitivity by several decibels and relaxes the design requirements for the OCT delay line. In this work we propose a hardware prototype with discrete components to holistically prove our leakage cancelation concept. We evidence several theoretical findings with measurements. Further, we propose a real-time signal processing architecture for the leakage canceler. Albeit the SR leakage can be considered as a static object reflection, the real-time mitigation is required to efficiently cancel the random, highfrequent PN contained therein. This brings along the benefit of having almost no additional latency for the subsequent signal processing chain. Ultimately, we show that with the proposed cancelation concept the anticipated gain in performance by several decibels is achieved in an automotive radar setting. The paper is structured as follows. Section II briefly summarizes our SR leakage cancelation concept. In Section III the fundamental properties of the leakage cancelation concept are verified by measurements. The real-time digital signal processing architecture is proposed in Section IV. Finally, we present our hardware prototype together with measurement results from the automotive application in Section V. II. S HORT-R ANGE L EAKAGE C ANCELATION C ONCEPT In [7] we showed that the downconverted, ideally lowpass filtered (LPF), and sampled IF signal of the SR leakage signal is given as yS [n] = AS cos (2πfBS nTs + ΦS + ∆ϕSL [n]) .

(1)

Therein, n is the discrete time index and Ts is the sampling interval of the analog to digital converter (ADC). Further, AS

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error (LMMSE) estimator the SR leakage cancelation signal is, based on (1), obtained as

Target reflections Short-range (SR) leakage (AS , τS ) × PA PLL

On-chip target (OCT) (AO , τO )

×

ˆ S + αL ∆ϕOL [n]), yˆS [n] = AˆS cos(2π fˆBS nTs + Φ {z } |

y[n] LPF

LPF

ADC Ts , Toffset yO [n] ADC

Fig. 1. Simplified block diagram of the SR leakage cancelation concept utilizing the OCT.

is a gain essentially defined by the reflected power, fBS is the beat frequency proportional to the distance, ΦS is a constant phase and ∆ϕSL [n] is the residual PN in the IF domain, also termed decorrelated phase noise (DPN). It is the difference between the delayed PN and the instantaneous PN. Its highfrequent noise components dominate the overall system noise floor depending on the PN power spectral density (PSD) and other system parameters [4]. Thus, the radar’s target detection sensitivity and accuracy is degraded. A simplified block diagram of the SR leakage cancelation concept is depicted in Fig. 1. For leakage cancelation, the OCT, which essentially consists of a delay line, is used. It is fed by the FMCW transmit signal from the phase locked loop (PLL). According to the FMCW radar principle, the delayed output signal is mixed with the instantaneous transmit signal. The resulting signal is then lowpass filtered and sampled. Note that the signal processing is equivalent to that of the channel response, and thus to the processed SR leakage. Hence, analogous to (1) we have yO [n] = AO cos (2πfBO nTs + ΦO + ∆ϕOL [n]),

(2)

where AO is a gain determined by the insertion loss of the OCT, fBO is the beat frequency, ΦO is a constant phase and ∆ϕOL [n] is the DPN. Note that in contrast to the SR leakage yS [n], which is contained in the overall channel response y[n], the signal from the OCT path is free from other target reflections or channel noise. Thus, together with the small angle approximation we derived in [7] that the DPN can be approximated from (2) as AO 2

cos(2πfBO nTs + ΦO ) − yO [n] AO 2

sin(2πfBO nTs + ΦO )

(4)

∆ϕ ˆSL [n]

SR Leakage Cancelation (FPGA)

Ts

∆ϕOL [n] ≈

2

.

(3)

Clearly, the quality of this DPN extraction depends on the intrinsic noise present within yO [n]. In [9] we investigate this in detail and show how to optimally choose the delay τO . We found that a minimum delay is required to extract the DPN to ensure a desired signal to noise ratio (SNR). On the other hand, the insertion loss of the delay line as well as the chip area constrain the achievable delay. For SR leakage cancelation, we found in [7] that there is a significant cross-correlation between ∆ϕOL [n] and ∆ϕSL [n], even if τO τS . Thus, with a linear minimum mean square

where AˆS is the expected SR leakage reflection gain, fˆBS is ˆ S is the expected phase. The the expected beat frequency, and Φ DPN scaling factor αL is computed from known circuit design parameters such as the PN power spectrum [7]. Together with the extracted DPN ∆ϕOL [n] it delivers the estimate ∆ϕˆSL [n] of the DPN contained within the SR leakage signal. To summarize, following steps are carried out for the SR leakage cancelation: 1) Extract the DPN from the sampled and lowpass filtered IF signal yO [n] according to (3). 2) Generate SR leakage cancelation signal yˆS [n] as given in (4). 3) Cancel SR leakage as z[n] = y[n] − yˆS [n]. This procedure is carried out thoroughly in the digital domain of the transceiver. From (4) it is important to note that a single sample of the extracted DPN is required to form the cancelation signal. Hence, in order to avoid a massive increase in latency and memory, the DPN extraction as well as the cancelation signal generation are required to be performed in real-time. In our hardware prototype, this is done on a field programmable gate array (FPGA). Prior to presenting the digital design and the hardware prototype in detail, we investigate the fundamental statistical property of our leakage cancelation algorithm. III. C ROSS -C ORRELATION P ROPERTIES OF D ECORRELATED P HASE N OISE In [7] we showed that there is a significant cross-correlation between the DPNs ∆ϕOL [n] and ∆ϕSL [n], even if τO τS . This is the underlying, fundamental property required for the proposed SR leakage cancelation concept. In this section we evidence this cross-correlation based on measurements from the PLL. As will be described in detail in Section V, we use the Analog Devices EV-ADF4159EB1Z evaluation board to generate the FMCW transmit signal for our prototype. For the analysis in this section we configure it to generate a chirp between 11.4 GHz and 11.7 GHz within a duration of 100 µs. We sample the output signal with a scope at a rate of 80 GHz and 8 bits of vertical resolution, and process the data further on a PC. To suppress the quantization noise, we set the frequency components outside the interval of 10.4 to 12.7 GHz to zero, which is 1 GHz below/above the chirp start/stop frequency. This preprocessed transmit signal is delayed by different delays τO and τS , and multiplied with the undelayed signal according to the FMCW radar principle. The image originating from the mixing process is removed with a lowpass filter. From this lowpass filtered IF signals, the DPNs ∆ϕOL [n] and ∆ϕSL [n] are extracted according to the algorithm proposed in [9]. As mentioned already, this extraction is analytically given by (3).



We now aim to find the cross-correlation between ∆ϕOL [n] and ∆ϕSL [n]. Assuming both to be zero-mean, their normalized, continuous time cross-covariance is E{∆ϕOL (t) ∆ϕSL (t + u)} q , 2 2 σ∆ϕ σ OL ∆ϕSL

1 0.8 0.6

(5)

2 2 where σ∆ϕ and σ∆ϕ are the variances of the two DPN OL SL processes. For the cross-correlation analysis, we keep the delay τS = 887 ps fixed and let τO = {150 ps, 412 ps, 587 ps, 712 ps, 887 ps}. The resulting numerical approximation of (5), based on the extracted DPN signals from the measured PLL output, is depicted in Fig. 2. Clearly, for τS = τO = 887 ps there is a crosscorrelation of 1 at zero lag. Most importantly, however, there is a significant cross-correlation even for decreasing τO . This correlation is maximized when evaluated at the optimum lag τS − τO . (6) uopt = Toffset = − 2 This result was analytically derived in [7] and perfectly matches the measurements given in Fig. 2. The optimum lag is applied to the leakage cancelation by delaying the sampling clock of the channel receive path, indicated by Toffset in Fig. 1. To accomplish this delay in our hardware prototype, we use a phase shifted version of the digital system clock, which is provided by a PLL. Concluding, we observe that the cross-correlation is not as high as found in [7], wherein a normalized cross-correlation of 0.94 is observed, even for τS /τO = 20. There are mainly two restrictions causing this. Firstly, the measurements are done with an oversampling factor of 80 GHz/11.7 GHz ≈ 7 only. Hence, the DPN extraction cannot be carried out with highest accuracy as it would require the downconverted IF signal to be evaluated around its zero crossing [9]. This is also why the delays for τO and τS in Fig. 2 are non-equidistant, yet not optimal. Secondly, the vertical resolution is very low with 8 bits only. Note, that also the uncorrelated noise between the two mixers could falsify the cross-correlation results. However, since we use passive mixers, the thermal noise added by the two mixers is negligibly small. In conclusion, with the analysis of this section we are able to evidence that there exists the anticipated cross-correlation, suggesting to implement the leakage cancelation in the anticipated way.

IV. D IGITAL D ESIGN ON FPGA In this section we present the real-time implementation of our SR leakage cancelation concept on an FPGA. An overview of the architecture is provided in Fig. 3. We split the discussion into the three steps pointed out in Section II. A. Decorrelated Phase Noise Extraction In this first step the DPN extraction from the input signal yO [n] is carried out according to (3). The sinusoidal parameters fBO and ΦO can be computed readily from known design parameters, which are optimized according to [9]. For generation of the required sine and cosine we utilize

ρ∆ϕO ∆ϕS (u)

ρ∆ϕOL ∆ϕSL (u) =

3

τO τO τO τO τO

= 150 = 412 = 587 = 712 = 887

1

1.2

ps ps ps ps ps

0.4 0.2 0 −0.2 −0.4 −0.6 −1.2 −1 −0.8 −0.6 −0.4 −0.2

0 0.2 0.4 Lag u [ns]

0.6

0.8

1.4

Fig. 2. Estimated normalized cross-covariances for various τO and a fixed τS = 887 ps, obtained from the measured PLL output signal. A significant cross-correlation is observed at the optimum lag uopt , even if τO τS .

the coordinate rotation digital computer (CORDIC) algorithm. For the problem at hand it is a highly beneficial hardware architecture. Since the arguments of the sine and cosine in (3) are equal, a single CORDIC instance is sufficient to retrieve their respective values. Clearly, due to the iterative nature of the CORDIC, the inputs have to be supplied already Niterations clock cycles earlier, where Niterations is the total number of iterations required for one CORDIC rotation. To obtain new values with each time step, a pipelined structure of the CORDIC is implemented. B. Short-Range Leakage Cancelation Signal Generation The SR leakage cancelation signal is generated according to (4) incorporating the DPN extracted in the previous step. Again, we use the CORDIC algorithm. However, in contrast to the previous step, the argument of the sinusoid now incorporates the random phase input given by αL ∆ϕOL [n]. Due to the iterative nature of the CORDIC, the respective output value would be valid Niterations clock cycles later. Although there exist many contributions to reduce the number of required CORDIC iterations [10,11], we use an approximation to avoid this latency issue at all. Since ∆ϕˆSL [n] is sufficiently small, we can approximate (4) as AˆS ˆS) yˆS [n] ≈ cos(2π fˆBS nTs + Φ 2 AˆS ˆ S ) ∆ϕˆSL [n]. − sin(2π fˆBS nTs + Φ (7) 2 Note that with this approximation the CORDIC can be computed with a constant phase increment as input and thus the delay in the signal processing chain by Niterations cycles is avoided. Furthermore, the multiplication of the sin(·) term and αL can be precomputed as shown in Fig. 3. As for the DPN extraction, both the sine and cosine required in (7) are output by a single CORDIC instance. In this work we consider the application specific parameters AS and τS to be known. Thus, together with some other ˆ S as well as the system parameters the estimates fˆBS and Φ DPN scaling factor αL can be computed readily.



y[n] Channel IF

ADC Ts

y[n − 3]

z −3

ADC Ts , Toffset

OCT IF

-

+ +

z −1

z −1

z −1

cos(·)

CORDIC

/

+

SR leakage cancelation signal generation

DPN extraction yO [n]

4

∆ϕO [n − 2]

-

× z −1

z −1

+ +

z[n]

yˆS [n − 3]

z −1

sin(·)

AO /2, fBO , ΦO

+ -

cos(·)

× αL

sin(·)

CORDIC

ˆS AˆS /2, fˆBS , Φ

Fig. 3. Digital design concept for SR leakage cancelation in real-time.

C. Leakage Cancelation The final step is to subtract the generated SR leakage cancelation signal from the channel IF signal y[n]. This subtraction is critical with respect to timing. As found in Section III, the DPN terms from the OCT (∆ϕOL [n]) and SR leakage (∆ϕSL [n]) are correlated for relative time shifts of a few hundred picoseconds only. For leakage cancelation it is thus crucial to subtract samples that were drawn from the two ADCs at the same time instant. Specifically, due to the digital processing delay required for DPN extraction (2 clock cycles) and the SR leakage signal generation (1 clock cycle), the channel IF signal needs to be delayed by 3 clock cycles, indicated by the z −3 in Fig. 3. This ensures that the subtracted values for leakage cancelation originate from the two ADC samples drawn at the same time instant up to the sampling clock shift by Toffset .

ADCs

Channel mixer Reference input

PA

OCT mixer

V. H ARDWARE P ROTOTYPE AND M EASUREMENT R ESULTS A. Hardware Prototype In this section we propose the hardware prototype for our SR leakage cancelation concept. It is built as depicted schematically in Fig. 1. For generation of the FMCW transmit signal we use the Analog Devices EV-ADF4159EB1Z evaluation board. It integrates the ADF4159 fractional-N frequency synthesizer and a voltage controlled oscillator (VCO) capable to generate output frequencies from 11.4 GHz to 12.8 GHz. To control the PN, the on-board crystal oscillator is bypassed and instead an external 20 MHz reference clock is supplied. The nominal signal output power of the VCO is 3 dBm. Since we use passive mixers, the VCO output signal is first amplified with a power amplifier (PA) to 18 dBm. This signal is then split by three Wilkinson dividers, which, due to their beneficial architecture, provide sufficient reverse-isolation. The four output paths from the dividers have a power of about 12 dBm each. Two of these paths are immediately fed into the local oscillator (LO) ports of the passive mixers. The other paths are fed into the transmit antenna and into a short coaxial cable representing the OCT. The respective outputs are connected to the radio frequency (RF) ports of the mixers. The two passive mixer IF outputs are lowpass filtered and subsequently feed the ADCs. Those are connected using an

Fig. 4. Picture of the hardware prototype together with the FPGA and the extension board providing the ADCs.

extension board to the FPGA. The chosen sample rate is fs = 100 MHz, and the vertical resolution is 14 bits. The FPGA carries out the digital signal processing as discussed in Section IV. The hardware prototype is depicted in Fig. 4 together with the FPGA and the extension board providing the ADCs. Therein the SR leakage is modeled with a coaxial cable, which we used in a first step to test our SR leakage cancelation. B. Measurement Results We now employ a real-world scenario in an automotive application. For that, we transmit and receive the radar signals using horn antennas. The antennas are mounted right behind a bumper coated with metallic paint. The measurement setup is depicted in Fig. 5. The FMCW transmit signal has a start frequency of 11.9 GHz, and the chirp bandwidth and duration are 900 MHz and 100 µs, respectively. Note that state of the art automotive radars have a much higher PN since they transmit at much higher frequencies. To compensate for this,



5

of the system. In Fig. 6 this becomes clear by observing the dashed line, which describes the expected DPN PSD of the SR leakage. It is determined as [7,12] S∆ϕS ∆ϕS (f ) = 2 Sϕϕ (f ) (1 − cos(2πf τS )),

Fig. 5. Picture of the hardware prototype with a car bumper mounted in front of the radar antennas.

Residual signal components from SR leakage −100

−110

Without SR leakage cancelation With SR leakage cancelation Expected DPN PSD of SR leakage S∆ϕS ∆ϕS (f )

where Sϕϕ (f ) is the PLL PN which was measured with a spectrum analyzer. Concluding, we note that based on this analysis the SR leakage cancelation is neither possible nor required for frequencies above 2.6 MHz in our particular case. Clearly, for a different PN PSD this immediately alters. Finally, note that we considered the SR leakage to be a reflection as from a point target. Measurements of the IF signal from our hardware prototype show that this is a valid assumption, since one major signal contribution with beat frequency fBS is indistinguishable contained therein. Clearly, this signal contribution is not perfectly sinusoidal. Thus, as is shown in Fig. 6, residual signal components close to DC remain in the canceled PSD. VI. C ONCLUSION We proposed a prototype to prove a novel concept to holistically mitigate SR leakage in FMCW radar transceivers. The leakage cancelation is performed in real-time on an FPGA requiring solely two CORDIC instances, and a few adders and multipliers. A significant gain in sensitivity is achieved.

Object reflections PSD [dBm/Hz]

(8)

−120

−130

R EFERENCES −140

−150

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8 Frequency [MHz]

2

2.2 2.4 2.6 2.8

3

Fig. 6. PSD estimates of IF signals with and without SR leakage cancelation, averaged over 4 chirps. With the proposed leakage cancelation technique up to 5 dB in sensitivity is gained.

the reference input signal of the PLL is modulated with PN to achieve −80 dBc/Hz at an offset of 1 MHz at the transmitter output. This approximately resembles the performance of a state of the art 77 GHz radar. The coaxial cable representing the OCT has a length of 12.7 cm. Together with a relative dielectric constant r = 2.25, the delay results to τO = 507 ps. From measurements we determined τS = 3778 ps (fBS = 34 kHz). Hence, the OCT delay is more than seven times smaller compared to the actual delay of the SR leakage (τS /τO = 7.5). With the two delays τS and τO , the optimum sampling offset is determined as Toffset = −1635 ps according to (6). Further, the optimum DPN scaling factor evaluates to αL = 7.34 [7]. The IF power spectra with and without SR leakage cancelation are depicted in Fig. 6. It is observed that with the proposed technique up to 5 dB in sensitivity is gained. Along with this, the objects within the channel can be detected more precisely due to the suppressed noise. Note that the leakage cancelation improves the sensitivity up to frequencies of around 2.6 MHz, since for higher frequencies the DPN contained in the SR leakage is below the noise floor

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