Receiver/Transmitter Input/Output Termination ... - IEEE Xplore

2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO)

Receiver/Transmitter Input/Output Termination Resistance Calibration Method Vazgen Melikyan, Abraham Balabanyan, Artak Hayrapetyan, Nazeli Melikyan Department of Microelectronics State Engineering University of Armenia Yerevan, Armenia [email protected], [email protected], [email protected], [email protected] In proposed configuration, the transmission line impedance is assumed 50-Ohm (Z0=50 Ohm). To avoid reflections, 50Ohm terminations in the near and far ends of the line are required.

Abstract—A method of receiver and transmitter input/output resistance calibration, using external reference resistor is presented in this paper. The proposed architecture produces a calibration code corresponding to 50-Ohm PVT compensated termination impedance, which is needed to avoid reflections in transmission lines. The presented calibration mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.

The proposed calibration method provides relatively constant 50-Ohm termination impedance in the driver output and the receiver input for all PVT [3] conditions. II.

Keywords—receiver; transmitter; resistance calibration; PVT compensation; reflection

The structure of proposed Input/Output termination resistance calibration circuit is presented in Fig. 1.

INTRODUCTION

Compensation circuit contains both analog and digital blocks. An external 200 Ohm high precision resistor (4 times the design target 50 Ohm impedance) and an integrated reference current generator [4] (which provides 3.25 mA DC current) are used for compensation. Current switch block consists of current mirrors with three branches (Fig. 2). Each of them is controlled by switches implemented with transmission gates (TG) [5]. The same reference current flows through all current mirror branches.

In high speed systems and interfaces signal delays in PCBs (Printed Circuit Board) [1] long lines are an important factor and their effects cannot be ignored. When delays in interconnects are commensurable with signal transition times, they are considered transmission lines [1]. One of the main factors limiting the operating frequency of high speed devices are the I/Os and their transmission lines. Signal termination [2] is required to reduce voltage reflections. Excessive transmission line reflections can cause random logic falsetriggering. As a result of the mentioned phenomena, the system may fail to function under some operating conditions such as high temperatures or over-voltages.

TX/RX

In general, the amplitude of the wave reflected at the end of a transmission line is determined by the reflection coefficient, ρ.

where Z0 is the characteristic impedance of transmission line, Zterm is the termination resistor in the far end of line.

Iref

Reset LOGIC MODULE

Write

(1)

Current Switch Vswitch [2:0]

Rext = 200 Ω

Vcal[6:0]

ITX IRX

Iext

Vext

Vcomp

As it is seen from (1), in order to have no reflections (ρ=0), termination resistance and Z0 must be matched (i.e., the same). If source impedance does not equal Z0, then reflections occur at the near end of the line as well. Each end of the line has its own value of ρ.

TX Replica

32X 16X 8X 4X 2X X

+ Comparator

RX Replica

MUX

Vcal[6:0]

When a voltage wave with amplitude Vwave hits the end of transition line, a wave with amplitude ρVwave is reflected.

978-1-4673-4672-6/13/$31.00 ©2013 IEEE

Integrated Reference Current Generator

Register

Vcal[6:0]

I.

CALIBARATION CIRCUIT ARCHITECTURE

Vact

-

Vswitch [2] 32X 16X 8X 4X 2X X

Fig. 1. I/O termination resistor calibration circuit structure.

126

Vcomp


IRX

R=32X

R=16X

Vcal _5

Vcal _4 R=4X

R=2X

R=X

R=64X

TX and RX replica blocks duplicate the actual transmitter and receiver input/output termination resistor circuits with one difference – total resistance of the replica blocks is four times higher than that of the actual ones.

Fig. 4. RX replica circuit.

In Fig. 3 a block diagram illustrating the structure of high speed links is presented. It consists of transmitter (TX) output resistance and output buffer, transmission line (which is typically 50 Ohm for PCBs) and receiver (RX) with its input termination resistance block. The ordinary TX is a buffer and RX is a differential amplifier.

Each replica block contains parallel connected resistors and control transistors which can operate in cut off or triode regions. All resistors which are active in any situation define the cumulative resistance of RX or TX replica. Since these resistors are controlled by binary calibration signals (which come from logic block), each block has a resistance two times smaller than the next one. In proposed solution replica circuit contains seven blocks with resistors: for example, the first block has the smallest resistance and contains 32 X resistors connected in parallel, the sixth one contains only one resistor with the same X value and has the highest resistance. As it is mentioned above RX replica consists of resistances groups connected in parallel. The MSB [5] binary code connected to the smallest resistance group (with 32 resistances connected in parallel) in replica (R=32X) and LSB [5] to the highest resistance group of replica (R=X). To avoid excessively large resistances of Rcal, there is also a block of resistance which is always on and has the smallest resistance (R=64X). RX replica block is presented in Fig. 4.

In the process of calibration a binary code is obtained from replicas, which sets 50 Ohm on the TX output and the RX input. The replica resistances (200 Ohm) are four times higher than termination ones in real high speed links, so if the same binary code is applied to the pull up/pull down resistance section of TX and input resistance of the RX, 50 Ohm resulting impedance will be achieved. In this case there will not be reflection in transmission lines (Fig. 3).

Binary_TX [5:0]

R=8X

Iext

Fig. 2. Current switch circuit.

Pull up

Z0=50 Ω

Calibration circuit provides about 200 Ohm constant resistance in replica circuits for all PVT conditions. Usually resistance variations can reach up to ±50 Ohm so in typical case it is required to have at least 150-250 Ohm resistance range during calibration. This fact is used to choose a resistor value in each block of replica. In proposed solution the block which is always open has 300 Ohm resistance (64X=300 Ohm). So when binary code is zero (Vcal=000000) the total resistance is about 300 Ohm. When all blocks are open (Vcal=000000) the total resistance is about 150 Ohm. It is important to have about 200 Ohm replica resistance value in typical case for the middle input binary code. This condition is also provided in proposed architecture (when Vcal=000000, Rcal=200 Ohm).

RX

Binary_TX [5:0]

Binary_RX [5:0]

Data

Vcal _3

Vcal _2

Vcal _1

Vcal _0

Vcal[6:0]

Iref

vddq

ITX

Vswitch[0]

Vswitch[1]

Vswitch[2]

Rcal

Pull_down

Fig. 3. Structure of high speed link.

127


Binary code vddq

changes RX replica resistance. Calibration precision depends on number of calibration bits (the higher is number of bits, the more accurate is calibration). During calibration replica resistance starts from the highest value (Vcal=000000). In these conditions in the replica resistance is about 300 Ohm. At the end of calibration the resistance of replica is minimum because all resistor blocks are open and connected in parallel (Vcal=111111). For such combination the replica resistance falls to about 150 Ohm. Number of calibration steps in proposed solution is 63.

Binary code

R=X

R=X

(a)

(b)

Nstep=2n-1,

Fig. 5. a) TX replica single resistor block, b) RX replica single resistor block.

where Nstep is the number of calibration steps and n is the bit number of input calibration signal. The positive input of comparator has constant value Vext which is the voltage drop of external 200 Ohm resistor (Vext=200Iref). Current in RX replica is constant as well and equal to Iref but its actual resistance decreases during calibration. So the voltage drop of RX replica decreases which, in the meantime, is the voltage on negative comparator input. When the actual voltage of replica reaches the external reference voltage (Vact=Vext) comparator output switches from logic “0” to logic “1“ (Vcomp=1). This is the case when the actual resistance of RX replica becomes equal to resistance of reference external resistor (IrefVact = IrefVref => Rreplica=200Ω). By the positive value of Vcomp the logic module stops decreasing calibration code (Vcal) and stores fixed code in the register. This code is transferred from register to the actual input termination resistance block of receiver and provides its fixed 50 Ohm resistance (one quarter of RX replica). To fix the right calibration code it is important that the delay between calibration code bit changes be bigger than the summary of comparator and multiplexer delays.

The principle of calibration used for TX and RX replica circuits is the same, with a little difference: as in TX the output termination resistance block is a part of driver circuit, there should be two transistors on both pull up and pull down paths. The first transistor serves for data input and the second one is controlled by a binary code obtained from TX replica. For TX only pull down circuit is used in replica block. After calibration the same binary code will be given to TX pull up circuit. Actually each resistor in TX replica block is presented as two NMOS transistors and a resistor connected in series (Fig. 5a). The first transistor gets binary code while the second gets the highest potential and is always open (this transistor is added to have similar conditions with real TX output resistor). The single resistor block of RX replica is presented as NMOS transistor (with binary input) and a resistor connected in series (Fig. 5b). In I/O termination resistor calibration circuit block diagram a logic module block, register, multiplexer and comparator are also used. Logic module provides all digital input signals such as calibration binary code (Vcal), switch signal (Vswitch) controlling current switch block and multiplexer, write and reset signals to write data or reset register (where calibration final code is saved). Comparator compares calibration voltage of replica with external reference voltage. Output voltage of comparator (Vcomp) is applied to logic module as an input. III.

(2)

RX_cal Vswitch [2:0] = 011

TX_cal Vswitch [2:0] = 101

Vcal [5:0] = 0000000

Vcal [5:0] = 0000000

OPERATION PRINCIPLE AND COMPENSATION

For RX and TX input/output termination resistance calibration RX replica and TX replica circuits are used. As it is mentioned above replicas are added for simple and fast simulation. They have the same structure but four times bigger cumulative resistance than RX and TX termination resistance blocks.

NO

Vcomp

YES

>> Vcal

YES NO V comp >> Vcal

Write to Register

The proposed principle of termination calibration method is presented as a block diagram in Fig. 6. The calibration starts from RX: A 3-bit signal, generated in logic module, is used to control the current switch block, turning it into RX mode. This means that no current flows through TX Replica (Vswitch=011). So reference current generated by integrated reference current generator flows through RX replica and the external resistor. The Vswitch signal controls multiplexer and enables path for actual voltage of RX replica to comparator. In the next phase logic module starts increasing 6-bit calibration code (Vcal) and

RX

Reset Register

Write to Register

TX Power Down Vswitch [2:0] = 000

Fig. 6. Algorithm of calibration method.

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2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO) After RX calibration the logic module resets register and starts calibration of transmitter. Logic module changes Vswitch signal (Vswitch=101) and switches current switch block to TX mode which means that no current flows through RX replica. In TX replica the same principle is implemented as it was in RX replica calibration. When the output of comparator switches the calibration binary code is being fixed, written to register and transferred to actual transmitter pull up/pull down sections providing their fixed 50 Ohm termination resistance value. After receiver and transmitter termination resistance calibration is completed, the function of this circuit is finished and it does not affect the RX and TX operation. It should be noted that the compensation circuit uses large currents: two branches of current switch block are always open so they consume approximately 6.5mA current. To reduce power consumption the compensation circuit is switched to power down mode by logic module. It is performed by Vswitch signal, which deactivates all TGs of three branches in current switch block (Vswitch=000).

IV.

Fig. 8. RX replica calibration results for slow corner.

SIMULATION RESULTS

Simulations have been performed using circuit level simulator Hspice[6] for 65 PVT corners, including SS (slowslow), TT (typical-typical), FF (fast-fast), SF (slow-fast), FS (fast-slow) with supply voltage and temperature variations. Fig. 7 shows RX replica calibration results for TT(55O) typical corner. It is seen that comparator switches to logic “1” when the actual voltage of RX replica equals to reference voltage and actual resistance of replica becomes about 200 Ohm (Ract=200.83 Ohm). Calibration is finished approximately in the middle of binary code (Vcal=100000 and Ni=32 for ideal case) at 33rd step of binary code, so in this case Vcal=100001 and Ni=33 (Ni is the step index of calibration binary code).

Fig. 9. RX replica calibration results for fast corner.

Fig. 8 and Fig. 9 show calibration simulation results for, respectively, SS(125O) and FF(-40O) main PVT corners. It is seen from waveforms that in slow case RX replica resistance reaches 200 Ohm for higher Vcal code values. In this case Vcal=110010, Ni=50 and Ract=197.71 Ohm (Fig. 8). In fast corner the calibration is finished more quickly and results for this case are the following: Vcal=000111, Ni=7 and Ract=201.25 Ohm (Fig. 9). TX replica calibration waveforms are similar. RX replica actual resistance waveforms (presented in Fig79) are obtained by dividing replica’s actual voltage (Vact) to the current flowing through it (IRX). As it is seen from waveforms the voltage step during calibration is not ideally constant. Step changes in a range (4-10)mV. The reason of this, is not ideally constant behavior of the reference current. An important parameter for calibration is the comparator sensitivity [5]. For calibration a comparator with sensitivity smaller than 1mV is designed. So calibration (4-10)mV voltage steps can easily be detected by comparator.

Fig. 7. RX replica calibration results for typical corner.

129

2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO) Ni(TX)=54

Ni(TX)=36

power of compensation circuit is approximately 12.4mW and obtained from the following equation:

Ni(TX)=24

Wavg=VvddqIvddq+VvddIvdd,

(3)

where Wavg is the average power of compensation circuit, Vvddq is the supply voltage of analog blocks, Vvdd is the supply voltage of digital blocks, Ivddq and Ivdd, respectively, are the currents flowing through analog and digital power sources. TABLE I. Ni(RX)=50

Ni(RX)=33

Ni(RX)=7 PVT corner

SS(125O)

Ract(TX)=195.88Ω

Ract(RX)=197.71Ω

TT(55O)

Corner

SIMULATION RESULTS OF THE THREE MAIN CORNERS FOR TERMINATION ACTUAL VALUE. RX Replica

TX Replica

FF(-40O)

Ract(TX)=200.04Ω Ract(TX)=203.48Ω

Unit

Ract (Ω)

TT(55)

200.83

SS(125) FF(-40)

Var. (%)

Ract (Ω)

Var. (%)

0.4

200.04

0.02

197.71

1.16

195.88

2.1

201.25

0.63

203.48

1.74

V.

Ract(RX)=200.83Ω Ract(RX)=201.25Ω

CONCLUSIONS

A calibration method for receiver/transmitter input/output termination resistance is proposed and the respective circuit designed. Calibration system generates a digital code obtained from replica circuit calibration, both for driver and receiver. The proposed method provides 200 Ohm PVT compensated termination resistances with 2.1% maximal variation from the reference value. Without compensation variation of CMOS resistors can reach about ±20% due to PVT variations. Calibration is performed prior to RX/TX activation and has 3.2µs duration. Maximal power consumption of the designed circuit is approximately 12.4mW. Main disadvantage of the proposed solution is the necessity of an external 200 Ohm (±0.01%) reference resistor.

PVT corner

Fig. 10. Dependence of RX/TX replica calibration step index (Ni) and after calibration actual resistance (Ract) from 65 simulation PVT corners.

Fig. 10 shows the dependence of RX and TX replica calibration step index (Ni) and after calibration actual resistance (Ract) from 65 simulation PVT corners. Three main cases for RX replica discussed above are highlighted in the waveforms. From waveforms shown in Fig. 10 it is seen that the worst conditions of termination calibration both for TX and RX are two extreme cases: variation of resistance is maximum in SS(125O) and FF(-40O) PVT corners. Three main cases for TX and RX replica calibration results are circled in the waveforms (the circles showing RX results are filled, other ones are empty).

REFERENCES [1]

Simulation results of the three main corners for termination actual value using proposed calibration method are presented in Table I. The results show that termination resistance variation of transmitter is a little higher than variation of receiver (up to 2.1%). The result of this is the fact that TX replica resistor block is a little more complicated and contains one extra transistor which is always on during calibration.

[2]

[3]

The blocks which define main power consumption of the compensation circuit are RX/TX replicas, the external resistor (each of them uses approximately 3.25mA current and their supply voltage is 1.8V) and comparator (with average current approximately 400uA and supply voltage 1.8V). Logic block has small currents and 1V nominal supply voltage. Average

[4]

[5] [6]

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