Reduced Multilevel Converter: A Novel Multilevel ...

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IEEE, Jose Rodriguez, Fellow Member, IEEE. Abstract—This paper presents a new multilevel converter topology based on a variable or multilevel dc-link stage.
Reduced Multilevel Converter: A Novel Multilevel Converter with Reduced Number of Active Switches Margarita Norambuena, Member, IEEE, Samir Kouro, Senior Member, IEEE, Sibylle Dieckerhoff, Member, IEEE, Jose Rodriguez, Fellow Member, IEEE

Abstract—This paper presents a new multilevel converter topology based on a variable or multilevel dc-link stage. This stage is shared by all inverter output phases, thus increasing the number of output voltage levels while reducing the overall number of active devices compared to traditional topologies, and therefore called Reduced Multilevel Converter (RMC). The converter is not capable of reducing the blocking voltage of the devices, hence unlike other multilevel converters aimed at medium voltage applications, this converter is interesting for low voltage and high power quality demanding applications such as photovoltaic inverters, wind energy conversion systems and UPS. The main novelty behind the proposed concept is the basic DCcell used to generate the variable dc-link voltage, which includes a controlled path through the floating capacitors to provide the necessary degree of control to enable a shared multilevel dc-link for all the output phases of the converter. The DC-cells are connected in a multicell structure to increase the number of levels of the converter. A five-level version of the RMC topology is briefly compared to other five-level converters such as the five-level Active Neutral Point Clamped (5L-ANPC) and five-level Flying Capacitor Converter (5L-FCC). This paper presents the structure of the new topology with its operating principle, switching states, main characteristics, and experimental validation using finite control set model predictive control. Index Terms—Multilevel Converters, Variable dc-link, DCAC power conversion, Model Predictive Control

I. I NTRODUCTION HREE PHASE Voltage Source Inverters (VSI) are among the most widely used power converters in industry. They have been extensively used in motor drive applications of all power ratings, and in the last decades have found an increasing industrial presence in grid connected applications such as distributed energy systems, wind and photovoltaic energy conversion systems, uninterruptible power supplies (UPS), and electric vehicle fast charging stations, to name a few [1]–[5].

T

Copyright (c) 2017 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to [email protected]. This work was supported by CONICYT/FONDECYT Research Project 1170167, by CONICYT/Doctorado Nacional/2014-21140574, by DAAD/Bi-nationally Supervised Doctoral Degrees/57129430 and by AC3E CONICYT-Basal Project FB0008. M. Norambuena is with Universidad Andres Bello, Facultad de Ingenieria, Santiago, Chile, and also with the Fakultat IV - Elektrotechnik und Informatik, TU Berlin, Germany, and with the Departamento de Electronica, UTFSM, Valparaíso, Chile. e-mail:[email protected]. S. Kouro is with the Departamento de Electronica, UTFSM, Valparaíso, Chile. e-mail: [email protected] S. Dieckerhoff is with the Fakultat IV - Elektrotechnik und Informatik, TU Berlin, Germany. e-mail: [email protected] J. Rodriguez is with Universidad Andres Bello, Santiago, Chile. e-mail:[email protected].

The most simple and widespread VSI topology is the twolevel VSI (2L-VSI) based on three half-bridge inverter legs with a common dc-link. However, the 2L-VSI is mainly used in low voltage operation, due to the device blocking voltage limits, and poses a design trade-off between device switching frequency (impact on efficiency), filter size (impact on size and cost) and power quality, to meet recent more demanding grid codes for grid-connected applications. On the other hand, multilevel VSIs emerged initially as a solution to overcome the blocking voltage limit of 2L-VSI, and enable VSIs for medium voltage applications, previously dominated by current source inverters. This also came with the added benefits of reduced dv/dt, higher efficiency due to lower switching frequency, and improved power quality due to more sinusoidal wave forms [6]. The later also made a positive impact on the output filter size and cost. Different topologies of multilevel converters have found industrial application: the neutral point clamped (NPC) [7], [8], the cascaded H-bridge (CHB), the flying capacitor converter (FCC) [9], the active neutral point clamped (ANPC) with [10] and without output flying capacitor cell, the stacked multicell (SMC) [11], the Hbridge NPC (H-NPC), the T-type or neutral point piloted (NPP) [12], and the modular multilevel converter (MMC). These topologies cater a wide spectrum of applications, have different voltage and power ratings, and have unique advantages and disadvantages. All these converters were primarily devised to reach medium voltage operation (typically 2.3, 3.3, 4.16, 6.6 and 10kV) and high power (>1MW). Therefore, the device blocking voltage (to reach medium voltage), the switching frequency (for efficiency) and the number of voltage levels (for power quality) were the main drivers behind the research and development efforts in multilevel converter topologies. More recently, multilevel converters have made a strong entrance in the low voltage market (typically below 690V), particularly for wind and photovoltaic energy conversion systems, UPS, and EV fast charging stations. Since the device blocking voltage is not an issue in this voltage range, the main driver behind this trend is the more demanding grid codes, the filter size reduction and the increased efficiency, which are directly or indirectly achieved by the more sinusoidal multilevel voltage waveforms. However since these applications are reaching quite high power levels (e.g. several wind turbines above 5MW, central PV inverters above 2MW), they require several converters operating in parallel, multichannel or interleaved mode. In fact some PV inverters have up to 12 converters (four per phase) to reach 2MW. In these cases

a reduction in the number of active devices and capacitors for each individual converter could translate in cost reduction, higher power density and less failure probability (less gate drives and capacitors). This paper proposes a new multilevel converter topology which reduces the number of power switches and capacitors to generate the same or more number of output voltage levels as traditional multilevel converters. The operating principle is based on a variable multilevel dc-link voltage which is shared by all the phases of an output inverter stage. The variable dc-link is generated by a multicell arrangement of DC-cells which have a controlled current path through a floating capacitor. Combinations of several DC-cells at the dclink can increase the number of voltage levels generated at the ac side, without increasing the number of active devices proportionally to the three phases, hence the name reduced multilevel converter (RMC). In particular the paper explores the five-level configuration using three DC-cells and a 2L-VSI output stage. It is compared with the five-level ANPC and FCC since they also feature five levels, and a single DC source (NPC and NPP have three levels, and the CHB and HNPC have more independent dc sources). Experimental results of a laboratory prototype controlled with finite control set model predictive control (FCS-MPC) are presented to provide a preliminary validation of the proposed topology. II. R EDUCED MULTILEVEL CONVERTER TOPOLOGY The RMC topology [13] is composed by a variable dclink followed by a three-phase output inverter stage. A 5-level configuration is shown in Fig. 1 made by the combination of three DC-cells and a single 2L-VSI output stage. The variable dc-link or multilevel dc-dc converter is a modular multicell structure, much like the FCC and SMC; this means that it is possible to increase (reduce) the number of levels by connecting (disconnecting) DC-cell units following the multicell arrangement. The generic circuit of the proposed DCcell is shown in Fig. 2. Every DC-cell is formed by three power switches and one capacitor; their allowed switching states provide a path that connects the capacitor of the DCcell in a way that it adds, subtracts, or bypasses the capacitor voltage respect the previous cells, going from the dc source VDC to the dc-link terminals p and n. The output inverter stage is in charge of connecting the output phase terminals to a potential of the dc-link. It can be any inverter with a single dc-bus configuration like the 2L-VSI, NPC, ANPC, T-type, FCC and SMC. However, in this paper, the 2L-VSI is used for simplicity, which can connect each output phase to the variable dc-link voltages: vpN or vnN . A. Switching states Every DC-cell has three allowed switching states which are listed in Table I, where Spk = 1 means that the power switch pk is ON and Spk = 0 means that it is OFF, for all power switches Spk , Snk and SCk . Therefore, each DC-cell incorporates three allowed additional switching states to the multilevel dc-dc converter stage. Thus the total allowed switching states can be expressed as

TABLE I: RMC DC-cell allowed switching states Switching State Spk Snk SCk 1 0 1

1 1 0

0 1 1

Output Potential vo−(k) vo+(k) vo+(k+1) vo−(k+1) + vck vo+(k+1)

vo−(k+1) vo−(k+1) vo+(k+1) − vck

a function of the number of DC-cells (NDC−cell ), given by NDC−states = 3NDC−cell . In the case of the RMC shown in Fig. 1, there are three DC-cells and therefore the allowed switching states for the multilevel dc-dc stage are 33 = 27. For the dc-ac 2L-VSI output stage, the half-bridge leg is composed of two switches working in a complementary way, when Sx = 1, i.e. it is ON, the switch S¯x = 0, is OFF, to avoid the variable dc-link short circuit. Since there are two switching states per phase, the number of allowed switching states in function of the number of output phases (NOP ) is given by NOP −states = 2NOP . For the case of the RMC shown in Fig. 1 there are three output phases, and therefore the allowed switching states for the 2L-VSI is as expected 23 = 8. The total number of allowed switching states of the whole converter (Nstates ) is given by the multiplication of the number of switching states in the multilevel dc-dc stage and in the dcac stage, hence Nstates = NDC−states ∗ NOP −states . For the 5L-RMC shown in Fig. 1, the total of allowed switching states is Nstates = 27 ∗ 8 = 216. Like with other multicell converter structures such as the FCC and SMC, there are several redundancies from an output voltage generation perspective. This can be used in favor for the DC-cell capacitor voltage control. From the 27 allowed variable dc-link switching states, only 10 generate different voltage potentials in the output terminals (the 17 other generate redundant levels) for a three DC-cell RMC. Fig. 3 shows a selections of the 10 different dc-link level generation possibilities. Fig. 3-(a) to Fig. 3-(d) show the possible combinations for vnN = 0 and vpN = VDC /4, vpN = VDC /2, vpN = 3VDC /4, and vpN = VDC respectively. Fig. 3-(e) to Fig. 3-(g) show possible combinations for vpN = VDC and: vnN = 3VDC /4, vnN = VDC /2, and vnN = VDC /4 respectively. Fig. 3-(h) and Fig. 3-(i) show possible combinations of vpN = 3VDC /4 and: vnN = VDC /4, and vnN = VDC /2 respectively. Finally, Fig. 3-(j) shows the combination of dc-dc voltage of vpN = VDC /2 and vnN = VDC /4. To generate five voltage levels with the same voltage step (dv/dt), the voltages in the inner capacitors must follow the following ratio: vC4 : vC3 : vC2 : vC1 = 4 : 3 : 2 : 1, being vC4 = VDC . All combinations of these dc-dc multilevel voltages using a 2L-VSI in the dc-ac stage, gives a total of 216 possible output voltage space vectors, which are shown in Fig. 4 including the number of their redundancies. The generated vectors have magnitudes of zero, VDC /6, VDC /3, VDC /2, and2VDC /3, whose redundancies are summarized in Table II. B. Analysis of constraints An important consideration for this topology is the each device blocking voltage. The blocking voltage of the semi-

p Sp3

Sp2 C3

VDC

SC3 Sn3

Sp1 C2

SC2 Sn2

SA variable dc-link

C1

SA

N

n DC-cell 3

DC-cell 2

A

vVDC

SC1 Sn1

SB

DC-cell 1

Multilevel DC-DC converter

SC B

SB

C

SC

Output Switches 2L-VSI DC-AC Output Inverter

Fig. 1: Five-level reduced multilevel converter (5L-RMC), with three DC-cells and a 2L-VSI output inverter stage.

vo

TABLE III: Maximum device blocking voltage

vo

+

+

(k+1)

Spk

(k)

vˆblock

Ck

VDC 4

vck

VDC 2

vo

Snk

SCk

-

vo

3VDC 4

-

(k+1)

(k)

VDC

DC-cell k

Power Switch Sp3 Sn3 SC3 Sp2 Sn2 SC2 Sp1 Sn1 SC1 SA , S¯A SB , S¯B SC , S¯C

Fig. 2: Generic DC-cell k for variable dc-link of the RMC. C. About medium voltage implementation TABLE II: Number of redundant voltage space vectors and their magnitude Number of redundant switching states 54 18 · 6 = 108 6 · 6 = 36 2 · 6 = 12 1·6=6

Output voltage magnitude 0 [V] VDC /6 [V] VDC /3 [V] VDC /2 [V] 2VDC /3 [V]

conductor in a DC-cell depends on the voltage vo+(k+1) , which can change. However, there is a maximum voltage that the transistors need to block, given by: vˆblock,Syk = VDC − vCk ,

(1)

where Syk is the power switch y in DC-cell k for all y ∈ {p, n, C}, and vCk is the voltage of the capacitor in DC-cell k. In the case of the output switches (Sx , S¯x with x ∈ {A, B, C}) the maximum blocking voltage is the full dc-link voltage. The maximum blocking voltages of the switches are summarized in Table III

The maximum device blocking voltage of this topology is a disadvantage that reduces its feasibility to be used for medium voltage applications. Nevertheless, multilevel converters have now been used extensively in low voltage applications, such as PV inverters, UPS systems, and wind power conversion systems (all below 690 V), which require high power quality and efficiency, making it the more natural scope for this topology. However, one solution to implement this topology for medium-voltage applications is to connect additional semiconductors in series, or to change the output inverter stage by a single dc-source medium voltage multilevel inverter topology (NPC, ANPC, NPP, etc. ). D. About the number of output levels The number of output voltage levels in the RMC depends not only on the number of DC-cells in the multilevel dc-link, but also on the number of output levels of the dc-ac output inverter stage. For example, the three DC-cell RMC shown in Fig. 1, when using a three level T-Type topology in the dc-ac output inverter stage, will have 9 instead of 5 levels.

vpN= vC1

vpN= vC2

p Sp3

Sp2

p

Sp1

Sp3 VSI

C4 dc-link

C3

SC3 Sn3

C2

Sn2

SC2

VSI

SC1 Sn1

C2

Sn2

SC2

C1

SC1 Sn1 n

N

vnN= 0

(a)

C3

SC3 Sn3 n

N

Sp1

C4 dc-link

C1

Sp2

vnN= 0

(b)

vpN= vC3

vpN= vC4

p Sp3

Sp2

p Sp3

Sp1 VSI

C4 dc-link

C3

SC3 Sn3

C2

Sn2

SC2

VSI

n

C2

Sn2

SC2

C1

SC1 Sn1 n

N

vnN= 0

(c)

C3

SC3 Sn3

SC1 Sn1

N

Sp1

C4 dc-link

C1

Sp2

vnN= 0

(d)

vpN= vC4

vpN= vC4

p Sp2

Sp3

p

Sp1 VSI

C4 dc-link

C2

C3

SC3 Sn3

Sn2

SC2

VSI

SC1 Sn1 n

C2

C3

SC3 Sn3

Sn2

SC2

C1

SC1 Sn1 n

N

vnN= vC4-vC1

(e)

Sp1

C4 dc-link

C1

N

Sp2

Sp3

vnN= vC4-vC2

(f)

vpN= vC3

vpN= vC4 p Sp3

Sp2

p

Sp1

Sp3 VSI

C4 dc-link

C3

SC3 Sn3

C2

Sn2

SC2

VSI

SC1 Sn1

C2

Sn2

SC2

C1

SC1 Sn1 n

N

vnN= vC4-vC3

(g)

C3

SC3 Sn3 n

N

Sp1

C4 dc-link

C1

Sp2

vnN= vC3-vC2

(h)

vpN= vC3

vpN= vC2

p Sp3

Sp2

p

Sp1

Sp3 VSI

C4 dc-link

C3

SC3 Sn3

C2

Sn2

SC2

VSI

SC1 Sn1

(i)

C3

SC3 Sn3 n

N

vnN= vC3-vC1

Sp1

C4 dc-link

C1

Sp2 C2

Sn2

SC2

C1

SC1 Sn1 n

N (j)

vnN= vC2-vC1

Fig. 3: Different DC-cell switching states (only non-redundant are shown) and their respective output potentials for a 5L-RMC.

III. C OMPARISON WITH OTHER EXISTING MULTILEVEL TOPOLOGIES

In order to assess advantages and drawbacks of the proposed RMC topology, it will be compared to two existing multilevel topologies, the five level Active Neutral Point Clamped converter (5L-ANPC) and the five-level Flying Capacitor converter (5L-FCC). This comparison is carried out for the same number

of output voltage levels, same power rating and under the supposition that all converters use the same rated power switches. Fig. 5 shows the power circuit of the three-phase 5L-ANPC [8], [10]. This is an industrial topology commercialized by ABB as ACS 2000 drive [14]. In the 5L-ANPC, the inner capacitor is kept charged to one quarter of the total dc-link

1

1 2

S1

2 6

C4

18

C3 C3 S1

1

6

2

18

18

18

6

2

S1

54 18

S3

C B A

C1 C1 C1S3

S2 S2

SA SA

C2 C2 C2S2

S1

1

SA

S3

S2 C3

dc-link

S3

S2

S1

3 VDC 3 6

S2

S1

SA

S3 S3

SA SA

18

N 6

6

2

Fig. 6: Five-level flying capacitor converter (5L-FCC) power circuit.

2

1

1

TABLE IV: Number of power switches in 5-level converters

2 VDC 3

Fig. 4: Output voltage space vectors generated by the RMC, including their number of redundancies.

Topology ANPC FCC RMC

S1A S1A S1A C21

N C22

S2A S2A S2A S4A S4A S3A S4A S3A

S21A C S22C 1A S21A C S22B S21A C 1A S22A 1A S3A S32A S31C S32A S31B S32A S31A

C B A

Fig. 5: Five-level active neutral point clamped inverter (5LANPC) power circuit.

voltage, i.e. vC1x = VDC for all x  {A, B, C}. The main 4 operating principle of this topology can be considered as a standard three-level ANPC with an additional flying capacitor cell connected to the output. This additional stage adds or subtracts the flying capacitor voltage to the three-level stage generating the two additional output levels. Fig. 6 shows the power circuit of the three-phase 5L-FCC [15], [16]. The FCC is built by the multicell connection of flying capacitor cells, which are composed of one capacitor and two switches that work complementarily, i.e. when one power switch in the cell is ON, the other switch is OFF. Every cell increases the number of voltage level of the converter by one, similarly to the proposed RMC. To generate 5 levels in the output, the inner capacitors must be controlled to the ratio of vC4 : vC3 : vC2 : vC1 = 4 : 3 : 2 : 1 with vC4 = VDC . In the 5L-FCC, all power switches block the same voltage which is VDC /4 in case of the 5-level inverter. Table IV summarizes the number of components that are required in the different topologies to generate 5 different output levels in a three phase connection considering the blocking voltage in the power switches.

Power Switches 12 12 24 3 3 3 6

Max. Blocking Voltage VDC /2 VDC /4 VDC /4 VDC /4 VDC /2 3VDC /4 VDC

Table V summarizes the number of capacitors considering the capacitances of the inner capacitors for a maximum voltage ripple of 5%. Their corresponding voltage rating is also listed. It is possible to see that the proposed topology is called Reduced Multilevel Converter because it needs less components to generate the same number of output voltages than the compared existing 5-level topologies. Furthermore, in comparison with the 5L-FCC, the proposed topology needs one third of the capacitors to ensure the correct performance. The RMC has a lower number of components, but the size of the converter does not vary much with the reduction of semiconductors, as they are a small contributor to the overall volume; moreover, all analyzed topologies have same number of levels, hence comparable power quality, which would not turn out on a huge impact in the filter size. However, the main advantage of the 5L-FCC, compared to the proposed topology, is that all power switches in 5L-FCC block the same voltage.

IV. C ONTROL S TRATEGY FOR RMC The control objectives for the RMC are the control of the flying capacitor voltages and the control of output currents. There is not a straight forward, or natural modulation scheme that can generate the multilevel output voltages of the converter and ensure a correct control of the capacitor voltages. This us due to the additional switch in series to each capacitor in the variable dc-link . For this reason, the a simple control strategy that allows to handle multiple control objectives in converters with complex switching arrangements is Model Predictive Control. This control strategy will be used to provide a preliminary validation of the behavior of the RMC.

TABLE V: Number of flying capacitors in 5-level converters Topology ANPC FCC RMC

Flying capacitors 3 9 1 1 1

Capacitance 171.4[µF ] 171.4[µF ] 171.4[µF ] 85.7[µF ] 57.1[µF ]

Rated voltage VDC /4 VDC /4 VDC /4 VDC /2 3VDC /4

In order to predict the DC-cell capacitor voltages, they can be modeled considering the integral of the currents passing through them, which is defined by a combination of the switching states and the load phase currents, given by vC3

1 = C3

Z X C 

 SC3 (1 − SC2 ) SC1 (Sx − Sp1 )

x=A

   + (Sp3 − Sx ) + SC2 (Sp3 − Sp2 ) ix dt

A. Mathematical model The best way to understand the behavior of a system is the mathematical description. In the case of the RMC, the equations that describe the properties of the converter are the output voltages and the inner capacitor voltage equations. The output phase voltages, at the output terminals (A, B, or C in Fig. 1) and the neutral point of the converter N , can be expressed as a function of the switching states and inner voltages. One way to find a general expression for the output voltage is by analyzing the equivalent circuits for the switching states in Fig. 3, and find an equation for every output voltage component in terms of the gating signals. For example, the voltage of the capacitor C1 is going to appear in the output voltage only if SC1 is ON and Sp1 6= Sx for x ∈ {A, B, C}, which can be written as vxN (vC1 ) = vC1 SC1 (Sx − Sp1 ).

vC2

vC1

(6) Z X C   1 = SC2 (SC1 (Sx − Sp1 ) + Sp2 − Sx )ix dt C2 x=A (7) Z X C   1 = SC1 (Sp1 − Sx )ix dt (8) C1 x=A

While equations (5)−(8) cover the behavior of the converter, the mathematical model of the whole system also requires the load equations. In this work, a balanced three-phase resistiveinductive RL load considered, which is modeled by dix + voN dt vAN + vBN + vCN voN = 3 x  {A, B, C}

vxN =Rix + L

(9) (10) (11)

(2)

A similar expression can be derived for the contribution to the output voltage by all flying capacitor voltages. For example, the voltage of C2 will appear in the output voltage only if SC2 is ON and Sp2 6= Sx if SC1 , and is OFF (SC1 = 0). However, if SC1 is ON, the condition changes to Sp2 6= Sp1 , this can be written as

where R and L are the load parameters and o is the neutral point of the three phase load. B. Finite Control Set Model Predictive Control

In the last decade, several works have proposed the use of Finite Control Set Model Predictive Control (FCS-MPC) to control several types of power converter topologies and electrical drives [17]–[22]. vxN (vC2 ) = vC2 SC2 (1 − SC1 )(Sx − Sp2 )  The main advantages of this control algorithm are that it + SC1 (Sp1 − Sp2 ) , (3) is conceptually simple to understand, able to deal with nonwhich can be reduced to linearities, handle multiple control objectives and provide a fast vxN (vC2 ) = vC2 SC2 SC1 (Sp1 − Sp2 − Sx + Sp2 ) dynamic response.  FCS-MPC explicitly takes into account the influence of + (Sx − Sp2 )  the switching states in the converter-load prediction model to = vC2 SC2 SC1 (Sp1 − Sx ) + (Sx − Sp2 ) (4) solve an optimization problem that chooses the switching state Following the same steps it is possible to find an expression to be applied at the next sampling instant (k + 1) through for the contribution to the output voltage of all the DC-cell minimization of a cost function. Since the gating signals are capacitors and the input dc-source voltage, in this case vC3 directly selected, no modulation stages are necessary. This and VDC remain to be added, which yields to the total output characteristic of FCS-MPC makes it particularly useful for voltage expression converters where the implementation of modulators is complex,  like is the case with the proposed RMC, where no classic PWM vxN = VDC (1 − SC3 ) SC2 Sp2 + (1 − SC2 )(SC1 (Sp1 − Sx ) based strategy is yet defined.    To implement FCS-MPC, it is necessary to obtain a discrete + Sx ) + Sp3 SC3 + vC3 SC3 (1 − SC2 ) SC1 (Sp1 − Sx ) time model of the whole system, including converter and load,   eq. (5) − (11). The state variables are the output currents and + (Sx − Sp3 ) + SC2 (Sp2 − Sp3 ) + vC2 SC2 (Sx − Sp2 ) the DC-cell voltages. The switching states Syk and Sx are con + SC1 (Sp1 − Sx ) + vC1 SC1 (Sx − Sp1 ), (5) sidered as control inputs, for all k ∈ {1, 2, 3}, y ∈ {p, n, C} where x ∈ {A, B, C}, vC1 , vC2 and vC3 are the inner voltages and x ∈ {A, B, C}. Since each switch can take only two values, and there is a limited number of possible combinations of the capacitors C1 , C2 and C3 , respectively.

(1)

(3)

(2) Cost Function Evaluation g

Prediction Model

v ,v ,v C1

v *,v *,v * iA* ,iB* ,iC* C1

C2

C3

v ,v ,v iA,iB,iC C1

15

C2

C2

(2)

RMC Converter

Sx

(3) (4) (1)

C3

C3

iA,iB,iC

Fig. 8: Experimental RMC prototype: (1) dc-link capacitors; (2) DC-cells; (3) Variable dc-link; (4) 2L-VSI.

RL Load O

Fig. 7: FCS-MPC block diagram for RMC.

modulation, the modularity may or may not hold, and should be matter or future research.

of switching states, FCS-MPC needs to be evaluated a finite number of times, in the case of the 5-level 3-phase RMC, there are 216 allowed switching states. Predicting the behavior of the system using the discrete mathematical model for the 216 allowed switching states, it is possible to choose the switching state that minimizes the controller’s cost function. The cost function is the part which seeks to control all important variables of the system. In this case, it is given by tracking the output currents error and DCcell voltages of the converter, defined as

V. E XPERIMENTAL VALIDATION

gk =

C X

i∗x − ik+1 x

2

k+1 ∗ + λ1 vc1 − vc1

2

x=A k+1 ∗ +λ2 vc2 − vc2

2

k+1 ∗ + λ3 vc3 − vc3

2

.

(12)

The superscript ∗ denotes the reference value, and the superscript k + 1 denotes the prediction value of the variable at the sampling instant k+1. Finally, λ1 , λ2 and λ3 are weighting factors that allow to give different importance to the different control variables. These weighting factors are calculated by dividing each term of the cost function with the corresponding rated value of the variable to obtain a normalized or nondimensional value. In this way all variables have a similar importance or weight. Fig. 7 shows the block diagram for the FCS-MPC strategy. Where (1) represents the block of the estimation and predictions stage of the control strategy; (2) represents the cost function evaluation considering all 216 possible switching states; and finally, (3) represents the power circuit, with the measurements of the DC-cell voltages in the converter and the output currents in the load. It is worth mentioning that when changes are made to the variable DC-link structure, by adding or eliminating DC-cells, the converter will have more or less switching states. Hence, the FCS-MPC algorithm does not change, only the number of predictions and iterations according to the available switching states changes; the implementation remains the same. This makes the converter not only modular in its variable dc-link structure but also from a control point of view. However, since this work does not proposes a classic control with a

In order to verify the performance of the proposed multilevel converter, this section shows some experimental results considering a VDC = 400[V ], and a load of R = 16Ω, L = 30mH with a sampling frequency for MPC of Fs = 8kHz. A. Experimental Setup The laboratory prototype built for experimental validation is shown in Fig. 8. The area (1) corresponds to the dc-link capacitors, area (2) shows the three DC-cells of the converter, section. (3) shows the variable dc-link bus connection between the DC-cells and the output inverter stage. Finally, area (4) shows the 2L-VSI. The power switches used in this prototype are IGBTs from ON Semiconductor, NGTB30N120IHSWG, with 30A and 1200V maximum collector current and collector-emitter voltage. The capacitance of the flying capacitor in all DC-cells is 330µF. The micro-controller platform used is MicroLabBox from Dspace. B. Experimental Results Two different experiments are presented to show the operation of the proposed topology: steady-state performance with rated output current, and dynamic behavior considering a step in the current reference from 6A to 3A with a phase shift of 180◦ . Fig. 9 shows the output current in phase A and the blocking voltage in the power switch SC1 . This is the power switch in series with the capacitor in the DC-cell further of the dcsource. It is possible to see that in one period, the switch SC1 needs to block different voltage ranges. As shown in Table III, the switch SC1 has a maximum blocking voltage of 3VDC /4. Fig. 10 shows the steady-state performance of the converter with a high fundamental voltage amplitude. It is possible to see in the figure that the MPC algorithm can control properly all control tasks, getting a sinusoidal three-phase output currents while ensuring controlled DC-cell voltages, which allow to generate the five-level output voltage waveform in all phases. Fig. 11 shows the performance of the converter during a dynamic step in the current reference. Much like the performance shown in Fig. 10, the control strategy ensures correctly

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controlled DC-cell voltages in the flying capacitors and a sinusoidal output current, even during the transients. It is also possible to appreciate that MPC achieves a fast response due to its non-linear nature, generating a fast current reference tracking in all three phases. VI. C ONCLUSIONS In this paper, a new multilevel converter topology based on a novel switched DC-cell and variable dc-link operation concept has been proposed. It can achieve same number of output voltage levels than existing multilevel topologies with a fraction of the active switching devices and capacitors, since the variable dc-link is shared by all output phases of the inverter. The main control challenge of the topology is the control of the DC-cell capacitor voltages to generate the desired total number of output levels. Due to the switched DC-cell capacitors, there it is not straight forward to implement a carrier based PWM scheme. For this reason, FCS-MPC was used to verify the performance of the new converter. A laboratory prototype has been built using three shared DC-cells and a three-phase 2L-VSI as inverter output stage.

Experimental results show that the DC-cell capacitors can be balanced and controlled accurately while achieving sinusoidal output currents, and a five-level output voltage waveform. At a first glance, the maximum device blocking voltage is the main disadvantage of this topology. However, this is imposed by the selected inverter output stage, which in the case analyzed in this paper is a 2L-VSI. This limitation prevents the use of this topology for medium voltage applications. Nevertheless, multilevel converters have now been used extensively in low voltage applications, such as PV inverters, UPS systems, and wind power conversion systems (all below 690 V), due to their power quality, making this topology interesting for further analysis. A comprehensive study to determine the most suitable applications for this topology, as well as the evaluation with different output inverter stages (NPC, ANPC, etc.), which could lead to medium voltage operation, is a matter of future research. Other open problems include the development of a carrier based PWM or space vector modulation strategy for the converter, and more sophisticated FCS-MPC techniques using fixed switching frequency and dv/dt reduction. R EFERENCES [1] N. Flourentzou, V. G. Agelidis, and G. D. Demetriades, “VSC-Based HVDC Power Transmission Systems: An Overview,” IEEE Transactions on Power Electronics, vol. 24, no. 3, pp. 592–602, Mar. 2009. [2] A. M. Abbas and P. W. Lehn, “PWM based VSC-HVDC systems — A review,” in Proc. IEEE Power Energy Society General Meeting, Jul. 2009, pp. 1–9. [3] R. Pena, J. C. Clare, and G. M. Asher, “Doubly fed induction generator using back-to-back PWM converters and its application to variable-speed wind-energy generation,” IEE Proceedings-Electric Power Applications, vol. 143, no. 3, pp. 231–241, May 1996. [4] N. Panten, N. Hoffmann, and F. W. Fuchs, “Finite Control Set Model Predictive Current Control for Grid-Connected Voltage-Source Converters With LCL Filters: A Study Based on Different State Feedbacks,” IEEE Transactions on Power Electronics, vol. 31, no. 7, pp. 5189–5200, Jul. 2016. [5] Z. Chen, C. Mao, D. Wang, J. Lu, and Y. Zhou, “Design and Implementation of Voltage Source Converter Excitation System to Improve Power System Stability,” IEEE Transactions on Industry Applications, vol. 52, no. 4, pp. 2778–2788, Jul. 2016.

[6] J. Rodriguez, J. S. Lai, F. Z. Peng, “Multilevel Inverters: A Survey of Topologies, Controls, and Applications,” IEEE Transactions on Industrial Electronics, vol. 49, no. 49, pp. 724–738, August 2002. [7] A. Nabae, I. Takahashi, H. Akagi, “A New Neutral-Point-Clamped PWM Inverter,” IEEE Transactions on Industry Applications, vol. 17, no. 5, pp. 518–523, 1981. [8] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A survey on Neutral-Point-Clamped inverters,” IEEE Transactions on Industrial Electronics, vol. 57, no. 7, pp. 2219–2230, 2010. [9] T. A. Meynard, H. Foch, P. Thomas, J. Courault, R. Jakob, and M. Nahrstaedt, “Multicell Converters: basic concepts and industry applications,” IEEE Transactions on Industrial Electronics, vol. 49, no. 5, pp. 955–964, Oct. 2002. [10] F. Kieferndorf, M. Basler, L. Serpa, J.-H. Fabian, A. Coccia, and G. Scheuer, “ANPC-5L technology applied to medium voltage variable speed drives applications,” in SPEEDAM 2010. IEEE, 2010, pp. 1718– 1725. [11] G. Gateau, T. A. Meynard, H. Foch, “Stacked multicell converter (SMC): properties and design.” IEEE 32nd Annual Power Electronics Specialists Conference, PESC 2001., June 17-22, Vancouver, Canada. 2001. [12] M. Schweizer and J. W. Kolar, “High efficiency drive system with 3-level T-type Inverter,” in Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on. IEEE, 2011, pp. 1–10. [13] M. Norambuena, J. Rodriguez, and S. Kouro, “Convertidor Multinivel para el Control y Transmisión de la Energía Eléctrica,” Chilean pat. requeriment 201 602 365, Sep. 20, 2016. [14] www.abb.com, “Abb acs2000,” no. 8, pp. 60–61, 2011. [15] R. H. Wilkinson, T. H. Meynard, and H. du Toit Mouton, “Natural balance of multicell converters: The general case,” IEEE Transactions on Power Electronics, vol. 21, no. 6, pp. 1658–1666, Nov. 2006. [16] E. I. Silva, B. P. McGrath, D. E. Quevedo, and G. C. Goodwin, “Predictive control of a flying capacitor converter,” in American Control Conference, 2007. ACC ’07, Jul. 2007, pp. 3763–3768. [17] J. Rodriguez, J. Pontt, C. A. Silva, P. Correa, P. Lezana, P. Cortes, and U. Ammann, “Predictive current control of a voltage source inverter,” vol. 54, no. 1, pp. 495–503, Feb. 2007. [18] S. Muller, U. Ammann, and S. Rees, “New time-discrete modulation scheme for matrix converters,” IEEE Transactions on Industrial Electronics, vol. 52, no. 6, pp. 1607–1615, Dec. 2005. [19] P. Lezana, R. P. Aguilera, and D. E. Quevedo, “Model predictive control of an asymmetric flying capacitor converter,” IEEE Transactions on Industrial Electronics, vol. 56, no. 6, pp. 1839–1846, June 2009. [20] S. Kouro, P. Cortes, R. Vargas, U. Ammann, and J. Rodriguez, “Model predictive control& simple and powerful method to control power converters,” IEEE Transactions on Industrial Electronics, vol. 56, no. 6, pp. 1826–1838, June 2009. [21] J. Rodriguez, M. P. Kazmierkowski, J. R. Espinoza, P. Zanchetta, H. AbuRub, H. A. Young, and C. A. Rojas, “State of the Art of Finite Control Set Model Predictive Control in Power Electronics,” IEEE Transactions on Industrial Informatics, vol. 9, no. 2, pp. 1003–1016, 2013. [22] S. Vazquez, J. Rodriguez, M. Rivera, L. G. Franquelo, and M. Norambuena, “Model Predictive Control for Power Converters and Drives: Advances and Trends,” IEEE Transactions on Industrial Electronics, vol. 64, no. 2, pp. 935–947, Feb. 2017.

Margarita Norambuena (S’12-M’14) received the B.S. and M. S. degrees in electric engineering from the Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile, in 2013. She received a scholarship from Chilean National Research, Science and Technology Committee (CONICYT) in 2014 to pursue the PhD degree studies in power electronics at UTFSM and Technische Universitaet Berlin (TUB). She also received a scholarship from German Academic Exchange Service (DAAD) in 2015 to pursue the PhD degree studies in TUB. Her research interest include multilevel converters, model predictive control of power converters and drives, energy storage systems, renewable energy and microgrids systems.

Samir Kouro (S’04-M’08-SM’17) received the M.Sc. and Ph.D. degrees in electronics engineering from the Universidad Tecnica Federico Santa Maria (UTFSM), Valparaiso, Chile, in 2004 and 2008, respectively. He is currently an Associate Professor at UTFSM. From 2009 to 2011, he was a Postdoctoral Fellow with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada. He is the Principal Investigator of the Solar Energy Research Center (SERC Chile) and Titular Researcher of the Advanced Center of Electrical and Electronics Engineering (AC3E), both being Centers of Excellence in Chile. He has coauthored over 150 refereed journal and conference papers. Dr. Kouro received the IEEE Industrial Electronics Society Bimal Bose Award in 2016, the J. David Irwin Early Career Award in 2015, the IEEE Power Electronics Society Richard M. Bass Outstanding Young Power Electronics Engineer Award in 2012, the IEEE Industry Applications Magazine First Prize Paper Award in 2012, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Best Paper Award in 2011, and the IEEE Industrial Electronics Magazine Best Paper Award in 2008.

Sibylle Dieckerhoff (M’04) received the Dipl.Ing. and Dr.-Ing. degrees in Electrical Engineering from RWTH Aachen, Germany, in 1997 and 2003, respectively. From 1997 to 2002, she was a Research Associate with the Institute for Power Electronics and Electrical Drives, RWTH Aachen, and with Daimler-Chrysler Research and Technology, Berlin, Germany. In 2003, she joined the Siemens AG as a Development Engineer, followed by positions as a Senior Researcher at the Technical University of Berlin (TU Berlin), and as a Professor at the Beuth University of Applied Sciences, Berlin. Since 2010, she is a Professor of Power Electronics at TU Berlin. Her research interests include converters applying WBG devices, multilevel converters, and grid converters in electrical grids with a large amount of power electronic devices. She is a member of the International Scientific Committee of the EPE, of the IEEE PELS AdCom, and served as vice chairperson of the German ETG / VDE Steering Committee from 2013-2016.

Jose Rodriguez (M’81-SM’94-F’10) received the Engineer degree in electrical engineering from the Universidad Tecnica Federico Santa Maria, in Valparaiso, Chile, in 1977 and the Dr.-Ing. degree in electrical engineering from the University of Erlangen, Erlangen, Germany, in 1985. He has been with the Department of Electronics Engineering, Universidad Tecnica Federico Santa Maria, since 1977, where he was full Professor and President. Since 2015 he is the President of Universidad Andres Bello in Santiago, Chile. He has coauthored two books, several book chapters and more than 400 journal and conference papers. His main research interests include multilevel inverters, new converter topologies, control of power converters, and adjustable-speed drives. He has received a number of best paper awards from journals of the IEEE. Dr. Rodriguez is member of the Chilean Academy of Engineering. In 2014 he received the National Award of Applied Sciences and Technology from the government of Chile. In 2015 he received the Eugene Mittelmann Award from the Industrial Electronics Society of the IEEE.