Reducing Hierarchical Test Path Cost via Modular Test Requirement ...

Reducing Hierarchical Test Path Cost via Modular Test Requirement Analysis Alex Orailoglu CSE Department - U.C. San Diego La Jolla, CA 92093 [email protected]

Yiorgos Makris EE Department - Yale University New Haven, CT 06520 [email protected] Abstract

We propose a methodology that examines design modules and identifies appropriate vector justification and response propagation requirements for hierarchical test. Based on a cell-level analysis and transparency composition methodology, test requirements for a module are defined as a set of fine-grained input and output bit clusters and pertinent justification and propagation values. The identified test requirements are independent of the actual test set and are adjusted to the cell-level connectivity and inherent regularity of the module. As a result, they combine the generality required for fast hierarchical test path construction with the accuracy necessary for minimizing the incurred DFT hardware overhead, thus fostering cost-effective hierarchical test. Experimental results verify the ability of the proposed methodology to moderate the cost of hierarchical test path construction through accurate, compact, and highly parametrizable test requirement definition.

1. Summary Hierarchical methods leverage on the ability to individually target each module in a design and generate highly efficient local test. This benefit, however, comes at the cost of necessitating hierarchical test paths through the upstream and downstream logic, which establish transparent access to the module under test (MUT), as depicted in Figure 1(a). During hierarchical test path construction, however, the module under test is treated as a black box and no information pertaining to its inherent test requirements is utilized. Consequently, excessive DFT hardware is employed in order to construct hierarchical test paths. In an effort to reduce the DFT cost of hierarchical test path construction, two directions have been examined. Along the first direction, several research efforts have been invested in efficiently defining, extracting, and utilizing inherent design transparency. Along the second direction, inherent functionality of the upstream and downstream logic is utilized to constrain local test generation in an effort to render highly translatable test. Not much attention has been paid, however, to a third alternative, namely the possibility of moderating the cost of hierarchical test paths through an examination and informed definition of test requirements for each module. This idea is depicted in Figure 1(b), where the internal cell-level connectivity of the MUT is examined and its test requirements are defined in terms of several input and output bit clusters. This, in turn, necessitates several narrow hierarchical test paths instead of a single coarse path, thus increasing the probability of their inherent existence in the design and reducing the expected DFT cost for their construction. In this work, we examine the impact of test requirement granularity on the severity of hierarchical test path construction and we propose a methodology for reducing the cost of hierarchical test path construction by adjusting the generality of test requirements. A cell-level analysis and a symbolic path composition result in the definition of fine-grained test requirements on sets of input and output bit clusters. Primary Inputs

Primary Inputs

Hierarchical Test Path Through Upstream Logic

Justify All Vectors

Module Under Test

Test Requirements (MUT=Black Box)

Propagate All Responses

Hierarchical Test Path Through Downstream Logic

Primary Outputs

Fine-Grained Bit Clusters to be Justified

DFT Cost for Test Requirements Hierarchical Test (Analyze MUT) Path Construction

Module Under Test CELL

CELL

Fine-Grained Bit Clusters to be Propagated

Primary Outputs

(a)

(b)

Figure 1. Granularity of Test Requirements

Reduced DFT Cost for Construction of Fine-Grained Hierarchical Test Paths

Test Requirement Analysis for Low Cost Hierarchical Test Path Construction

Motivation Hierarchical Test Generation & Application

Problem Definition • Lack of Identifiable Transparency Incurs DFT Overhead

Hierarchical Design Primary Inputs

Yiorgos Makris

Research Direction

Upstream Modules

Downstream Modules

ELECTRICAL ENGINEERING DEPARTMENT

• Reduce the Cost of Hierarchical Test Paths through: • Improved Transparency Extraction Methods • Low-Cost DFT for Establishing Transparency

Vector Justification Paths

YALE

Current Research Efforts

Primary Outputs

Module Under Test Response Propagation Paths

Proposed Method • Reduce the Cost of Hierarchical Test Paths through:

Hierarchical Test Paths

University Local Test Generation

Alex Orailoglu

• Accurate Test Requirement Identification • Low-Cost DFT for Reducing Test Requirements

Local To Global Test Translation

Local Test

Idea

Global Test

• Identify Sufficient Test Requirements Expressed in Many Narrow Paths Instead of One Wide Path

• Divide: Complexity Reduction – Customization • Conquer: Need Access to the Boundary of Each Module

COMPUTER SCIENCE & ENGINEERING DEPARTMENT

Justification • Full Transparency Rarely Needed for Testing Each Module • Narrow Paths Have Higher Probability of Inherent Existence

• Limitation: DFT Cost for Hierarchical Test Path Construction

Hierarchical Test Path Severity

Proposed Methodology

Test Requirements of Modules

Cell-Based vs. Exhaustive Requirement Analysis

• Test Requirement Severity Critical to Path Complexity • Current Approaches Assume Full Symbolic Path Needed • Accurate Fine-Grained Paths Important to Reduce DFT TEST SET

PATH REQUIREMENT

TS1={00, 11} TS2={01, 10} TS3={00, 01} TS4={10, 11} TS5={00, 01, 10}

MODULE

(A1, A1) : 1 Free Variable (A1, A1') :1 Free Variable (V, A1) : 1 Free Variable (A1, V) : 1 Free Variable (A1, A2) : 2 Free Variables

TEST SET MODULE

Surjection Activation Constants

'X'

Cell Granularity

'A'

Selection Factors • Satisfaction of Severity Threshold Condition • Repetitive Structures – Regularity - Homogeneity • Number and Size of Cells

Injection Activation Constants

'X'

MODULE k 'A'

Surjective Path ...

k≥l

l

CELL

m

'A'

Injective Path ...

'A'

'X'

'A'

Basic Cells Satisfying Severity Condition

n 'A'

FULL ADDER CELL A B C

n≥m

'X'

RESTORING DIVIDER CELL

D

MULTIPLY-ADD CELL

S

NON-RESTORING DIVIDER CELL

S D

C D

B E

A

C

A

B

S

C

D

E

B

E

PATH REQUIREMENT

TS6= {001, 010, 101, 110}

(A1, A2, A2') : 2 Free Variables

TS7= {010, 100, 110, 001}

(A1, A2, A3) : 3 Free Variables

Severity Threshold Condition • The hierarchical test path construction severity of a set of k-bit vectors is equivalent to a k -bit symbolic path if every subset of bits obtains more than half of the possible values

Test Requirements Example #1

'X'

P={Test Pattern Values}

E

'X'

Vectors:

MODULE k Vt

...

l

CELL

m

Vj

k≥l

'X'

...

n Vr

Vp

R={Test Response Values}

n≥m

'X'

Responses:

ABC 100 010 001 101 110 000

DE 10 01 00

Vectors:

ABCS 010X 111X 110X 0110 0111

ABCS 0X01 0100 1000 0X10 1101 0X11 1100

Responses:

ABCS 0001 1000 0011 1011 1001

DE 01 00 10 11

Vectors:

Responses:

DE 01 00 10

Responses:

ABCS 1000 0000 0101 1100 1010 0010 0100

Hierarchical Test Path Severity:

Justify 'AAAA' at ABCS Propagate 'AA' from DE

DE 01 00 10 Hierarchical Test Path Severity:





Justify 'AAA' at ABC Propagate 'AA' from DE

Test Requirements Example #2

Vectors:

A

Test Requirements Example #3 RESTORING ARRAY DIVIDER

74181 ALU

CARRY-RIPPLE ADDER M ' Cn A 0 B 0

A0 B0 Cin

FA#1

A1 B1 C1

A2 B2

FA#2

Z0

C2

Z1

FA#3

FA#1: FA#2: FA#3: FA#4:

C3

FA#4

Cout

Cell #1

Cell #2

Cell #3

Z0Z1Z2Z3Cout A A X X X X A A X X X X A A X X X X A A

Cell #5

Cell #6

Cell #7

Cell #8

F0'

F1'

F2'

F3'

∑ TPIS

TPIS( Path ) = ∏TPIS ( Bit ) 1  TPIS ( Bit ) = 2  4

∀Bits

∀Bits

'X '  'V ' ' A ' 

if

' X '  ' A ' ' V ' 

if if if

G'

G'CoP'F3'F2'EqF1'F0' X X X X X X A A X X X X A X A X X X X A A X X X X A X A X X X X X X X X X X X A X X X X X X A X X X X X X A X X X X X X A X X X A A A X X A X X

Adder Divider ALU

Non- Compacted Test C- TPES C-TPIS 848 38144 7360 3662468 65280 230430714

Proposed Method C-TPES C- TPIS 2560 656 49152 98304 238435456 16384

Adder Divider ALU

Symbolic Paths ? -TPES ? - TPIS 1024 32 4096 64 65536 256

Compacted Test ? - TPES ? -T P I S 224 7168 1088 69632 5632 1441792

Non- Compacted Test ? -TPES ? - TPIS 40 256 832 47888 4064 1013856

Proposed Method ? -TPES ? -TPIS 64 16 36 272 32 320

DFT for Test Requirement Reduction

Surjection Activation Constants 'X'

'A'

'X'

4-bit Carry Ripple Adder

Cout

CELL

'A'

m

Injective Path ...

'A'

'X'

'A'

'X'

0 0 0 1 0 1 0 1

0 1 1 0 1 0 1 0

1 0 0 0 0 1 1 1

0 1 0 1 0 1 1 0

1 1 1 1 0 1 0 0

1 0 1 0 1 0 0 1

0 1 0 1 0 0 0 0

0 0 0 1 0 1 0 0

1 1 1 0 0 1 1 1

0 1 1 1 1 0 1 1

1 0 0 0 1 0 0 1

1 0 0 1 0 0 1 1

Compacted Test

1 Justification Path: "AAAAAAAAA"

8 Justification Paths: "VVVVVVVVV"

9

D2

Cell #12

CELL

m

C-TPES(M)=8*2=4096 9 C-TPIS(M)=8*4 =20197152 7 Propagation Paths: "VVVVV"

5

Guide Input

B C

A1

B1

Full Adder

A2

C2

Z1

B2

Full Adder

A3

C3

n 'A'

Z2

Z3

C-TPES(M)=8*26+4*25+ 5 * 24 =848 C-TPIS(M)=8*46+4*45+5*44* 24+42=38144

O-TPES=3*23+4*22=40 O-TPIS=3*43+4*42=256

O-TPES=7*2 =224 O-TPIS=7*45 =7168

S5

S6

' 0'

Z1

Cell #10

D1

Z2

D2

Cell #3

Z3 Cell #2

Vdd Test

MUX

Test

Cell #6

Q3

Cell #12

MUX

J

L

Cell#5: Cell#9:

Z1Z2Z3Z4Z5Z6D1D2D3 V A V A A V V A A V V A A A V A A V

Q1Q2Q3S4S5S6 A A X A X X A A A X X X A A X X X X X A A X A X X A A A X X X A A X X X X X A X X A X X A X A X X X A A X X A X X X X X X A X X X X X X A X X X

Cout

A3A2A1A0B3B2B1B0Cin CoutZ3Z2Z1Z0 0 1 1 X 0 1 0 1 0 0 0 0 0 0 1 X 0 1 X 0 0 X 0 0 X X 0 X X 0 X X 0 X X 0 0 1 X 1 0 X 1 0 X 0 0 X 1 1 X

X 0 1 X X 0 X 0 X 0 0 X 0 X 1 X 1 X 1 X 0 X 0 X X 0 X 1 X 0 X 1 X 0

0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 X 0 X 0 X 0 X 0 1 X 0 X 0 X 0 X 1 X

X X 1 X X X X X X X X 0 X 0 1 X 0 1 0 0 1 0 0 1 X X X X X X X X X X

0 X 0 0 0 X X X X X X X 0 1 0 0 1

1 X 0 0 0 X X X X X X X 1 0 1 1 0

0 1 1 1 1 0 0 0 X X X X X X X X X

X 0 X X X 1 1 1 1 0 0 0 X X X X X

X X X X X X X X 0 1 1 1 X X X X X

4 Propagation Paths: "XXXAA" "XXAAX" "XAAXX" "AAXXX" O-TPES=42 +42 +42+42=64 O-TPIS=22+22+22+22=16

Conclusions • Fine-Grained Test Requirement Identification

Why ?

Z4 Cell #1

D2

D1

Cell #11

D3

Cell#1: Cell#2: Cell#3: Cell#4: Cell#5: Cell#6: Cell#7: Cell#8: Cell#9: Cell#10: Cell#11: Cell#12:

What ?

RESTORING ARRAY DIVIDER

Original Test Justification Requirements:

H I

K

Cell #7

S4

C-TPES(M)=22*43 +22 *44+22*44 +44 =2560 C-TPIS(M)=42* 23+42*24+42* 24+42=656

D3

Cell #5 D1

• Reduce the Cost of Hierarchical Test Path Construction

' 0'

How ?

Z5 Cell #4

D2

• Analysis of Severity Imposed on Test Paths • Efficient Cell-Level Transparency Extraction • Test Requirement Granularity Identification & Adjustment

' 0'

D3

Z6

Cell #9

Cell #8

Cell #7

S4

S5

S6

' 0'

G=1

F

Z6

Cell #8

4 Justification Paths: "XXVAXXVAA" "XVAAXVAAX" "VAAXVAAXX" "AAXXAAXXX"

DFT for Test Requirement Reduction

n 'A'

D

'0'

D3

Cell #9

TEST PATTERNS - TEST RESPONSES ( RANDOM FILL TURNED OFF)

B3

Full Adder

Non-Compacted Test 17 Distinct Justification Paths: (8 have 3 Xs, 4 have 4 Xs, 5 have 5 Xs)

'A'

A=0

B0

Full C1 Adder Z0

5

O-TPES=4 =1024 O-TPIS=2 5=32

n≥m

Injective Path

'A'

Z5 Cell #4

D2

Proposed Methodology

C-TPES(M)=4=262144 9 C-TPIS(M)=2 =512 1 Propagation Path: "AAAAA"

MODULE 'A'

' 0'

D3 Cell #5

Test Propagation Requirements:

Z1Z2Z3Z4Z5Z6D1D2D3 A V V A V V V V A A V A A V V V A A A A A V V V A A V V A V V A V V V A V A V A A V V A A V A A A V V A A V V V A V V A V V A V V A V A A V A A V V A A A V A A V A A X X X X A X X A A A V X X A V X X A A A V X A V X

9

Guide Inputs Other Inputs

'A'

l

0 1 0 1 1 0 0 1

Symbolic Paths

Q2 Guard Inputs Other Inputs

Z4 Cell #1

Cell #6

7 Distinct Propagation Paths: (3 have 2 Xs, 4 have 3 Xs)

Q1

l

Cin

M

Injection Activation Constants

MODULE Surjective Path ...

D3

Test Justification Requirements:

Cell#1: Cell#2: Cell#3: Cell#4: Cell#5: Cell#6: Cell#7: Cell#8: Cell#9: Cell#10: Cell#11: Cell#12:

A0

0 0 1 1 0 1 0 0

Example

Guard and Guide Inputs

E

D1

8 Distinct Vectors - 7 Distinct Responses

Compacted Test C-TPES C-TPIS 4096 20197152 9216 4718592 425984 6979321856

Guard Input

Z3 Cell #2

Metric Calculation Example (cont’d)

Z[3:0]

Symbolic Paths C- TPES C-TPIS 262144 512 262144 512 238435456 16384

Surjective Path

D2

Cell #11

Q3

A3A2A1A0B3B2B1B0Cin CoutZ3Z2Z1Z0

Experimental Results

'A'

Z2 Cell #3

D1

Cin

1  TPES ( Bit ) = 2  4

if

D1

Z1

Q2

B[3:0]

( Path )

TPES ( Path ) = ∏TPES ( Bit )

Test Inputs k

E q P ' Co

∀P a t h s

if

Cell#1: Cell#2: Cell#3: Cell#4: Cell#5: Cell#6: Cell#7: Cell#8: Cell#9:

Cell #9

Metric Calculation Example A[3:0]

TPIS ( Module ) =

(Path )

∀P a t h s

k≥l

Cell #4

M'CnA0A1A2A3B0B1B2B3S0S1S2S3 V V A X X X A X X X A A A A V V V A X X V A X X A A A A V V V V A X V V A X A A A A V V V V V A V V V A A A A A A A A X X X A X X X A V V V A A A A X X A A X X A A V V A A A A A X A A A X A A A V A A A A A A A A A A A A A A A A A A A A A A A A A A A A

TEST PATTERNS - TEST RESPONSES

Severity Metrics

k 'A'

Cell#1: Cell#2: Cell#3: Cell#4: Cell#5: Cell#6: Cell#7: Cell#8: Cell#9:


FA#1: FA#2: FA#3: FA#4:

Cell #10

Q1

S0S1S2S3


Metrics and Experimental Results ∑ TPES

A3B3

Z3

CinA0B0A1B1A2B2A3B3 A A A V V X X X X X A A A A V V X X X X X A A A A V V X X X X X A A A A

TPES ( Module ) =


A2B2

A3 B3

Z2


A1B1

Modified Test Justification Requirements:

Cell#5: Cell#9:

Z1Z2Z3Z4Z5Z6D1D2D3 V A V A A X V A V V X A A A V X X V

Results ? • Identified Test Requirements Combine: • Generality (for Fast Hierarchical Test Path Construction) • Accuracy (for Low Hierarchical Test Path Severity & Cost)

Future Work ? • Extension for Sequential Logic • DFT For Test Requirement Reduction