Reliability improvement of automotive electronics ...

Microelectronics Reliability 53 (2013) 1235–1238

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Reliability improvement of automotive electronics based on environmental stress screen methodology S.I. Chan a,⇑, J.H. Kang b, J.S. Jang b a b

Reliability Physics Research Center, Korea Electronic Technology Institute, Seongnam, Republic of Korea Department of Industrial Engineering, Graduate School of Ajou University, Suwon, Republic of Korea

a r t i c l e

i n f o

Article history: Received 24 May 2013 Received in revised form 25 June 2013 Accepted 10 July 2013

a b s t r a c t The effectiveness of ESS method for detecting early failure was verified using semiconductor sample with fault latency. Analysis for field failure data based on Kaplan–Meier estimation and fault tree analysis revealed that the failure of semiconductor devices occurred in the early failure period. In order to carry out ESS experiment, artificially fault injected specimen, which had physical damages but performed main function, were prepared. Even though a thermal cycling test was performed to detect fault latency, it was concluded that fault latency was not screened out using the standard ESS method. Ó 2013 Elsevier Ltd. All rights reserved.

1. Introduction A smart car applies new electronic technologies to the traditional mechanical systems. Thus, safety, convenience, and infotainment are being important issues of the development. In a smart car, the architecture of electronic system requires design optimization considering the combination of sensors, ECUs, actuators and user interfaces to perform complex electrical functions [1]. Thus, an increasing number of electronic sub-assemblies affect functional safety of a car [2]. Therefore, automotive electronics require a high level of reliability. Environmental Stress Screening (ESS) is an important methodology in terms of reliability of the automotive electronics. It is considered to be an effective test to find out the component faults and manufacturing defects before the shipment [3]. Patent defects occupy most of failures and are detected by quality inspection or test. Latent defects are dependent upon time and cannot be discovered until changed to patent defects by external stresses in operating environment [4]. One of the typical latent defects in a component is partial damage given by electrostatic discharge (ESD) or electrical overstress (EOS) and so on [5]. Even a low-amplitude ESD pulse can make a latent defect in a semiconductor device by causing leakage current. Moreover, the latent defect can develop into a physical failure in the steady state [6]. When low leakage current such as hundreds of nA occurred, the physical defect was observed in the p–n junction of a semiconductor device. Furthermore, fault latency in device did not show any

⇑ Corresponding author. Tel.: +82 (31) 789 7054; fax: +82 (31) 789 7059. E-mail address: [email protected] (S.I. Chan). 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.07.037

electrical malfunction in the circuit. After performing burn-in, leakage current increased [7]. Burn-in used for the detection of the faults in semiconductor devices applies high temperature and voltage for more than 96 h [8]. On the other hand, the standard ESS conditions, used for automotive electronics, are weaker than the burn-in conditions. The level of temperature range from 60 °C to 110 °C and the test time is as short as 60–90 min. That is because it should consider the operating temperature of both active and passive component. Thus, the currently used ESS condition is considered to have difficulty in detecting the latent defects of semiconductor devices. In this study, the effectiveness of ESS method was verified using semiconductor device with fault latency. Section 2 analyzed field failure data through Kaplan–Meier estimation and did fault tree analysis (FTA). In Section 3, in order to carry out ESS experiment, artificially fault injected specimen, which had physical damages but performed main function, were prepared. A thermal cycling test was performed to detect fault latency. Section 4 discusses the effectiveness of standard ESS based on the test result. Finally, Section 5 concludes the paper. 2. Field information analysis The field failure data of automotive electronics was analyzed, especially for the audio and AVN (Audio Video Navigator). The data was limited to that collected within the warranty period. 2.1. Life data analysis Using Kaplan–Meier estimation, we analyzed the field life data of the audio. Plotting the time to failure data points on the Weibull plot produced the graph shown in Fig. 1.

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Fig. 1. Weibull plot of failure distribution. Fig. 2. Sample preparation sequence using fault injection.

The result of the Weibull analysis suggests that the value of shape parameter (b) is 0.6. This value indicates a decreasing failure rate known as infant mortality. The value of the shape parameter generally indicates the state of the failures (b < 1: early failures, b = 1: random failures, b > 1: wear-out failures).

2.2. Fault tree analysis ESS accelerates fault latency of a component and manufacturing defects by environmental stress. The ESS condition should be adjusted to the type of a failure mode and mechanism in order to maximize the precipitation of latent defects [9]. Therefore, to perform ESS, the failure modes and mechanisms of automotive electronics should be identified. FTA is one of the reliability analysis technique, which deals with failure modes and causes. Starting from top events, the analysis proceeds by determining how these can be caused by individual or combined lower level failure events [3]. Table 1 shows the FTA template for identifying failure stress. In this table, a failure is analyzed in the perspective of three levels. A component is a non-system level, a module consists of electrical or electronic components performing a specific function, and a product is the group of interconnected or assembled modules, which performs overall functions [10].

Fig. 3. ESS condition and failure analysis.

The defects of electronics always fall in the category of design, component, or process related [11]. Therefore, the failure site was classified into design, component, manufacturing and others. Failure stress is defined as natural environmental stress (temperature, humidity, etc.) and induced environmental stress (ESD, EOS, etc.). The induced environmental stress comes from human or equipment and it directly or indirectly affects the reliability. Root cause or failure mechanism is a result of reacting to environmental stress with the physical or chemical and mechanical operations [12]. Table 2 shows the FTA result for audio and AVN. The component failures occupied 25.8%, which included LCD panels, switches, and so on. The failures from manufacturing process accounted for

Table 1 FTA template for identifying failure stress. Product Failure mode a

Module Failure mode

Components Failure mode

Number of failures

Root cause or mechanism

Failure sitea

Failure stress

Failure Site: Component, Design, Manufacturing, Induce, Software, System Management, Mechanical Parts.

Table 2 FTA result of field failure data.

Failure rate (%)

Component

Design

Manufacturing

Induced

Software

System managements

Mechanical parts

25.8

7.1

19.3

6.2

11.9

25.6

3.2


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Fig. 4. Leakage current of device after ESD injection. (a) 1000 V injection, and (b) 800 V injection.

19.3%, which were cold solder, poor adhesive of cable, etc. In addition, the failures of semiconductor devices occupied 6.2%, which were caused by ESD or EOS. 3. Experimental methodology 3.1. Sample preparation using fault injection Fault injection is a technique for improving the coverage of a test by introducing faults into the target system. In addition, hardware fault injecting using direct contact with circuit pins is the most common method of hardware implemented fault injection [13]. Using the fault injection method, we made fault latency in an integrated circuit (IC). The IC was given a physical damage in its p–n junction, but the main function of it was qualified. The IC was composed of small body of 14 14 mm2 in size, 1.4 mm in height and fine pitch of 0.5 lm with the LQFP package. In order to make fault latency, we applied ESD stress to IC. ESD stress of component level is classified into the human-body model (HBM) and the machine model (MM). The warranty level of the component used for automotive electronics against ESD is up to 2000 V for HBM and up to 200 V for MM [14–16]. ESD was injected from 2000 V to 6000 V for HBM and from 200 V to 800 V for MM. AEC-Q100 defines that the highest level of HBM > 8000 V and the highest level of MM > 400 V. Therefore, the stress level we used is very high [16]. ESD model test method was implemented in the second edition of IEC 61340-3-1 and IEC 61340-3-2 [14,15]. The electrostatic discharge was simulated using the KeyTek MK2 ESD simulator. During the experiment, the pin under test was evaluated for related damage by examining the current (I)–voltage (V) transfer characteristics. After the ICs with fault latency were made, they were mounted on the circuit board of a product. The main function was examined. If the product was functionally qualified, specimen preparation for ESS was completed. Fig. 2 shows the sample preparation sequence using the fault injection.

Over warranty level of ESD stress was applied to ICs, the p–n junction was damaged. It caused increase of leakage current. Fig. 4 shows the increase of leakage current of ICs after the ESD stress test. For HBM, leakage current did not increase even when we injected 6000 V. However, it significantly increased at 800 V for MM. In addition, the wave pattern of current at 1000 V was similar to that of short circuit. After making fault latency in ICs, the electrical characteristics of the ICs was evaluated by a function test as they were mounted on products. As a result of function measurement, the products that showed the wave pattern of (a) in Fig. 4 did not work. However, among the products showing the wave pattern of (b), only two specimens of them were functionally qualified.

3.2. ESS test and failure analysis

4.2. ESS test and failure analysis

Thermal cycling test is the most effective method to find out the latent faults of electronics [17]. Therefore, in this study, thermal cycling test was chosen for ESS of automotive electronics.

The ESS test was carried out with just one of the two samples having latent defects. The other one was used for the failure analysis to observe the existence of a defect in the IC.

Fig. 5. Experimental setup for the ESS test.

Considering the temperature characteristics of the passive component, the test temperature was set between 40 °C and 85 °C with maximum 30 min dwell time. Furthermore, a sample was powered on for 10 min and off for 5 min, repeatedly during the test. The test was done for 2 h per cycle and continued for 48 h. Besides ESS, p–n junction damage of IC was analyzed by emission microscopy (EMMI) technique. Fig. 3 shows the ESS condition and failure analysis. 4. Result and discussion 4.1. Fault injection and ESS test

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In order to carry out ESS experiment, artificially fault injected specimens, which had physical damages but performed main function, were prepared. Even though a thermal cycling test was performed to detect fault latency, it was concluded that fault latency was not screened out using the standard ESS method. In order to minimize infant failures of hardware in automotive electronics, an ESS condition, which can detect fault latency in ICs, must be developed. References

Fig. 6. Leakage current at p–n junction.

Consequently, the standard ESS test condition, thermal cycling for 48 h, was not able to screen the product with a defective IC. The ESS conditions must be set to precipitate a specific type of defect. Therefore, for other types of defect, different environmental conditions are needed [18]. The test period of ESS is generally 2– 4 h and as long as 24 h [19]. The test result of thermal cycling cannot represent all available ESS methods because we used standard test method and only one specimen. However, it can be used for a reference to design ESS. Fig. 5 shows the experimental setup for the ESS test. To observe the existence of the p–n junction damage in IC, EMMI analysis was performed. As a result, leakage current caused by physical damage was detected. EMMI analysis is well known to be very effective to detect physical damage, both at gate and junction levels [20]. Despite the leakage current, specimen functioned normally. Therefore, it can be inferred that leakage current is allowed in the product. Fig. 6 shows the leakage current at the p–n junction caused by the fault injection. 5. Conclusion Analysis for field failure data based on Kaplan–Meier estimation and fault tree analysis revealed that the failure of semiconductor devices occurred in the early failure period.

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