Reliability Prediction for TFBGA Assemblies - IEEE Xplore

IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 29, NO. 2, JUNE 2006

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Reliability Prediction for TFBGA Assemblies Zoran Radivojevic, Yasir Abdul-Quadir, Pirkka Myllykoski, and Jukka Rantala

Abstract—One of the key hot topics in dense large scale integration packaging technologies is to reduce the thermomechanical stress caused by a mismatch of coefficients of thermal expansion among material employed. Nearly all manufacturers of portable electronics products perform several kinds of physical tests in the development cycle to evaluate reliability of the products. In this paper, results obtained by accelerated thermal and power cycling tests by using thin fine pitch gall grid array (TFBGA) packages are reported. Power-cycling stands for a lifetime acceleration method which is close to the real environmental conditions of many electronic products. For this purpose, a set of TFBGA thermal test packages were designed and manufactured for reliability assessment of solder joint interconnections. The assemblies consisted of an array of polysilicon resistors surrounding a sensing diode for accurate temperature measurements. The package uses a qualified bill of materials including a 36-mm2 dummy die. Each assembly was designed to perfectly reproduce the thermomechanical behavior of the mass production packages by several semiconductor manufacturers. This package is used in telecom wireless application where it offers high density input/output solution for advanced application-specific integrated circuit (IC) devices a system on chip ICs. Both experiments and simulations were carried out to locate the position of the most critical parts. Complexity of structural package characteristics was examined by using finite-element method modeling methodology. A strain energy based model was employed to locate the most vulnerable parts in the package and predict failure rates. Index Terms—Power cycling (PC), reliability, solder joint.

I. INTRODUCTION

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HERMAL fluctuations caused by power dissipation in an electronic package during normal operation causes strains and stress in the package and solder joint interconnections. These result from difference in material properties and coefficient of thermal expansion (CTE) between various components of the package. The thermal fluctuations are produced by heat dissipated in the electronic components or by environmental temperature changes. Cyclic repetition of such fluctuations produces strain and stresses, which ultimately lead to the failure of the solder joints in fatigue. To assess long-term reliability of electronic components, lifetime acceleration experiments are necessary. In this work, both power cycling (PC) and thermal cycling (TC) experimental approaches have been performed to obtain valuable experimental information. The PC experiment is a substitute for approach where heat is generated in the die. This approach is quite close to the real operational conditions.

Manuscript received August 5, 2003; revised October 18, 2003. This work was recommended for publication by Associate Editor L. Nguyen upon evaluation of the reviewers’ comments. Z. Radivojevic and J. Rantala are with the Nokia Research Center, Helsinki FIN-00045, Finland (e-mail: [email protected]). Y. Abdul-Quadir and P. Myllykoski are with the Nokia Technology Platforms, Helsinki FIN-00045, Finland. Digital Object Identifier 10.1109/TCAPT.2006.875889

Fig. 1. Test vehicle used in power and TC experiments: (a) single card with several TFBGA packages and (b) 15 cards in a rack connected to the DAQ system.

Fig. 2. Temperature profiles in PC lifetime acceleration experiments. Two upper curves present values for two components from the same card. The temperature was measured on the component surface by thermocouples. The two lower curves are temperatures measured on the PWB surface 3 mm away from the component corner. (Color version available online at http://ieeexplore.ieee.org.)

1521-3331/$20.00 © 2006 IEEE

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Fig. 3. IR image of the test vehicle with TFBGA components. The image was taken 6 min after the components were powered when a steady state temperature regime was reached. (Color version available online at http://ieeexplore.ieee.org.)

On the other hand, the TC approach is a substitute for environmental temperature cycling where heat was generated outside and absorbed by the package. For our studies, we have constructed a test-vehicle for PC and TC to determine the fatigue behavior of near-eutectic Sn–37Pb solder joints in TFBGA thermal test packages. The experimental part involved construction of the test-vehicle with a set of TFBGA components mounted on an eight-layer printed wiring board (PWB) as presented in Fig. 1(a)–(b). Several TFBGA components were mounted on a single card. A set of 15 cards was assembled in a rack connected to the data acquisition system (DAQs). A set of several power supplier units were constructed to provide stable powering of the chips. Each unit had a possibility to adjust the power profile directly by the DAQ system. The lifetime acceleration and failure provocation was performed by dedicated PC introducing severe but controlled thermal transients and gradients. The applied power for each chip was 2.3 W. The PC profile was 6-min 2.3 W and 4-min power-off ( power-on with 0 W). This power profile resulted in a temperature response 125 C measured on the component-surface by of means of attached thermocouple and at end of the power cycle when the system reached steady state equilibrium. At the same 136 C time corresponding junction temperature was measured by a sensing diode. Each chip contained a sensing

Fig. 4. Directly measured junction-to-ambient thermal resistances by using T3Ster device. Two curves stand for the resistances of two TFBGA components on the same card. (Color version available online at http://ieeexplore.ieee.org.)

diode implemented inside and placed at the chip center. These sensing diodes are able to measure junction temperatures directly. Switching off the power resulted in a cooling of the system reaching a component-surface temperature of 22 C. The temperature profile in the PC experiment is shown in Fig. 2. Furthermore, 3 mm from each of the packages, a thermocouple was mounted on the PWB surface to measure

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Fig. 6. SEM microphotograph of the crack propagation.

Fig. 5. Some of typical failures observed in lifetime acceleration by power and TC experiments with TFBGA packages.

temperature and have additional information for validation of simulation models. A corresponding IR temperature map for the whole card is shown in Fig. 3 in steady-state regime when the system reached equilibrium. Temperature profile in corresponding TC experiment was consisted of 11 min ramp-up and 14 min ramp-down with 10 125 C and 5-min dwell-time at min for dwell-time at 22 C. This profile was selected in order to be consistent with PC conditions and have a possibility for comparison with results obtained elsewhere [1]. Solder joint failures were detected by monitoring the daisy-chain resistances as a function of the time (or number of cycles). Daisy-chain structure covered almost 50% of the all input/output (I/O) channels. Afterwards, exact failure location was obtained by microsectioning and optical inspection with high magnification. In addition to lifetime acceleration measurements, junchave been obtained tion-to-ambient thermal resistances directly by fast transient measurements using T3Ster device

Fig. 7. Failure rates observed by using TFBGA packages in power (circles) and thermal (squares) cycling experimental conditions.

(within EU-PROFIT collaboration project). Obtained values are presented in Fig. 4. This information later served for adjusting an adequate thermal model suitable for implementation into finite-element method (FEM) simulation for stress analysis. Generally speaking, a number of models have been developed to describe the stress-strain behavior of solder joints in fatigue and the resulting crack initiation and growth that leads to failure.

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thermal cycles which was samples have failed after % . This difference of 30%, in about 30% higher than number of cycles to failure, is probably caused by more severe and stressful conditions seen by the solder joints when exposed to PC and anisothermal temperature variations. After microsectioning and inspection of the samples loaded by both TC and PC conditions it was possible to locate the most risky areas when plotting distribution of failures on the map of package solder joints. It was clear that the most vulnerable part is the area close to the die edges where the highest thermal transients and gradients are observed. Results of both lifetime acceleration approaches (PC and TC) were consistent. The most probable area for a crack formation and growth is the area between the solder balls and the package (component side of the interconnections). III. SIMULATIONS

Fig. 8. Results of FEM simulations for PC conditions: (a) location of the most critical solder joint (marked by array) and (b) plastic work energy distribution in critical solder joints after three power cycles. (Color version available online at http://ieeexplore.ieee.org.)

A global-refined quarter model of the package on the PWB was used in FEM analysis. First, an adequate thermal model was built and validated by using thermal measurements (see Figs. 3 and 4). Then it was implemented in an FEM thermomechanical model for stress analysis. Material properties were assumed to be isotropic and elastic for all materials except the PWB, substrate, and solder material. Sn–37Pb solder material was treated by the Anands viscoplastic model using Darveaux’s [2] parameterization, which allows strain-rate dependent plasticity. The PWB and substrate were modeled with orthotropic material properties, having different CTE, modulus, and thermal conductivity values in thickness direction. Results of the stress analysis are presented in Fig. 8 for PC conditions. , can be described by Thermal fatigue life, Coffin–Manson [3] and Norris–Landzberg [4] equations. More recently, Darveaux’s model and corresponding set of (1) has been used extensively for Sn–Pb solder joints to calculate their lifetime

Certain numbers among these deal with a “damage integral” . variable such as plastic work energy density %

II. EXPERIMENTAL RESULTS The stress seen by some of the joint balls was enough to create a whole or half-break of the solder joint functional interconnection. A typical microphotograph for the failures observed is shown in Fig. 5. Fig. 5(a) shows the total breakage of the interconnection between the joint and the package. Fig. 5(b) shows a half-break and gold traces on pad of the PWB. Finally, Fig. 5(c) shows a break of half of the interconnection. Fig. 6(a)–(b) present an SEM photograph of solder microstructure showing the fracture on the component side. The SEM picture shows that the solder microstructure has coarsened making lead-phases and tin-phases clearly distinguishable. Furthermore, Fig. 6(b) indicates that the largest grain boundary sliding occurs at the Sn–Sn boundaries and within the Sn phase. In the PC testing conditions, half of the samples have failed PCs as preafter exposure to the certain number of % sented in Fig. 7. In the case of TC testing conditions, half of the

(1)

stands for the number of cycles to crack initiation, is the crack growth rate, and – are constants. Darveaux’s model correlates plastic work energy density with crack initiation and crack growth rate. In this work, we have used the Darveaux model modified according to Nokia specifications [5] to calculate thermal fatigue life for both PC and TC conditions. The set of (1) allows direct correlation of the fatigue is known. life if plastic work energy density per cycle . Three We have used a validated FEM model to calculate cycles has been simulated before extracting value. Furthermore, by using these values and set of the constants we have been able to obtain failure rates by simulations as PCs and thermal-cycles for power % % and TC conditions, respectively. These simulation predictions were correlated with experimental results within a difference of about 35%. where

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Fig. 9. Correlation between applied power, ambient temperature, and failure rate obtained as result of optimization procedure. (Color version available online at http://ieeexplore.ieee.org.)

IV. OPTIMIZATION OF LOADING CYCLE AND TESTING TIME Once validated, the simulation model allows variation of boundary conditions and testing parameters. The goal in the optimization procedure was to define a PC that maximizes the plastic work energy density. The second attempt was to minimize testing time and achieve information about faster life acceleration conditions. In addition, this procedure yielded information about harsh conditions where reliability is challenged. To achieve intended goals, a neural network’s based response surface model was employed. The following variables were subjected to optimization: ; • ambient temperature ; • power level • power-on time . Result of the optimization, which correlates applied powerlevel , ambient temperature , and failure rate is presented in Fig. 9 By using the correlation it was possible to optimize (minimize) the number of cycles to failure. A function has been defined as a function of —power —ambient temperature ( level, —power-on time, and was kept as a constant value). Initial setting was settled to be and then the optimization procedure was executed. The procedure converged in a value of yielding a set of loading and boundary conditions . This set of parameters stands for a harsh working environment where plastic work energy accumulation

is very efficient causing damage in solder joint interconnections. In the second attempt, the time needed for testing was optimized to receive information about faster lifetime accelerawas tion conditions. Temporary product formed and used in the optimization procedure. Obtained results indicated that faster lifetime acceleration is achieved by using higher power levels and power-on time of about 0.5 min at lower ambient temperatures. These results showed that plastic work and damage accumulation in the solder joints is more efficient in relatively short cycles around high dissipation packages where functional cycles are repeated many times. V. CONCLUSION PC and TC life acceleration approaches have been combined with FEM simulations to predict reliability of solder joint interconnections. Results of the PC yielded in about 30% failure rate presenting the effect of more efficient lower stress accumulation seen by the solder joints when exposed to conditions closer to the real field of usage (anisothermal temperature field). FEM simulations matched experimental results within a difference of about 35%. Further improvements in prediction power of the FEM methodology can be achieved by performing more PC experiments by using different types of package working in different environmental conditions. Dominant failure mode in both (PC and TC) approaches was a fractured solder joint on component side. Solder fatigue had caused fractures propagating mainly through tin-phase

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boundaries. The most vulnerable place is area between the solder balls on the component side and around the silicon-die edge. This is consistent for both TC and PC conditions. Most critical solder joints were located close to the edges of silicon die, which stiffens the package and increases plastic strain on solder joints. The package under investigation showed very high reliability for current applications. Provocation of failure modes has been done in accelerated conditions. Furthermore, by using a neural networks-based optimization technique, information about harsh boundary conditions has been received. This information is also useful when managing thermal environment and reliability of solder joint interconnections in case of increased component density in the future. It also gives a basis for development of faster reliability assessment methods.

Yasir Abdul-Quadir received the M.S. degree from the University of Science Malaysia, Pulau Pinang, in 1996 and the Ph.D. degree in microelectronics engineering from University College Cork, Cork, Ireland, in 1998. He started working at Nokia Technology Platforms, Helsinki, Finland, in April 2001. His main research interest is thermal management and solder joint reliability. In his current position he is working on thermal management of mobile phones and systems and improvement of solder joint reliability.

ACKNOWLEDGMENT The authors wish to thank all of the members of the EU PROFIT Collaboration Project for fruitful scientific exchange and their assistance in fast transient measurements. REFERENCES [1] V. S. Sastry, J. C. Manock, and T. I. Ejim, Effect of Thermal-Cycling Ramp Rates on Solder Joint Fatigue Life. Princeton, NJ: Lucent Technologies, 2001. [2] R. Darveaux, “Eff. of simulation methodology on solder joint crack growth correlation,” in Proc. 50th Electron. Comp. Technol. Conf., Las Vegas, NV, May 2000, p. 1048. [3] L. F. Coffin Jr., “A study of the effects of cyclic thermal stress on a ductile metal,” Trans. ASME 76, p. 931, 1954. [4] K. Norris and A. Landzberg. (1969, May) Reliability of controlled collapse interconnections. IBM J. Res. Dev., pp. 266–271 [5] Nokia Research Center, “FEM Thermomechanical Reliability Simulations—Nokia Standard Procedure,” Tech. Rep., Dallas, TX, Apr. 2000.

Zoran Radivojevic received the M.S. and Ph.D. degrees in computational simulations and physics from the University of Jyväskylä, Jyväskylä, Finland, in 1999 and 2001, respectively. He is a Principal Scientist at Nokia Research Center, Helsinki, Finland, where he has been working since 2001. He has worked with several EU laboratories. He has written over 60 publications in different fields ranging from fundamental and applied physics to advanced materials and numerical simulations.

Pirkka Myllykoski received the M.Sc. and Ph.D. degrees in material and information science from the Helsinki University of Technology, Helsinki, Finland, in 1993 and 1997, respectively. He is a Senior Specialist at Nokia Technology Platforms, Helsinki, where he has been working since 2000. He has more than 30 publications in international journals and conferences in the field of metallurgy, information science, and numerical simulations.

Jukka Rantala received the M.Sc. and Ph.D. degrees from the University of Helsinki, Helsinki, Finland, in 1988 and 1993, respectively. Currently, he is a Senior Research Manager with the Nokia Research Center, Helsinki. Previously, he was affiliated with the University of Helsinki, Neste Ltd., the Institute for Manufacturing Research, Detroit, MI, the Institute for Polymer Research, Stuttgart, Germany, and the Academy of Finland. He has authored or coauthored more than 60 refereed articles and book chapters.