Representation of strained gate-all-around ...

Microelectronic Engineering 162 (2016) 12–16

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Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog applications Rouzbeh Molaei Imen Abadi, Seyed Ali Sedigh Ziabari ⁎ Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran

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Article history: Received 2 January 2016 Received in revised form 1 April 2016 Accepted 19 April 2016 Available online 27 April 2016 Keywords: Junctionless tunnel field effect transistor Strain Band-to-band tunneling Cut-off-frequency

a b s t r a c t In this paper, we investigated gate-all-around silicon nanowire (NW)-based junctionless tunnel field effect transistor (FET) which is called junctionless tunnel NWFET (JL-TNWFET) with the impact of variation of amount of uniaxial tensile strain on band-to-band tunneling (BTBT) injection and electrical characteristics. The tunneling model is first calculated for measurements of gate-controlled BTBT in the JL-TNWFET and is compared with the strained JL-TNWFET with similar technology parameters. The simulation results show that the JL-TNWFET have potential for low-operating-voltage application (Vdd $_amp_$lt; 0.4 V) and represent high ION/IOFF ratio and steep subthreshold swing over many decade while encompassing high ON-state currents. Whereas, the strained JL-TNWFET due to thinner tunneling barrier at the source-channel junction which leads to the increase of carrier tunneling rate shows excellent characteristics with high ON-current, superior transconductance (gm) and cut-off frequency (ƒT). © 2016 Elsevier B.V. All rights reserved.

1. Introduction In recent years, some novel devices based on different mechanisms have been reported in response to the limit of the traditional MOSFET scaling. The tunneling field effect transistors (TFETs) is one of the alternative devices to replace CMOS technology, which is most suitable for low-power applications [1]. Because such devices utilize tunneling injection of carriers through a tunneling barrier rather than thermionic injection over a barrier, and the barrier width can be controlled by the gate voltage, they have good immunity to short channel effect, drain induced barrier lowering, and superior electrostatic control (lower OFFcurrent and steeper subthreshold swing) which enabling transistor operation at voltage below 0.5 V [2,3]. However, quantum mechanical tunneling in these devices is insufficient due to the relatively large band gap (1.1 eV), indirect energy gap of Si, and therefore the ONcurrent in such transistors is limited. For achieving higher tunneling currents, semiconductors with lower band gap Eg are required [4,5]. III-V materials with direct band gap offer distinguished advantages in achieving high tunneling currents [6,7]. However, their adaptability with Si processing and the poor high-k interface are still the main limitations for III-V tunnel FETs. Also, Strain engineering technologies to enhance MOSFETs mobility have been extensively investigated [8] and already widely used in mass production. Moreover, it has been shown that tensile strained Si significantly improves tunneling currents [9, 10]. This advancement stems from the effect, that uniaxial strain in Si ⁎ Corresponding author. E-mail addresses: [email protected] (R. Molaei Imen Abadi), [email protected] (S.A. Sedigh Ziabari).

http://dx.doi.org/10.1016/j.mee.2016.04.016 0167-9317/© 2016 Elsevier B.V. All rights reserved.

nanowires along the [110]-direction picks up the subband degeneracy of the valence and conduction bands, leading to reduction of the effective mass m* of electrons and holes [11]. Furthermore, SiGe is an attractive material for make utilizing in TFETs because of its lower Eg [12,13]. However, recently a new structure named junctionless tunnel field effect transistor (JLTFET) has been proposed which is tunnel FET without any abrupt doping profile [14,15,27]. It has presented good ON-state current and low subthreshold swing as blends advantages of JLFETs and TFETs. JLTFET also feature lower subthreshold slope than conventional MOSFET and JLFET at the room temperature opens new future for low power application devices [16]. In this paper, we have examined a gate-all-around junctionless tunneling nanowire-based FET (JLTNWFET) structure with and without uniaxial tensile strain, in order to achieve superiority of all three the JLFET, the conventional TFET and uniaxial tensile strain incorporated together. Then, we present the simulation results exhibiting considerably enhanced gate-controlled bandto-band tunneling (BTBT) current and radio frequency (RF) metrics due to using highly uniaxial tensile strained Si (Eg = 0.865 eV) in the JLTNWFET. 2. Device structure and simulation Fig. 1 shows a schematic of the gate-all-around junctionless tunneling nanowire field effect transistor (JL-TNWFET) structure in conjunction with the lengths and thickness of layers, which used in simulation. The simulated device is fundamentally a junctionless transistor uses n+-doped strained silicon along the [100]-direction with uniform doping concentration of (1 × 1019 cm− 3) which placed throughout the source, drain and channel regions. The proposed JL-

R. Molaei Imen Abadi, S.A. Sedigh Ziabari / Microelectronic Engineering 162 (2016) 12–16

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Fig. 1. (a) Sketch of the gate-all-around JL-TNWFET (b) and its cross section along z-axis. For the gate-all-around JL-TNWFET, the gate near the tunneling region is named as middle-gate (MG), and the other is denoted as side-gate (SG).

TNWFET utilizes two isolated gates (Middle-Gate, Side-Gate) with two work functions to treat like a tunnel field effect transistor (TFET). The length of the channel is 40 nm and the length of the source and drain regions is 30 nm. The radius of the strained nanowire (Tsi) is on the order of 5 nm, oxide thickness (Tox) is 2 nm and the isolation layer in between middle-gate (MG) and side-gate (SG) electrode is 2 nm which works as spacer between the gates. The gate-all-around structure is used to provide better electrostatic controllability of gate over channel. Preset parameters used for device simulation of JL-TNWFET as in Fig. 1 are tabulated in Table 1. In order to make the layers beneath middle-gate (MG) and side-gate (SG) intrinsic and p-type, respectively, we have chosen 4.38 eV and 5.92 eV for the MG and SG electrode, to increasing electrons populations below the gate and give the superior result in terms of ON/OFF-state current values for the both devices. The integration of MG and SG together in the fabrication process, whose workfunctions are different, could be done by using the techniques as reported in Refs. [17–19]. The formation of the isolation layer with thickness of 2 nm of SiO2 could be done either by using a sputtering process or by a modern photolithography process (such as electron beam lithography, X-ray lithography, extreme ultraviolet lithography, and ion projection lithography) after formation of the field oxide by wet oxidation. The key parameter of the investigated device is the constant uniaxial tensile strain which has an equal level along the device direction. The high level of uniaxial tensile strain along the device induces a local band gap constriction. The band gap (Eg) corresponding non-strained Si JL-TNWFET is assumed to be 1.1 eV, similar to bulk Si. Depending on the earlier reported works in [20,21], 0.2 eV band gap constriction in Si can correspond to 3 or 5 GPa uniaxial tensile stress, respectively. Both expected amounts of stress are below the yield strength of Si (7 GPa for bulk Si [22]) and therefore, $_amp_$gt;0.2 eV local constriction of band gap can be accessible by local strain engineering. In this way, we have assumed the band diagram profile along the channel for reference JL-TNWFET with band gap (Eg) = 1.1 eV and also, for highly constant strain profile channel with band gap (Eg) = 0.865 eV. Fig. 2 presents the (a) OFF-state, and (b) ON-state of the simulated energy band diagrams of the device that illustrate the basic operation of JLTNWFET versus strained JL-TNWFET. In the absence of gate voltage, the tunneling barrier width in between source and channel junction in the case of JL-TNWFET is large enough to give extremely small current Table 1 Preset Parameters for device simulation of JL-TNWFET. Parameter

Value

Source/drain/channel doping (ND) Effective oxide thickness (Tox) Middle-gate workfunction (ФMG) Side-gate workfunction (ФSG) Gate length (Lg) Source/drain length (Ls,d) Channel thickness (Tsi) Supply voltage (VDD) Permittivity of gate dielectric material (εd)

1 × 1019 cm−3 2 nm 4.38 eV 5.92 eV 40 nm 30 nm 10 nm 1V 3.9

Fig. 2. (a) OFF-state (VD = 1 V, VMG = 0 V) and (b) ON-state (VD = 1 V, VMG = 1 V) energy band diagrams of JL-TNWFET and strained JL-TNWFET.

(IOFF) and the probability of band-to-band tunneling of electrons is negligible. However, in the strained JL-TNWFET, as expected, the tunneling barrier between source and channel reduced as we apply uniaxial tensile strain. This feature of shortening the OFF-state tunneling barrier has key function in increase of BTBT current, as well as increasing the transition probability of the carriers. As the gate voltage become increasingly positive from the OFF-state, both of JL-TNWFET and strained JL-TNWFET bands at the source-end will bend more and making the tunneling barrier increasingly thinner. Accordingly, the strained device formed the narrower tunneling barrier at the source-channel interface for conducting a high ON-state tunneling current. The OFF-state (a) and ON-state (b) of the electric field profile of the JL-TNWFET against strained JL-TNWFET are shown in Fig. 3. In the OFF-state, for both structures due to the formation of band diagram looks like N+-IP+ doped device structure, it has been created two electric field peaks at the source-channel and drain-channel junction. Simultaneously, the strained JL-TNWFET because of smaller tunneling barrier has lower values of lateral electric field which leads to the increase of carrier tunneling. However, in the ON-state, due to the presence of gate-tosource voltage, the band diagram profile behave similar to N+-N-P+ doped device structure, so it has been created one strong electric filed peak at the source-channel junction which implicates the tunneling probability goes up in that region and the reason of this superiority is the further quantum tunneling phenomenon. Although, the strained JL-NWFET has performance enhancement because of the application

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Fig. 3. (a) OFF-state (VD = 1 V, VMG = 0 V) and (b) ON-state (VD = 1 V, VMG = 1 V) electric field profile of JL-TNWFET and strained JL-TNWFET.

of uniaxial tensile strain which creating thinner tunneling barrier at the source-channel junction.

intrinsic carrier concentration required in the expressions for Shockley-Read-Hall (SRH) recombination. To capture the effect of temperature dependent mobility, a concentration dependent mobility (CONMOB) model and parallel and perpendicular electric field dependent mobility (FLDMOB) model are used. Due to the presence of high doping concentrations band gap narrowing (BGN) and auger recombination (AUGER) models are included in the simulations. Moreover, in order to assuming high impurity atom in the channel and also to taking into account an interface trap (or defect), the Shockley-Read-Hall (SRH) recombination mode is enabled [26]. In fabricated tunneling FETs, the amount of BTBT currents due to trap-assisted tunneling can be remarkable in the subthreshold region. However, because the traps are process sensitive, voluntary supposition is beyond the domain of simulationbased study. Therefore, this investigation were utilized defect-free TFETs. The transfer characteristics of JL-TNWFET and comparable strained JL-TNWFET at drain-to-source voltage Vds = 1 V are shown in Fig. 4. The OFF-state current IOFF of JL-TNWFET which is determined as the drain-to-source current Ids at Vgs = 0 V and Vds = 1 V, as well as the ON-state current ION of Si-control JL-TNWFET which is determined as the as the drain-to-source current Ids at Vgs = Vds = 1 V, is lower than that of strained JL-TNWFET. It is observed that, a significantly enhance of ON/OFF-state BTBT current has shown in strained device with uniaxial tensile strain. Therefore, the ION/IOFF ratio decrease to 4.872 × 107 from 2.365 × 109, which is specified within the best possible value of JL-TNWFET by adjusting the MG and SG electrode work function in the simulation. Furthermore, it is clear from the inset, the JL-TNWFET gives the improved average subthreshold swing SSAVG due to the higher slope of drain-to-source current Ids than that of strained one. Also, the ON-state tunneling current of both Si-control and strained JL-TNWFET were measured at the threshold voltage in which for the JL-TNWFET, the lower amount of drain-to-source current 2.195 × 10−12 A/μm is obtained at 0.6 V of gate-to-source voltage. However, the strained device is obtained the value of 1.918 × 10−8 A/μm at 0.6 V of gate-to-source voltage. Enhancement of this current of the strained JL-TNWFET are due to reduction of tunneling barrier width at source-channel junction resulting in the improving of lateral electrical filed, consequently improving the carriers tunneling probability. Furthermore, for more accurate investigation of JL-TNWFET versus strained JL-TNWFET, radio frequency (RF) performance inquired with the use of different amount of uniaxial tensile strain and its impact on the analogous behavior of these structures. The main figures of merit for evaluate RF performance are transconductance (gm) and cut-off frequency (ƒT). The transconductance is defined by ∂IDS/∂VGS for a given

3. Results and discussion All simulations evaluated using 2-D TCAD simulator Silvaco Atlas [23] which uses Kane's band-to-band tunneling (BTBT.KANE) model [24,25] to account for the amount of band-to-band tunneling (BTBT) generation rate per unit volume (GKane) of carriers which tunnel form valence band of source region to conduction band of channel. The Kane model assumes that the electric field is constant over the tunneling length. The drain current ID , BBT is derived by integration of the band-to-band tunneling (BTBT) generation rate per unit volume of the device [23]: ID;BBT ¼ q∫GKane dV GKane ¼ AjEj5=2 exp

ð1Þ −B jEj

ð2Þ

In this expression, |E | is the magnitude of electric field and the parameters A = 9.6615 × 1018 cm− 1 s−1v−2 and B = 3.0 × 107 v/cm are the material dependent parameters in Atlas model. Moreover, we comprise the effect of Fermi-Dirac statistics in the calculation of the

Fig. 4. Transfer characteristics of JL-TNWFET and comparable strained JL-TNWFET. The inset shows the corresponding subthreshold swing as a function of gate voltage.


drain-to-source voltage. Fig. 5 shows the transconductance of the JLTNWFET versus strained one with different value of uniaxial tensile strain (1GPa $_amp_$lt; ε $_amp_$lt; 5GPa) as a function of the gateto-source voltage for Vds = 1 V. It can be observed that due to increasing the value of tensile strain from 1 GPa to 5 GPa for the strained JLTNWFET, the amount of transconductance change remarkably. This is because of current conduction in the TFETs occur by carrier tunneling in between source and channel junction and also effective width of tunneling barrier will change due to exert of different amount of uniaxial tensile strain. As we already know, the cut-off frequency ƒT is one of the competency criteria for analogue applications. The cut-off frequency is defined by ƒT = gm/2πCG, wherein gm and Cg are the transconductance and the gate capacitance, respectively. The gate capacitance is defined by CG = ∂Qch/ ∂Vgs in which Qch is the total charge of the Si nanowire channel. Here we assume that gate electrostatic control is good, so that the charge in the channel is equal to that in the gate when parasitic capacitance is negligible [27]. Fig. 6 illustrates cut-off frequency (ƒT) characteristics of the JL-TNWFET against strained JL-TNWFET as a function of the gate-tosource voltage. As Vgs increases, number of electrons injected from source-channel interface by means of band-to-band tunneling is increased, hence, frequencies starts increasing with gate bias until it reaches its maximum value at a specific gate bias. It can be seen in the figure that utilizing uniaxial tensile strain in the JL-TNWFET leads to increases the ƒT over the entire range of gate-to-source voltage. It is clear that in the strained JL-TNWFET with downscaling of the amount of energy band gap and as a result increasing uniaxial tensile strain from 1 GPa to 5 GPa in order to shortening of tunneling barrier, gm increased and this device metric is responsible for significant improvement of cutoff frequency. It is noteworthy; the value of cut-off frequency for JLTNWFET is ~ 0.8 GHz which has a negligible value against strained JLTNWFETs. As a result, strained JL-TNWFET can be superior candidate for analogous application due to utilizing thinner tunneling barrier at the source-channel interface, which leads to the increase the probability of carrier tunneling. 4. Conclusion A gate-all-around junctionless nanowire-based tunneling filed effect transistor with and without uniaxial tensile strain is presented by introducing the two isolated gates (Middle-Gate, Side-Gate) with two different metal workfunctions, to make the layer under the gates intrinsic and p-type, instead of using metallurgical p-n junction. 2-D numerical simulations investigate the performance characteristics of the devices.

Fig. 5. Transconductance (gm) of the JL-TNWFET versus strained JL-TNWFETs with different amount of uniaxial tensile strain. The inset zooms out the corresponding transconductance of highlighted area.

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Fig. 6. Cut-off frequency (ƒT) characteristics of the JL-TNWFET versus strained JL-TNWFETs with different amount of uniaxial tensile strain.

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