RF/Microwave Device Fabrication in Silicon-on-Glass ...

PROC. 26th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2008), NIŠ, SERBIA, 11-14 MAY, 2008

RF/Microwave Device Fabrication in Silicon-on-Glass Technology L.K. Nanver, H. Schellevis, T.L.M. Scholtes, L. La Spina, G. Lorito, F. Sarubbi, V. Gonda, M. Popadiü, K. Buisman, L.C.N. de Vreede, C. Huang, S. Milosavljeviü, and E.J.G. Goudena Abstract - This paper reviews recent developments in circuit and device implementations based on back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT). This technology has been specifically developed for the enhancement of silicon RF and microwave device and circuit performance. While metal transmission lines can be placed on the low-loss glass substrate, the resistive and capacitive parasitics of the silicon devices can also be minimized by a direct contacting of the parts of the devices that are usually connected via the bulk Si. Focus is placed here on the device level aspects of the SOG process, in particular high-quality varactors for high-linearity adaptive circuits and complementary bipolar device integration are treated in relationship to new developments in back-wafer contacting and the integration of AlN heatspreaders.

I. INTRODUCTION This last year the value of applying substrate transfer technology to enhance the performance of silicon-based RF/microwave integrated circuits has been demonstrated by a number of record-breaking varactor-diode circuits for RF adaptivity [1]-[5]. These were fabricated in our transfer to glass process called back-wafer-contacted silicon-onglass (SOG) technology [6]-[7]. As a special feature of this technology, the active silicon device regions are isolated in islands glued to the glass replacement substrate. Both the patterning and alignment of the original top and bottom side of the devices (processed respectively on the front side of the Si wafer, the “front-wafer”, and the backside of the wafer after gluing and silicon removal, the “back-wafer”) are performed with the same high-precision lithography [8]. Moreover, low-ohmic contacts to the back-wafer are created by using laser annealing to activate implanted dopants [9]. Several types of device integration processes have been developed in the SOG technology. The one that has reached the highest level of maturity is the varactor circuit process, where the diode itself is stripped of nearly L.K. Nanver, H. Schellevis, T.L.M. Scholtes, L. La Spina, G. Lorito, F. Sarubbi, V. Gonda, M. Popadiü, K. Buisman, L.C.N. de Vreede, C. Huang, S. Milosavljeviü, and E.J.G. Goudena are with the Department of Microelectronics, Faculty of EEMCS, DIMES, Delft University of Technology, Feldmannweg 17, 2628 CT Delft, The Netherlands, E-mail: [email protected]

all resistive/capacitive parasitics and low circuit losses are guaranteed by the positioning on the glass substrate. Highlinearity was achieved by a combination of (i) special diode doping profiles that could be maintained due to the low thermal budget of the overall SOG processing, and (ii) new innovative circuit designs that make use of the novel doping profiles. In a bulk realization, low RC parasitics can only be achieved by using finger-like structures that have the drawback of seriously complicating the control of the doping profile that determines the varactor’s C-V characteristic. With back-wafer contacting, on the other hand, the metal contact can be placed directly next to the capacitor and in this manner, the ideal intrinsic 1-D device performance is approached. Thus, circuit concepts can be realized that are much simpler and more potent than otherwise feasible. In general, in the SOG process just the fact that the active and, particularly, the (large) passive components are placed on a low-loss glass substrate will enhance the circuit performance. Moreover, considerable benefits on the device architecture level are feasible through the lowohmic back-wafer contacting. A third noteworthy advantage is the fact that any simplification of the device architecture will also simplify the task of combining different device in one process. This is demonstrated in our SOG complementary bipolar process, in which Schottky collector contacting has also been realized for the first time [10]. In contrast to the varactor circuit research, bringing the SOG bipolar process to a level of maturity that allows circuit realizations was hampered by the near-ideal electrical isolation of the devices. All the materials originally used for this purpose (silicon oxides/nitrides, adhesive) are also very good thermal insulators. Record high thermal resistance values were realized for the bipolar transistors, making them ideal electrothermal research objects but totally unsuitable for reliable circuit design. This has led to an investment in the development of deposited AlN layers as thin-film heatspreaders. They have with success been integrated on a device level and are shown to bring the thermal resistance of the individual devices and the electrothermal behavior of small circuits into a domain that is suitable for reliable circuit manufacturing [11].

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Al/Si boron deposition varactor profile

buried oxide silicon substrate

glass substrate adhesive

Al/Si

laser annealed As+ implant glass substrate

copper-plated aluminum

Fig. 1. Schematic of process flow for the integration of SOG varactor diodes and high-ohmic resistors.

1E+17 w/o shallow implant simulation

-3

The basic varactor process flow, shown schematically in Fig. 1, is representative of the back-wafercontacted SOG device processing. Our starting material is 100 mm SOI SOITEC wafers on which any extra layers needed for the specific device fabrication are grown epitaxially. The varactor profiles are tailor-made to the application by arsenic doping-profile engineering during the epitaxy. The total n-epi thickness depends on the breakdown voltage that is required. For example, for a 30 V breakdown voltage about a 1-Pm-thick epi-layer is needed. Diode and resistor Si islands are then defined by plasma etching shallow-trench steps to the buried oxide (BOX). The varactor diode p+ terminal contact windows are processed and contacted by Al/Si(1%) metal tracks. The wafer is covered with 1 µm PECVD oxide to enable the gluing of the wafer to a glass wafer. To preserve the integrity of the adhesive, all subsequent thermal processing temperatures must not exceed 300 qC. After gluing, the Si substrate is removed by etching selectively to the BOX. An Al/Si layer is sputtered on the back-wafer to serve as a reflective mask for laser annealing and the back-wafer contact windows are then etched through the Al/Si and BOX. The contacts are implanted with 5 keV As+ and excimer laser annealed for dopant activation. In this manner it is possible to create low-ohmic contacts and near-ideal diodes essentially at “room-temperature” [9]. This is because the laser pulse only melts the top few nm of the Si surface while the heat pulse that thereby is sent into the bulk is so short, in the µs range at most, that the underlying layers are unaffected. This step provides the low-ohmic contact to the back of the diodes as well as contacts to the resistors. Next, the contact windows to the front-wafer metal are etched and Al/Si(1%) is sputtered and patterned on the back-wafer. Electroplating of 4-ȝm-thick copper on the Al/Si is then performed to achieve low metal resistance. The varactor diodes are used in the reverse mode of operation and the tuning range is determined by the capacitance at zero volt and at the reverse-voltage where leakage/breakdown-associated currents become so large that they supersede the ideal behavior. Ideally the n-doping profile sets the breakdown voltage but any defects in the depletion region will increase the reverse leakage and lower the effective breakdown voltage. In general the diode perimeter will be the main source of leakage current and, in this respect, the large single-contact SOG varactors have a large advantage over their bulk finger-structure counterparts. However, the breakdown voltage of the SOG varactors is consistently lower than similar varactors processed on bulk silicon. One issue in this connection has been identified: during the back-wafer contact implantation, interstitials are injected and have been detected up to 0.6 ȝm away from the contact itself. The effect of this residual damage on the lowering of the breakdown voltage can be correlated to the implantation

dose and tilt. When injected into boron doped p-type silicon, the interstitials cause a significant level of dopant deactivation that is readily detected by CV-profiling, an example of which is shown in Fig. 2. An acceptable situation was created by using high-tilt 60° implants to direct the injected interstitials more away from the diode depletion region. The results of on-going research also indicate that, by optimizing the laser-anneal conditions, some measure of interstitial annealing can be effectuated as a consequence of the laser heating [12].

log10 active boron concentration (cm )

II. HIGH-PERFORMANCE VARACTOR DIODES

o 15 As+ 5 keV 30 2x10 implant + 900 ELA 30o 3x1015

7o 3x1015

1E+16 0

100

200

300

400

500

depth (nm)

Fig. 2. Active boron concentration profiles obtained from C-V

measurements (solid curves) as a function of implantation conditions with respect to the original profile (dashed curve). The boron deactivation increases with dose and decreases with increasing implant tilt [12].


A. Varactor circuits Record high Q values and excellent linearity have been achieved with SOG varactor circuits, examples of which include adaptive matching networks [1] for adaptive power amplifiers [2], phaseshifters [3] and filters [4]. The realized matching networks have third-order interception points (IP3) of over +42 dBm and can tune from 0.2 to 82 ȍ. Using these matching networks an adaptive amplifier has been realized, which provides 13 dB gain, 27-28 dBm output power at the 900, 1800, 1900 and 2100 MHz bands, while also providing optimal loading for improved efficiency at backoff power levels. The phaseshifter operates at 1 GHz and has a 150 degrees controllable phaseshift per dB loss performance, while at the same time the measured IP3 is better then +45 dBm. A tunable bandpass filter, which can tune from 2.4 to 3.5 GHz with a passband loss of 2-3 dB, a stopband rejection of 25 dB and with an IP3 of +46 dBm has been demonstrated. The linearity and power handling of all these circuits can be further improved by stacking multiple varactors in series at the expense of increased area usage [5], doing so IP3s as high as +60 dBm have been demonstrated. Microphotographs of circuit realizations are shown in Figs. 3 and 4.

Fig. 3. Microphotograph of two SOG highly-linear varactor stacks in series to improve linearity, power handling and effective tuning range.

Fig. 4. Microphotograph of the copper-plated highly linear differential phaseshifter realized in SOG technology.

III. COMPLEMENTARY BIPOLAR TRANSISTOR INTEGRATION At present there is an increasing interest in complementary high-frequency SiGe heterojunctionbipolar-transistor (HBT) BiCMOS processes and a few bulk integration schemes have recently been presented [13]-[14]. As always in complementary bipolar processes, the speed of the PNP device is limited by the collector contacting via the bulk. One of the very strong points of SOG technology is that the integration of such different device types in one process becomes much more straightforward: the contacting of device regions via the bulk, which often entails high-temperature processing, can be replaced with back-wafer contacts, and the whole process of isolating the device with respect to the bulk with junction or trench isolation becomes redundant. These benefits are demonstrated in our low-complexity SOG complementary bipolar process. In this process the collector is contacted directly under the emitter, thus eliminating the need for buried layers that in bulk processes are practically impossible to realize in a truly complementary form. The back-wafer contacting offers new possibilities for the collector design. Instead of the conventional contacting of a lightly-doped collector via a highly-doped region, Schottky collector contacting can be implemented [10]. This is illustrated in Fig. 5 for the case of Schottky contacting of p-type bipolar transistors. In one case the lightly-doped p-type collector is retained and contacted by an Al to p-Si Schottky diode. In the other case the Al metallization is placed directly on the n-type base. The characteristics of these Schottky collector devices were almost identical to the ohmic collector contact devices except for the offset voltage, which becomes very high (even 0.3 – 0.5 V) for Schottky contacting directly to the base as shown in Fig. 6. This is determined by the reverse base current which becomes very high due to the low Schottky barrier height of the contact. For HF analog applications the high offset-voltage is not an issue. In fact, such a device can have a speed advantage due to the low collector resistance, transit time and storage time [15]. Moreover, the Schottky contact can be placed very close to the high-doped base as the diode breakdown restrictions will permit and this may have a benefit for reducing collector current avalanching. Like the SOG varactors, the bipolar devices with implanted collector contacts also suffer from the effects of the residual implantation damage [16]. Depending on the distance to the implant and the type of implant, we observed enhanced junction leakage, increased impact ionization current (illustrated in Fig. 7) and reduced breakdown voltages. These effects were not very pronounced in our devices because we have a process with relaxed dimensions but in a down-scaled advanced process, the placing of the implanted collector close to the metallurgic collector-base junction may be destructive.


This concern is completely taken away by replacing the ohmic contacts with Schottky contacts.

IV. ELECTROTHERMAL ISSUES AND SOLUTIONS The isolation of the basic SOG device is almost perfect both electrically and thermally. While the former is ideal for HF purposes, the latter will in many cases lead to unacceptable electrothermal device and circuit behavior. For many SOG devices, heatspreading and heatsinking structures become indispensable at even very low power dissipation levels [17]-[18]. Nevertheless, in our varactor circuits extra heatspreading has not been necessary up until now. However, if it should become an issue in processes such as this with large-area back-wafer metal contacts, heatsinking could be easily implemented: the thick copperplating used to reduce the metal resistance on the backwafer also functions as a very effective heatspreader due to the high thermal conductivity (~ 400 W/mK). Such large

Cu areas can also be directly surface mounted to a printedcircuit board (PCB), which means that the thermal ground is brought as close as possible to the heat generating device region. Adding Cu metallization schemes to the back-wafer is readily doable. For example, an elaborate Cu metallization scheme has been demonstrated in our SOG VDMOS transistors [19]. A schematic of this type of device is shown in Fig. 8. In the front-wafer processing, the source, gate and the drain epi-profile of the VDMOSFET are realized. In particular, p-sinkers are formed to be able to bring all terminals to the back-wafer. The gate p-sinkers are isolated by trench etching from the back- to the frontwafer oxide. The trenches are then filled with benzocyclobutene (BCB) and etched back to the Al/Si. A two-level thick copper interconnect is then electroplated on the back-wafer. This copper is covered with BCB before the devices are soldered to a printed-circuit board (PCB). The first 4ȝm-thick copper layer on the drain minimizes debiasing

Fig. 5. Schematic of different of SOG p-type BJT collector contacts: (a) implanted/laser-annealed ohmic, (b) p-Schottky and (c) n-Schottky collector contacts.

Fig. 6. Measured output characteristics around the offset voltage (at IC = 0) for several p-type BJTs with different collector designs. The high offset devices (d, e, f) have a Schottky contact placed either directly on the base or very close to the base. IB = 2, 4, 6, 8 and 10 µA, emitter area 40×1 µm2 [10].

Fig. 7. Above: Gummel plots of an SOG NPN with implanted collector contact showing two of SOG issues: (1) catastrophic thermal runaway at high currents and (2) enhanced impactionization current due to unannealed residual implantation damage. Below: impact-ionization current versus base-collector reverse voltage at VBE = 0.66 V for NPNs with different collector contacting and an emitter area of 40×1 µm2; the devices have the same forward current gain.


over long drain fingers, and the second 10-µm-thick layer to the source improves thermal conductance to the thermal ground. Due to the very close proximity of the PCB to the active device regions, the thermal resistance of the transistor can be brought down to values even lower than that of bulk counterparts. For large devices such as the varactors and the VDMOSFETs, it is possible to add the thick copper-plated layers directly on the contacts without paying a capacitive penalty. For small dimension devices such as HF bipolar transistors, it would be electrically counterproductive to achieve cooling by placing regions of copper, which have large lateral dimensions, directly on the collector contacts. Preferably, heat transport away from the active device area must be accomplished by a thermally conductive dielectric. For this purpose, we have developed physical-vapor deposition (PVD) of AlN, thin layers of which have been integrated as heatspreaders directly on the heat-generating devices [11]. The application of these layers will be described in detail in the following sub-section. A. Heatspreading with AlN thin-films When considering the integration of dielectric heatspreaders, AlN is an obvious choice. It has a large energy bandgap that makes it suitable as an insulator in many situations and a high bulk thermal conductivity of about 270 Wm-1K-1 [20]. Moreover, it is compatible with standard silicon technology: it is neither contaminating nor poisonous, and can be both deposited and etched by

Fig. 8. SOG VDMOS device structure before and after substrate transfer and back-wafer processing showing the 2-level copper processing.

conventional silicon processing techniques. The integration of thick heatspreading layers in the front-wafer processing is attractive because they can be deposited just before the gluing procedure and do not require any patterning. Thus, they can in principle be chosen as thick as possible. A limitation on the layer thickness is, however, imposed by the stress since the flatness and integrity of the back-wafer surface after gluing and bulk silicon removal is very sensitive to any stress in the remaining layers. A PVD deposition technique was therefore developed to obtain almost stress-free micrometer thick layers composed of a stack of 0.2-µm-thin layers of alternatingly tensile or compressive stress. With this technique AlN layers of up to 4 ȝm in thickness were successfully integrated in the bipolar SOG process. On the back-wafer it is possible to deposit even thicker layers but due to mainly unfavorable etch selectivities, the processing of windows through the AlN to the bondpads entails a trade-off between layer thickness and process complexity. The electrical properties of the AlN layers were found to be in order both from a DC and RF point of view. The resistivity is of the order of 1013 ȍcm and the dielectric constant falls in the range of 9-11.5. The behavior of AlN at microwave frequencies has been studied by fabricating Al coplanar waveguides on surface-passivated high-resistivity Si wafers. In Fig. 9 the measured losses up to 30 GHz are shown for different configurations of AlN and/or SiO2. The results show that the presence of AlN does not introduce additional losses at high frequency, but, on the contrary, depositing AlN reduces the losses. In addition to the conductive properties of the AlN, also the piezoelectric behavior has been examined; crystal morphologies of AlN are known to have strong piezoelectric properties, the presence of which would be undesirable in an RF circuit environment. For a wide range of layer thicknesses the piezoelectric response was found to be negligible.

Fig. 9. Measured microwave losses for 5 different CPWs: (a) CPW on 330 nm SiO2; (b) CPW on 200 nm AlN deposited directly on the silicon substrate; (c) CPW on 200 nm AlN deposited on 30 nm SiO2; (d) 2 ȝm AlN, (e) 4 ȝm AlN, and (f) 6 ȝm AlN deposited on a CPW as in (a) [11].


The efficiency of the AlN as heatspreader can be seen from the experiment illustrated in Fig. 10 where relatively thin 0.8 ȝm layers are applied to an NPN and also copper-plated blocks are added at different distances from the active device area. In Table I the thermal resistance RTH of the NPN is given as a function of the AlN position and of the distance L between two Cu blocks. Each layer of AlN contributes to a strong reduction of RTH, and for L=34 ȝm (that is when each Cu part is placed 17 ȝm far from the center of the active device region) still a significant measure of heatsinking by the Cu blocks is achieved. The measurements of devices with thermal resistances that fall in a wide range have been used as a basis to establish reliable thermal [21] and electrothermal [22]-[23] simulation tools. An important parameter is the thermal conductivity of the AlN, the thin-film values of which are very different from the bulk values. A dedicated structure was developed to measure the lateral thermal conductivity and a value of about 11 W/mK was determined [24]. This value is much too low to be able to describe the overall heat transport in the device layers. This can be understood by considering the structure of the AlN layers, which is columnar with long grains oriented in the vertical direction, as can be seen in Fig. 11. Thus, it is plausible that the vertical thermal conductivity is much higher than the lateral value. In the devices themselves, the non-planar surface topology of the device and the AlN covering will also play a role. Nevertheless, the simulation results showed that a quiet consistent agreement with the experimental results could be achieved by assuming an isotropic thermal conductivity of 50 W/mK. Both experimentally and in the simulations, the reduction of RTH is found to be very significant; a reduction of more than 70% in the value of thermal resistance is obtained using a 4-ȝm-thick AlN layer on the front-wafer. As already mentioned before, a further reduction can be achieved by sandwiching the device between AlN layers on both the front- and back-wafer and by adding Cu blocks that in the packaging could be connected to large heatsinks. Results obtained by simulations of different devices are shown in Table II. A total of 90% reduction of RTH, respect to the case (a), is found in situation (e) of Table II. This translates into a great improvement of the safe-operatingarea of the NPNs as illustrated in Fig. 12. An important function of heatspreaders is to keep critical devices in a circuit at the same temperature. When several bipolar transistors are operated in parallel, the circuit can suffer from electrothermal instabilities that lead to current hogging by one transistor while the others switch off. A typical situation is shown in Fig. 13 where the circuit without extra cooling is already instable at very low current levels. For a device with a 4-ȝm-thick layer of AlN added, the operating temperatures of the three devices become much closer. The transistor #3 again bears the highest current, but, in the whole range examined in Fig. 13, all the three devices still conduct a significant part of the total

current. This will result in an increase of the reliability of the overall circuit. TABLE I THERMAL RESISTANCE OF NPNS WITH DIFFERENT COMBINATIONS OF ALN AND CU HEATSPREADERS AS APPLIED IN FIG. 10. Device 1 2 3 4 5 6 7

AlN on front-wafer [Pm] 0 0.8 0.8 0.8 0.8 0.8 0.8

AlN on back-wafer [Pm] 0 0 0.8 0.8 0.8 0.8 0.8

L [Pm]

RTH [K/W]

no Cu no Cu no Cu 0 18 24 34

12600 8800 7550 3600 5600 6500 6530

Fig. 10. Schematic of a 20x1-µm2-emitter SOG NPN cooled by AlN and Cu. A 0.8-ȝm-thick AlN on both front- and back-wafer reduces the thermal resistance from 12600 K/W to 7550 K/W and additional Cu-plating brings it down to 3600 K/W.

Fig. 11. TEM image of an AlN layer deposited on thermal oxide. The 0.2-µm-thick alternated sub-layers and columar growth are visible.


TABLE II SIMULATED THERMAL RESISTANCES OF SOG BIPOLAR TRANSISTORS WITH DIFFERENT THICKNESSES OF ALUMINUM NITRIDE, WITH AND WITHOUT COPPER-BLOCK DEPOSITION DIRECTLY ON ACTIVE DEVICE AREA. Device

AlN frontwafer [ȝm]

AlN backwafer [ȝm]

Cu [ȝm3]

RTH [K/W]

(a) (b) (c) (d) (e)

0 1 2 6 6

0 1 2 2 4

0 0 0 0 4×50×50

18810 5120 3480 2690 1670

Fig. 12. DC thermal limit of the safe-operating-area of bipolar transistors described in Table II.

V. CONCLUSIONS Efficiently exploiting silicon technology for RF/microwave applications and carrying it into the terahertz age is, to a great extent, a question of reducing the RC parasitics. The presented back-wafer-contacted SOG technology is an effective way of accomplishing this. This has in particular been demonstrated by the fabricated SOG varactor circuits, which also owe their success to the fact that the access to more ideal devices spurred the realization of new circuit design principles. The varactors have a performance that is more than competitive with comparable MEMS varactors without having the reliability and packaging issues that are seriously hampering the introduction of MEMS RF devices in production. Two main issues have been identified in the SOG technology. The first is the very limited thermal budget permitted in the back-wafer processing that has consequences for the fabrication of low-ohmic contacts on the back-wafer. The presently applied solution, implantation plus laser induced activation, is effective but should in future preferably be replaced by methods that do not introduce lattice damage in the vicinity of the contacts. Replacing the implanted contacts with Schottky contacts is shown to be a very viable solution for collector contacting in bipolar transistors. The second main issue is the inherently high thermal resistance of the silicon devices if no special cooling measures are taken. The for this purpose developed thinfilm AlN layers exhibit excellent properties not only with respect to heatspreading but also as far as electrical properties and process compatibility are concerned. They present a means of circumventing the high thermal isolation while still preserving the extremely attractive RF/microwave capabilities. With these device-level heatspreaders, the back-wafer-contacted SOG technology has reached a level of development that makes it attractive for wider use in the semiconductor industry.

ACKNOWLEDGEMENTS The authors would like to thank the staff of DIMES cleanrooms and measurement rooms for their continual support. This work has in part been supported by NXP/Philips Semiconductors Cluster and PACD projects.

REFERENCES

Fig. 13. Measured collector currents of the individual transistors of a set of three operated in parallel as a function of the total collector current for the reference device (solid lines) and a device with a 4-ȝm-thick layer of AlN (dashed lines).

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