RF noise characterization of MOS devices for LNA ... - IEEE Xplore

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 10, OCTOBER 2001

RF Noise Characterization of MOS Devices for LNA Design Using a Physical-Based Quasi-3-D Approach Yi Lin, Michael Obrecht, and Tajinder Manku, Associate Member, IEEE

Abstract—A quasi–3-D method for microwave noise simulation of MOSFET is presented in this paper. This method inherently takes into account all the microscopic noise sources within the transistor at microwave frequencies. It is realized by properly transforming the 2-D noise sources to 3-D equivalent noise sources. The 2-D noise sources and their correlation term are calculated in the framework of a PDE based 2-D device simulator. Based on 3-D , equivalent noise network, the four noise parameters min , , and which are critical for low noise device design are calculated. A 0.5 - m LDD nMOS transistor was simulated and the simulation results were compared to measurement data. The functional behavior of the four noise parameters at microwave frequency with bias and layout parameters is illustrated. An example for designing a low noise MOSFET for RF application is provided. Index Terms—2-D noise, CMOS, CMOS RF, four noise parameters, high frequency noise, quasi-3-D noise model, RF design, transformation matrix.

I. INTRODUCTION

C

MOS TECHNOLOGY is becoming a suitable technology for personnel portable terminals due to the fact that the gate lengths of MOS devices have been scaled down to submicron regime (e.g., [1], [2]). Furthermore, by incorporating its high integration level and low cost, CMOS technology is a good candidate for RF/analog/digital mixed signal applications. A multistandard CMOS RF single chip solution for wireless communication system is expected to be realized in the near future. Although many prototype CMOS RF circuits have been implemented worldwide [3], [4], most of these circuits are designed based on standard CMOS process. Unfortunately, these processes are mainly optimized for digital applications. Therefore, the potential advantages of CMOS RF circuits have not been fully demonstrated. Because of this, the RF performance of CMOS circuits still can not compete with their GaAs or BJT counterparts. The current RF designs are not only limited by the CMOS processes which are not optimized for RF application, but also the design tools and device models which are far from prepared for the new generation RF/analog/digital mixed signal Manuscript received September 30, 1999; revised September 28, 2000. This work was supported by MicroNet and CITO. This paper was recommended by Associate Editor G. Gielen. Y. Lin and M. Obrecht are with the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada N2L 3G1 (e-mail: [email protected]). T. Manku was with the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada N2L 3G1. He is now with Sirific Wireless Corporation, Waterloo, ON, Canada N2L 5J2. Publisher Item Identifier S 1057-7130(01)11052-9.

integrated circuit design. From the literature, it is apparent that the development of new circuits and system architectures for wireless communication is the main-focus of CMOS RF research, but only a little research attention has been put on RF CMOS device modeling. For example, low noise design is one of the key issues in most of the RF circuits, however, due to the poor MOSFET high frequency noise models currently available within most commercial circuit simulators (e.g., HSPICE), “good” low noise design requires several revisions. The difficulty in designing low noise circuits/devices is due to our limited understanding of the noise properties of MOS devices. Even though some experimental research works [5], [6] have illustrated the basic trends between noise parameters and device structures, all the observations are based on a limited subset of device geometries and processes. This paper presents a quasi-3-D simulation approach [7] which can be used to virtually characterize the microwave noise performance of MOSFET. The method can either be used to determine the noise parameters for circuit design, or to provide one with a comprehensive physical understanding of the high frequency noise behavior. In addition, the method can also be used to optimize the device structure/process for better noise performance. In Section II, the important noise sources and models in MOS device at high frequency are briefly introduced. The four noise parameters are also discussed in this section. The details of the quasi-3-D noise simulation procedure is described in Section III. This section begins with describing the 2-D noise simulations, and then follows by describing the 2-D to 3-D transformation. Based on the noise data obtained from the quasi-3-D model, the noise parameters are extracted. In Section IV, the noise simulation results and the measurement data of a short channel LDD MOSFET structure are presented. II. OVERVIEW OF HIGH FREQUENCY NOISE IN MOSFET A. Noise Sources Historically speaking, MOS devices have been used for low frequency application due to the limited carrier mobility of Si. Consequently, the most important noise source was channel thermal noise and flicker noise. At high frequencies, channel thermal noise is still the key noise source. Besides this noise source, some other noise sources, such as induced gate noise and parasitic resistance thermal noise become important. Normally, the high frequency noise sources are classified as intrinsic and extrinsic noise. The noise originated within the active region of a MOS device channel is defined as intrinsic noise. It includes the channel noise and induced gate noise as shown in Fig. 1. Channel noise

1057–7130/01$10.00 © 2001 IEEE

LIN et al.: RF NOISE CHARACTERIZATION OF MOS DEVICES

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where represents the voltage noise source of gate resistance, is the effective noise resistance of the gate. Because of and is given by the distributed effect of gate resistance, (5)

Fig. 1. 3-D MOS device structure with high frequency noise sources.

is one kind of thermal noise which is associated with carriers within the channel. According to Nyquist theorem and the gradual channel approximation, the short circuit thermal noise current at drain terminal is given by (1) where is the Boltzmann constant, is the absolute temperis the channel conductance at zero drain source ature, and voltage. For long channel devices, is approximately a constant in saturation region. But for short channel devices, is a very complex function which depends on biasing conditions. Induced gate noise is another type of intrinsic noise. At moderate higher frequencies, the random motion of the free carriers in the channel generates not only an output drain current noise, but also an input gate current noise due to the capacitive coupling effect via the gate-channel capacitance. The gate current noise is approximately given by [14] (2) is the gate-source capacitance of the MOSFET, and where is also dependent on basic transistor parameters and bias conditions. Since induced gate noise also originates from the random motion of the carriers in the channel, the two noise currents and are correlated and the correlation can be described by (3)

is correlation factor. For long channel MOS devices [12]. Aside from the intrinsic noise sources, various parasitic elements will contribute to the overall noise measured at the terminals of the devices at high frequencies. These types of noise source elements are classified as extrinsic noise sources. The gate resistor thermal noise is one kind of extrinsic noise. The MOSFET poly gate resistivity is usually very large. Even though a silicide process is normally adopted to form the gate, the gate resistance becomes more significant when the gate length is further reduced. The resistive gate contributes to thermal noise at the gate node. The mean-square noise voltage of the gate resistance is described by

where

(4)

is the total gate resistance, is gate sheet resiswhere is the width of the gate, and is the gate length. tance, Equation (5) is only valid when the gate is connected at one end. The source parasitic resistor also contributes to thermal noise. This noise is modeled by the following equation: (6) represents the voltage noise of source parasitic resiswhere tance . The noise generated by the source resistance is also important. However, it is a strong function of the materials used to form the source as well as processing. If not designed properly, its contribution to the noise figure of the whole device can be as significant as the noise added by the gate resistance. It is known that distributed substrate resistance is another noise source [13]. An accurate calculation of this noise source is complex. However, a qualitative representation can be simply expressed as (7) where is a constant, is the space size between gate and bulk is the gate width, and is the bulk transconduccontact, . If the tance which depends on the bulk to source voltage device uses a finger like structure, (7) is still valid. Note that the noise due to the substrate resistances can be mitigated by bias. According to [10], the substrate properly choosing a noise source will probably play a significant role when the gate resistance is reduced to a small value by multifinger structure. However, the main focus of this paper is related to single finger device simulation and characterization. The simulation data is also used to optimized the unit finger width and the number of fingers of low noise MOS device. For single finger device, we can assume that the noise contributed from substrate is less significant. To fully characterize the high frequency noise performance of a device, four noise parameters are required. A definition of each of these parameters is provided below: —minimum noise figure the device can achieve. 1) —equivalent noise resistance. 2) —optimum source resistance to achieve the min3) imum noise figure. —optimum source reactance to achieve the min4) imum noise figure. The four noise parameters can be obtained from a simple lumped circuit model. A noise equivalent circuit is shown in , , are the intrinsic and extrinsic Fig. 2, where , , noise source, and , are correlated. In this lumped element model, the gate-drain capacitance has been neglected. The and is proporchannel charging resistance is denoted by , where is transconductance. tional to

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[18]. As a result, the noise coefficients and in (1) and (2) have been analytically derived. In saturation region, these two parameters are equal to 2/3 and 4/15, respectively. For short channel devices, several analytical models have been recently proposed [19], [21]. In [19], channel noise was modeled by taking into account velocity saturation. In [21], a two region modeling scheme was used to calculate the channel thermal noise in short channel devices. However, compared with the long channel MOSFET analytical models, short channel noise models are still not accurate enough to predict the noise parameters of submicron MOS devices. The main reason for this is because there is a fundamental theoretical problem that manifests itself when one moves from a long channel device to a short channel device. The analytical model discussed so far are based on integrating the thermal noise sources arising from each differential portion of the channel. That means each differential portion can be considered as a thermal noise source, and its noise voltage spectral density is given by Nyquist’s formula

(a)

(b) Fig. 2. MOSFET noise equivalent circuit.

(12) All the noise sources in Fig. 2 can be transformed into two correlated input noise sources and of a noise free network is [see Fig. 2(b)]. To a first order, if the contribution from ignored, the noise parameters can be obtained from the noise equivalent circuit shown in Fig. 2 [16]

is the field dependent noise temperature, and where is the differential channel resistance at a point x along the channel. The total spectral density of the open circuit thermal noise voltage at the drain is expressed as the sum of all the differential noise source spectral densities; i.e. (13)

(8) (9) where

and

(10) (11) Note that the noise coefficient , , correlation factor , and and will have impacts on device parasitic resistance noise parameters. The parameters , , and for a long channel MOSFET have been well characterized using simple analytical methods [12], while for short channel devices, analytical calculation of these coefficients are relatively complex if not impossible to obtain. B. Accurate Modeling of Intrinsic Noise in Short Channel Device The high frequency intrinsic noise model for a long channel MOS device is based on the gradual channel approximation. The amount of channel noise measured at the drain is obtained by integrating the inversion layer charges [24], whereas the amount of induced gate noise is calculated using a active line method

This method which was originally introduced by van der Ziel [22] uses the assumption that there exists no correlation between the noise voltages of each differential slice, which means for . For long channel devices this method can give the correct result. However, for short channel devices this assumption is questionable [23]. Since the gradual channel approximation is no longer valid for short channel devices, it will also affect the validity of the active line method used in [18]. The Impedance Field Method (IFM) is a more general method to determine the amount of noise in a device [25]. Unfortunately, only for some special cases can analytical formulas for noise be obtained using the IFM. However, the real advantage of IFM is its flexibility for numerical implementation. It has been used successfully for simulating the noise in MESFET and bipolar device [33], [34]. Only recently, this method has been used to simulate the noise behavior in submicron MOS devices [7], [8]. Numerical noise modeling is formulated as a linear perturbed problem in which microscopic noise sources are introduced into the semiconductor transport equations. For simplicity and the numerical efficiency, the drift diffusion transport model is more commonly used within 2-D device simulators. The linear perturbed problem can be solved by the Langevin method or its equivalent Impedance Field Method [23]. The Impedance Field Method implies that a stimuli current (or voltage) is applied within the device and a corresponding voltage (or current) is recorded. Generally speaking, the term that relates the stimuli to response can be treated as a Green’s function. Therefore, the impedance is just a special form of a Green’s function.


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Having obtained the scalar and vector Green’s function, the noise spectral density at the device’s terminal (gate or drain) can be determined by using (14) is the local diffusion noise, and is equal to . is the diffusivity tensor, and denote is the electron density at the DC the device terminals, [or ] is the scalar Green’s operating point, function corresponding to the (or ) terminal, and is the frequency. The detail definition of vector and scalar Green’s function can be found in [33], [34].

where

Fig. 3.

3-D distributed noise equivalent network.

Fig. 4.

2-D noise current injection and responses.

C. 3-D Distributed Noise Model Due to the distributed gate effect in MOSFET’s, the accurate noise equivalent representation of the device is 3-D by nature. A proper way to construct a 3-D equivalent noise network is to slice and connect the whole device along the gate width direction using a series of small gate resistors. This scenario is clearly shown in Fig. 3. Based on this 3-D distributed noise equivalent network, a quasi-3-D noise simulation can be achieved in two steps; i) a 2-D noise simulation is carried out to calculate the ; ii) a current noise sources , and the correlation terms circuit level simulation is conducted using a four port network in which the 2-D noise information can be efficiently transformed to 3-D. Then, the high frequency noise parameters of the whole device can be obtained. III. QUASI 3-D NOISE SIMULATION METHOD A. 2-D Noise Simulation Fig. 4 shows the 2-D cross section of the MOS device. To calculate the noise spectrum given in (14), the scalar and vector Green’s functions need to be evaluated. To construct the Green’s functions associated with the gate and drain, an impulsive current source is injected into a grid point, and the drift-diffusion transport equations are solved. These equations are described as (15) (16) (17) (18) (19) is the potential, and are the corresponding carwhere and are the corrier concentrations within the device, responding impurity concentration, and are carrier recomis stimuli current bination and generation rates respectively, and are electron density injected at the grid point, and (or ) and (or and hole current density respectively. ) are electron (or hole) mobility and diffusivity. is bandgap

narrowing factor. The stimuli current is a spatial delta function and contains a number of harmonics in the frequency domain. The amplitude of the stimuli current source is kept small enough so that the terminal response is linear. After numerically solving the equations, the response currents at the terminals are recorded. Following this, an FFT is carried out so that the frequency domain stimuli current and response current are obtained. Finally, the Green’s functions are calculated. Before the 2-D drift diffusion based numerical noise calculation is implemented, some assumptions have to be made. First, the hot electron effect is assumed to be small. The evidence presented in [11] supports this assumption. Second, the stimuli was only used within electron continuity equation; i.e., we neglected the noise due to the holes. This assumption was verified by calculating the hole noise contribution for a typical case. The simulation results showed that the hole contribution is only 7 percent of the electron contribution. The mobility model used for solving drift-diffusion equations has taken velocity saturation into account. Since we are only considering the high frenoise and the generation/recombinaquency noise sources, tion noise of the device is not discussed in this paper. The 2-D noise simulation procedure has been implemented into the framework of 2-D device simulator MicroTec [26]. A decoupled transient scheme was used for the numerical implementation [29]. It is a modified Gummel-like scheme with an improved convergence rate. As an example, a 0.5- m LDD MOS device was simulated. Fig. 5 is a plot of the local noise density. Local noise density describes the amount of noise generated at a particular point in the channel seen by a specific terminal, such as drain or gate. From this plot, we find the maximum drain and gate local noise occurs near the source. That means the drain or gate current noise spectrum are mostly contributed by the channel noise at the source side.

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Fig. 6. Representation of 3-D noise network by two equivalent noise sources at the input.

(a)

Fig. 7. 3-D noise network reconstruction using cascade four port networks.

(b) Fig. 5.

3:0 V, V

Device local noise density. LDD NMOS, = 1:3 V, f = 2:5 GHz.

L

= 0:45 m, V

=

B. 2-D to 3-D Transformation 2-D noise simulation is used to calculate the noise source of each 2-D slice in the 3-D equivalent noise network. For further calculation of the noise parameters of the whole device, all the noise sources in the network have to be transformed to the input or output terminal. In Fig. 6, two equivalent noise sources are used at the input to represent the whole 3-D noisy network. The number of slices used to construct the 3-D network is an important factor that affects the accuracy of this quasi-3-D distributed model. The minimum number of slices required for obtaining sufficiently accurate results usually depends on gate sheet resistivity and device operating frequency. Using a large number of slices will increase the complexity of the transformation of the distributed noise sources to the terminals. Furthermore, the correlation between the 2-D noise sources will make the transformation more complex. Therefore, a systematical mapping scheme is required. The 3-D noise network is a multiple two port network; see Fig. 3. However, the periodical property of this structure gives us an opportunity to reconstruct the network for mathematical simplification [30]. The network in Fig. 3 can be reconstructed as a cascade four port network as shown in Fig. 7. Because of its periodical property, the network is constructed by a series of identical four port elements. The individual four port network is shown in Fig. 8. Each element incorporates the 2-D MOS device slice which is located between the gate and the drain line and is described by a shaped equivalent circuit. The noise sources in the elementary 2-D slice are represented by a noise voltage and a noise current at the input terminals of the transistor. The input and output links of the drain and gate line may either

Fig. 8. Equivalent circuit of the k th network.

consist of a short or a lumped resistor element. The advantages of using a four port network are that the voltages and currents of the input and output of whole network may be determined by the transformation matrix of the four port elements. Furthermore, the noise sources can be transformed using the transformation matrix. In Fig. 8, the voltages and currents of the individual ports may be related to the other ports by the following matrix equations

(20)

is transforwhere denotes the th element, , , are the transformation matrixes mation matrix, of the subnetworks which are constructed from the elementary is equal to . Fig. 9 illustrates four port network. Here, the construction of these transformations from subnetworks of the four port elements.


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(a)

(b) Fig. 9. Subnetworks of the unit four port network and their relative transformation matrixes.

By including the noise sources

and , (20) is modified as

(21)

Fig. 10. Cascade four port termination conditions and the equivalent noise representation at the terminals.

individual ports. In (21), the various noise sources arising from the 2-D transistor slice have already been included. Since only information about the noise is required, the terminal signal can be separated from the noise quantities. As a result, the noise behavior of a single four port element can be described by the following relationship:

(25)

where

(22)

(23)

(24)

(, or ) are the parameters of the MOSFET where is the number of 2-D MOS device elements. All element, voltages and currents in (21) contain both the signal and the noise components. The matrix equation (21) includes the transformation of the transistor’s noise voltage and noise current to the input port of the elementary building block in Fig. 8. The only relates to and of the active MOSFET. matrix In order to determine the noise figure, a relationship between the input/output quantities and internal noise sources of each “slice” has to be derived. There are two types of internal sources within the whole network (see Fig. 7). One arises from the noise in the 2-D transistor elements. The second is the thermal noise source arising from the distributed gate resistance. We first consider the noise contribution from the transistor. Equation (21) describes the signal and noise transformation between

After we obtain the noise transformation of the elementary blocks, the whole network and its boundary conditions (or termination status of different ports) are then considered. The network is represented by a black box unit in Fig. 10. In general, two of the four ports are terminated with an arbitrary admittance on the drain side and an arbitrary on the gate side. In is conaddition, a signal source with an internal admittance to nected to the network input terminal, and a load of the output terminal. If all four terminations contain a finite con, ductance, they inject thermal noise which means that , contributes to the noise power at the network’s output and and terminal. However, for the special case shown in Fig. 7, are equal to 0 (see Fig. 10). Thus, only the noise generand each 2-D MOSFET element have a strong inated by fluence on the network noise behavior and may be represented by a current and/or a voltage source at each of the four terminals. By transforming the transistor’s individual noise sources to the four-port terminals as illustrated in Fig. 10, we can thereby make the four-port network noiseless. Applying these boundary conditions to (25), we obtain the following matrix equation:

(26)

where (27)

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(28)

(29) (a)

(b)

(c)

(d)

(30) is the identity matrix. For the case when all the elements are and ), (27) and (29) take the identical (i.e., form (31) (32) To directly relate as

,

,

,

to , ,

, (26) is rewritten

(33)

and are described in Appendix A. where elements In order to calculate the noise figure of the network shown in Fig. 7, the total noise contribution from each elementary transistor is calculated first, and then the noise contribution due to the gate resistance is calculated. The first goal can be achieved by using (33). If the network output is used as a reference plane, the computation of the noise figure will only require the knowledge of the noise output power from the input source resistance and network itself. When only the elementary MOSFET noise is decontributions are considered, and the noise voltage rived from (33), we obtain (34)

Fig. 11. (a) Minimum noise figure versus gate source voltage. (b) Optimum noise resistance versus gate source voltage. (c) Equivalent noise resistance versus gate source voltage. (d) Optimum noise reactance versus gate source voltage. TABLE I 0.5-m LDD MOSFET SIMULATED PARAMETERS AT SPECIFIC BIAS POINTS

where (38) Substituting (37) into (35), yields

depends on , [see (27), (29)], and the terminawhere tion admittances of the network. The noise power at the output is therefore given by

(39)

(35)

Replacing the noise voltages and noise currents of (39) with the MOSFETs’ equivalent noise parameters given in Appendix B leads to

The noise current of the 2-D elements can be expressed in (see Appendix B), i.e., terms of a correlation admittance (36)

(40)

represents that part of the current that is not corwhere related with . By substituting (36) into (34), the output noise voltage of the network can be expressed in terms of parameters that are not correlated with each other

and are equivalent noise resistance and conducwhere tance respectively. In (40), the noise contribution by the termination admittances has been included. To calculate the noise figure of the whole device, the noise due to the distributed gate resistance also has to be included. As mentioned in Section II, the distributed gate resistor noise sources can be represented by a equivalent noise resistance

(37)


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at the input of the network. Using (26), the equivalent noise at the output due to the distributed gate resistance is (41) In terms of noise power (42) As a result, the total noise power at output of the network is the sum of the two noise contributions (40) and (42) Fig. 12. Minimum noise figure versus finger width for a single finger device for different bias points. F = 2:5 GHz, R = 6 , V = 3:0 V. R is gate sheet resistance. Number of slices = 15.

(43) , and the Since the available input noise power is , the noise figure of the overall power gain is “3-D” MOS devices is given by

(44) Fig. 13. Equivalent noise resistance versus finger width for a single finger device for different bias points. F = 2:5 GHz, R = 6 , V = 3:0 V. Number of slices = 15.

Further noise characterization will be based on (44). C. Noise Parameter Extraction

(50)

, , and are usuThe four noise parameter ally considered to be the figure of merit for low noise device design. The relationship between noise figure and these noise parameters is given by

(51)

IV. RESULTS AND APPLICATION (45) Equation (45) can also be expressed in a form that is linear with [35]: respects to four new parameters , , , (46) , the equivThe computation of the minimum noise figure , the optimum resistance , and opalent noise resistor may then be accomplished by computing timum reactance the noise figures in (44) for four arbitrary, but different input and substituting the resulting noise figures into admittances (46). This results in four equations. We can therefore solve for , , , and . As a result, the noise parameters can be calculated using (47) (48) (49)

The quasi-3-D method was used to simulate the noise performance of a 0.5 - m CMOS LDD MOSFET. The process and structure parameters were first entered into the 2-D simulation program and the simulated – curves were calibrated with the measured results from the device. Several bias conditions were used within the 2-D noise simulator. After obtaining , , , and the parameters of unit width device, the noise parameters of the device were characterized for different frequencies, different bias points, finger widths, and gate sheet resistances. To verify the simulation results, comparison with measurement data was carried out. The measurements were conducted using a HP8510 network analyzer and the ATN noise measurement system. A multifinger device was used for measurement, and the single finger device data was extracted from the measurement data. Fig. 11 plots the four noise parameters versus gate source voltage. The simulation results agree well to measurement data. An interesting thing to note is an optimum exists at which the minimum noise figure could be achieved. starts to saturate and starts to inThis is due to fact that is proportional to , an optimum also crease. Since

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Fig. 14. Optimum noise resistance as a function of finger width for a single finger device for different bias points. F = 2:5 GHz, R = 6 , V = 3:0 V. Number of slices = 15.

Fig. 15. The ratio of the input resistance and the optimum noise resistance at different bias points for a single finger device. F = 2:5 GHz, R = 6 , V = 3:0 V. Number of slices = 15.

exists for lowest . At the optimum , the reaches its at this bias point. The oplargest value because of optimum is in the low voltage range which means low noise timum and low voltage could be realized in CMOS technology. For , it first reduces with increasing , then starts to saturate continue to increase. as A. Single Finger MOS Device Noise Behavior , , Table I provides the basic device parameters, such as and for different bias points. These parameters are calculated using 2-D steady-state simulation. The maximum was simulated to be 21.9 GHz, which is close to our measurement result of 21 GHz. To investigate the behavior of the noise parameters with bias, a number of figures have been plotted; Figs. 12–17. In these figures, gate sheet resistance and the drain to source voltage are fixed. Also, the device is operating at 2.5 GHz. Fig. 12 is a plot versus finger width for various . From this figure, we of can see the minimum noise figure increases with finger width. This is attributed to the fact that the gate noise due to the gate resistance increases with finger width. An easy explanation to this phenomenon can be given by looking at the first-order equation [31] for

Fig. 16. Optimum noise reactance as a function of finger width for a single finger device for different bias points. F = 2:5 GHz, R = 6 , V = 3:0 V. Number of slices = 15.

(52) is bias dependent factor, where , , are drain and gate noise coefficient, is correlation factor, is channel conductance at zero drain source voltage, and is an equivalent lumped gate resistance. As can be seen . from (52), the minimum noise figure is proportional to increases, increases as well. Fig. 12 also Therefore, if is a strong function of . To achieve a low shows that , not only should small finger width be used, but also a proper bias point should be selected. In Fig. 13, the equivalent noise resistance is plotted as a funcas a parameter. Note that the value tion of finger width with for a single finger device is very large and it increases of very rapidly as the finger width decreases in small finger width saturates region. When the finger width continue to increase, and increases again at a particular finger width. The reason for is governed by both and this is due to the fact that

Fig. 17. The ratio of the input reactance and the optimum noise reactance at different bias points for a single finger device. F = 2:5 GHz, R = 6 , V = 3:0 V. Number of slices = 15.

. is dominant when finger width is small, while is dominant when finger width is very long. For low noise design, is required. To explain this further, we can a small value of use the well-known noise figure equation (53) is signal source admittance. According to where . Thus, small results in this equation, is proportional to small . Furthermore, if the noise matching is not perfect, that , small will reduce the is to say is not exactly equal to


Fig. 18. Minimum noise figure versus finger width for a single finger device at different frequencies. R = 6 , V = 1:3 V, V = 3:0 V, R is gate sheet resistance. Number of slices = 25.

contribution of this mismatch term to the total noise figure. A is to use a multifinger structure. possible solution to reduce , , , Figs. 14–17 illustrate the behavior of as a function of gate width for various bias and and are real and imaginary parts of the input points. , is also governed (gate-source port) impedance. Like for small finger widths and for larger finger by is related to . widths. The optimum noise reactance decreases as the finger width increases. Ideal Hence, and . However noise matching requires , it may be hard to match the device due to large values of for minimum noise figure using a single finger device; i.e., if the input of single finger device is directly connected to 50 , the noise figure of the whole device would be large because of the noise mismatching. Moreover, to match for both a minimum noise figure and a maximum power gain, the criteria and are required. Figs. 15 and V, 17 tell us that this criteria is perfectly satisfied at V, and while at optimum noise bias point deviate from and . However, the tradeoff between noise matching and power matching still can be achieved if we . An effective way of reducing will be further reduce discussed in the next section. Besides bias, the operating frequency is another factor that of affects the noise parameters. As shown in Fig. 18, the a device at a particular finger width increases dramatically as frequency increases from 2.5 GHz to 7.5 GHz. Also, the slope versus finger width is larger for higher frequency which of implies that the gate resistance effect is more significant as the is plotted as a function frequency increases. In Fig. 19, of finger width using frequency as a parameter. As frequency decreases as . increases, In submicron CMOS RF device, the gate resistance will also is unaffected affect the noise parameters. Fig. 20 shows by the gate resistance for small finger width, but deviates for larger widths; i.e., as the gate sheet resistance increases, increases. Also, its effect on is stronger when a large finger width device is used (see Fig. 21). B. Effect of Multi-Finger Structure For MOS devices, the sheet resistance of a poly gate is usually high, even when a silicide process is adopted. This situation

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Fig. 19. Optimum noise resistance as a function of finger width for a single finger device at different frequencies. R = 6 , V = 1:3 V, V = 3:0 V. Number of slices = 25.

Fig. 20. Minimum noise figure versus finger width for a single finger device for different values of gate sheet resistance. F = 2:5 GHz, V = 1:3 V, V = 3:0 V, R is gate sheet resistance. Number of slices = 25.

Fig. 21. Optimum noise resistance as a function of finger width for a single finger device for different values of gate sheet resistance. F = 2:5 GHz, V = 1:3 V, V = 3:0 V. Number of slices = 25.

is expected to be more severe as the finger length continues to be scaled down. When designing low noise devices, low is our major concern, but at the same time the noise matching impedance should also be chosen properly so that on chip noise matching can be easily realized and is repeatable. Because of this reason, an optimum finger width is usually required. For a single finger device, we can find the optimum finger width . Unfortunately, the optimum noise and bias for lowest matching impedance is still too high to be achieved on chip ’s). Also from a power gain point of (i.e., in the order of view, the device will not have sufficient gain if the finger width only. To overcome these problems, is optimized for low

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Fig. 22. end.


A multifinger structure device layout with the gate connected at one

a multi-finger structure is required. Fig. 22 illustrates a typical finger structure layout. Using network analysis, a simple scaling rule for the noise parameters for this kind of structure can be derived [31]

Fig. 23.

Typical input matching circuit using inductors.

TABLE II SUMMARY OF LOW NOISE RF MOS DEVICE/CIRCUIT CODESIGN

(54) (55) (56) (57) is the number of fingers and subscript indicates the where is indepennumber of fingers. These formulas tell us that , and decrease dent of number of fingers, whereas , . by C. Low Noise Design Consideration for LNA For traditional RF low noise discrete circuit design, the device itself is normally given by device suppliers. Thus, we do not have to be worried about device design when we design the circuit. For example, in LNA design, the best and most suitable low noise device is chosen first, then the proper input matching circuit or feedback circuit is designed to meet the low noise requirements. In this case, the size and factor of circuit elements is not a serious problem. However, when we talk about RF integrated circuit design, the design concept changes. Here, the design of circuit and device should be conducted together. For CMOS RF LNA, low noise device design is particularly important. This is because of the factors of the on chip passive elements (i.e., inductor or capacitor) are usually very low. Therefore, if the transistor is not designed properly, the required noise matching circuits could be very difficult to achieve on chip. That is why some integrated CMOS RF LNA’s suffer from large noise figures [3], [4]. Applying the noise data simulated using the quasi-3-D method, we can determine the optimum bias for low noise operation, as well as the optimum device size so that the device is noise matched to the characteristic impedance of the system; this impedance is typically 50 . As an example, a 0.5 - m LDD MOS device at 2.5 GHz will be designed for a tuned LNA using the simulation data. The gate sheet resistance is

assumed to be equal to 6 . Since the finger length is fixed 0.5 m, only the finger width needs to be decided. As can be seen from Figs. 12, 14, and 16, there is a tradeoff finger , and relative small , can be width for which low achieved. Suppose we want to achieve 2.2 dB noise figure and a dB for a 2.5 GHz tuned LNA. The unit finger width of the device will be chosen to be equal to 15 m. For optimum V, we get dB, k , bias point k . To reduce to 50 , a multifinger structure must be employed. Assuming the gate is connected at the one end, the number of fingers can be obtained by using the scaling and total device rule presented previously. Therefore, width is equal to 750 m. After these steps, the device is designed to match the real part of the optimum noise impedance without degrading the minimum noise figure. to 50 Noise matching and signal power matching at the input stage are two key issues in LNA design. The imaginary part of the optimum noise impedance is not equal to zero and needs to be compensated by circuit elements. In order to illustrate the basic concept of matching the LNA for both noise and power gain, a typical input stage with one device and two inductors are used is added (see Fig. 23). To match the input power, an inductor to the source of the MOS device to match the real part of input . Since the single finger device has impedance to k , a 50 finger device has a input resistance of


983

. Applying the matching criteria for the real part of input impedance, we get

the noise current , and the noise current generated by the source is formulated in (34) impedance . The output noise voltage and its elements are given by (62)

nH

GHz

(63)

(58)

does not effect (assuming is lossless), Note that of the device. For the structure in but it does affect the of the device is modified to (the optimum Fig. 23, the reactance of the device with an inductor at source); i.e.

(64)

(59)

(67)

Since the device we are discussing has 50 fingers and is operis approximately equal to 140 . With ating at 2.5 GHz, nH, we obtain . Because of , the is modified to (the input reacdevice input reactance tance of the device with an inductor at source) (60) . Hence, . From (60), . is still close to one, simultaneous noise Note and signal power matching can be realized by using another inductor at the gate (see Fig. 23). This input inductor cancels out the reactance due to the input reactance of the device. Using a power matching criterion, we obtain From Fig. 17,

(65) (66)

APPENDIX B NOISE PARAMETERS OF ELEMENTARY MOSEFET In the framework of 2-D noise simulator, , and their corare calculated (see Section II). The parelation term rameters of the device can also be calculated within the framework of the 2-D simulator. Applying the theory developed in [15], we obtain (68) (69)

(61)

(70)

, However, from noise matching criterion, i.e., is equal to 8.7 nH. In order to meet the spec, is chosen the to be 10.4 nH. In Table II, a summary of the design is provided.

is the correlation admittance, is the equivalent where is equivalent noise conductance. noise resistance, and

nH

V. CONCLUSION In this paper, we have proposed a quasi-3-D noise simulation method for high frequency noise characterization of MOS devices. The behavior of the four noise parameters with device width, bias, frequency, and gate resistance was depicted. Good agreement was observed between measurement and simulation results. It was shown that 3-D noise effect is important when the gate sheet resistance and operating frequency are high. This effect is expected to be more severe when deep submicron MOS devices are used for RF applications. For easy noise and maximum power gain matching, a multi-finger device is required. Also, the unit finger width and number of finger should be optiis achieved without sacrificing mized so that a reasonable . To illustrate the importance of co-device/circuit design, a typical low noise input stage of a low noise amplifier was designed as an example. APPENDIX A THE ELEMENTS OF [ ] The noise voltages at the four terminals of the quasi-3-D network are expressed by (33) as functions of the noise voltage ,

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Yi Lin received the B.S. degree in electrical engineering from Southeast University, Nanjing, China, in 1988, and the M.A.Sc. degree in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1999, where he currently is working on the Ph.D. degree. In 1988, he joined the Nanjing Electronic Device Research Institute (NEDI), Nanjing, China, where he was a microwave semiconductor device and circuit design engineer. From 1991 to 1995, he was a Microwave/RF IC design engineer in the same Institute working on Si and GaAs MMIC design for satellite communication application. From 1994–1995, he was a Group Leader leading GaAs power amplifier MMIC design and testing in NEDI. From 1996 to 1997, he was a Research Engineer with Microelectronics Center, Nanyang Technological University, Singapore, where he was working on GaAs HBT MMIC project. During the summer of 1999, he was with Mitel Semiconductor Inc., Kanata, ON, Canada, where he designed RF IC building blocks for deep submicron CMOS technology RF performance evaluation. During the fall of 2000, he was with the Semiconductor Product Sector of Motorola Inc., Phoenix, AZ, where he investigated a phase noise reduction technique and its implementation in RF CMOS VCO.

Michael S. Obrecht was born in Kholmsk, Sakhalin, Russia, in January 1953. He received the M.Sc. and Ph.D. degrees from the Novosibirsk State University, Novosibirsk, Russia, in physics and applied mathematics in 1975, and theoretical physics in 1983, respectively. He has worked in the area of semiconductor device numerical modeling since 1982, first at the Institute of Pure and Applied Mechanics, Russian Academy of Sciences, Novosibirsk, and since 1991, at the Electrical and Computer Engineering Department of the University of Waterloo as a Research Associate Professor. Since 1994, he has also been with Siborg Systems Inc., a company that develops TCAD software tools for process engineers and educational use. Currently, he is working on numerical transient and noise simulation of high-frequency semiconductor devices for CMOS and BiCMOS circuits. His research interest is in new efficient algorithms for steady-state and transient, 2-D and 3-D semiconductor device simulation. He has authored and coauthored more than 30 papers and 1 patent. He has developed software tools for semiconductor process-device simulation which are currently used by more than 20 companies and 90 universities.

Tajinder Manku (M’94–A’96) received the B.Sc. degree in particle physics from the University of Manitoba, in 1990, and the M.A.Sc. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1993, respectively. In 1993, he joined Mitel Semiconductors, QC, Canada, as an IC high-speed analog designer. In 1997, he joined the University of Waterloo, Waterloo, Canada, as an Associate Professor. Currently, he is the CTO and founder of SiRiFIC Wireless Corp., Waterloo, ON, Canada. His research areas include RF technology and microelectronics. He has published more than 70 papers and has 17 patents.