Ripple-Port Module-Integrated Inverter for Grid ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 49, NO. 6, NOVEMBER/DECEMBER 2013

Ripple-Port Module-Integrated Inverter for Grid-Connected PV Applications Souhib Harb, Student Member, IEEE, Mehran Mirjafari, and Robert S. Balog, Senior Member, IEEE

Abstract—The single-phase inverter has inherent doublefrequency power ripple, which if not internally mitigated, appears at the input port and deteriorates the maximum power point tracker performance. Conventional dc link inverter topologies filter this significant double-frequency ripple by means of the bus capacitance, usually in the form of electrolytic capacitors, which have well known lifetime challenges. This paper presents a doublefrequency ripple cancellation concept and experimental proof of concept. The proposed module-integrated inverter is based on the commonly used two-stage inverter. However, a third port is added for ripple cancellation purposes. Hence, a very small capacitance is needed, and, as a result, a high-reliability film capacitor can be used instead of the bulky low-reliability electrolytic ones. Index Terms—Double-frequency ripple, grid-connected inverter, microinverter, MIL-HDBK-217, photovoltaic, power decoupling, reliability, single-phase inverter.

I. I NTRODUCTION

P

HOTOVOLTAIC (PV) module-integrated inverter (PV-MII) has become the trend for grid-connected PV applications [1] due to its numerous advantages, including improved energy harvest, improved system efficiency, lower installation costs, Plug-N-Power operation, and enhanced flexibility and modularity [1]–[4]. However, mounting the power electronics directly to the PV module necessitates using highly reliable converters due to the thermal environment [5] and the need for a 25-year lifetime to match the PV module [1], [6], [7]. Inherent in a single-phase MII is double-frequency ripple that is usually filtered using bulky electrolytic capacitors [1]. It is well known that the electrolytic capacitor is the limiting component of the reliability of the MII [8]. Recently, a number of new inverter topologies that use a highly reliable film capacitor for power decoupling purposes have been proposed [9]–[17]. These topologies are cost effective for film capacitors because only tens of microfarads (instead of the 10 000 μF or more for conventional topologies)

Manuscript received September 26, 2012; revised December 10, 2012; accepted January 12, 2013. Date of publication May 17, 2013; date of current version November 18, 2013. Paper 2012-SECSC-502.R1, presented at the 2012 IEEE Energy Conversion Congress and Exposition, Raleigh, NC, USA, September 15–20, and approved for publication in the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS by the Sustainable Energy Conversion Systems Committee of the IEEE Industry Applications Society. The authors are with the Department of Electrical and Computer Engineering, Renewable Energy and Advanced Power Electronics Research Laboratory, Texas A&M University, College Station, TX 77843 USA (e-mail: souhib85@ gmail.com; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2013.2263783

Fig. 1.

RP-MII.

of capacitance are needed. However, the control in most cases can become very complicated and require many sensing signals. The latter increases cost, reduces power density, and can deteriorate reliability. In contrast, the control of the proposed ripple-port topology is very simple and straightforward as will be shown later in this paper. Although the criterion for minimum energy storage is established [18], the design tradeoffs to minimize the value of capacitance have not been fully explored. This paper presents a double-frequency ripple cancellation technique, based on a ripple-port concept [18], and experimental validation. The proposed topology, suitable for use as a MII, is based on the commonly used two-stage inverter with a third port is added, at the dc link, for ripple cancellation purposes. Hence, a very small capacitance is needed, and, as a result, a high-reliability film capacitor can be used instead of the bulky low-reliability electrolytic ones [8], [19], [20]. II. RP-MII Fig. 1 shows the block diagram of the ripple-port MII (RP-MII) in which double-frequency ripple cancellation is accomplished by adding a “ripple port” on the dc link of the multistage inverter. The proposed RP-MII significantly reduces the minimum required power decoupling capacitance, i.e., CD . Another advantage is that this ripple-port concept can be used with any isolated dc/dc converter topology capable of boosting the input voltage and providing galvanic isolation for gridconnected applications. III. RP-MII I MPLEMENTATION The input dc/dc stage can be implemented using any dc/dc converter topology that is capable of boosting the voltage from the PV module and providing the needed galvanic isolation

0093-9994 © 2013 IEEE

HARB et al.: RIPPLE-PORT MODULE-INTEGRATED INVERTER FOR GRID-CONNECTED PV APPLICATIONS

Fig. 2.

RP-MII, integrated design.

for safety purposes. To demonstrate the concept, the popular flyback converter is used in this paper [1], [9], [10], [13], [16]. The proposed MII can be implemented in two ways, namely, integrated and auxiliary ripple-port winding. Both implementations are explored in this paper along with the simulation results, and the integrated RP-MII is experimentally verified. Although the separated ripple-port winding can be implemented in a way that further reduces the required decoupling capacitance, its impact on the reliability, as compared with the integrated option, is very small. The detailed analysis was presented in Section V. A. Integrated Ripple Port (Single Flyback Output) Fig. 2 shows the implementation of the proposed RP-MII with single-output flyback converter. The ripple port is integrated with the output port on the secondary winding of the flyback coupled inductor. Hence, the peak voltage of the decoupling capacitor is limited by the dc link. For a 235-W inverter with a 200-Vdc dc link and depth of modulation (DoM) of 0.95 for the ripple-port dc/ac inverter, 36 μF is needed. However, due to imperfect coupling between the transformer’s winding, a slightly larger decoupling capacitance is needed in practice. B. Separated Ripple Port (Multiple Flyback Outputs) Fig. 3 illustrates the integration of the ripple port into the flyback converter through a separated transformer winding. In this case, the decoupling capacitor peak voltage is not limited by the dc link. Consequently, the capacitance can be minimized by using a higher voltage. For the same 235-W RP-MII, but with a turns ration to provide 550 Vdc at the input to the ripple port, only 4.6 μF is needed (5 μF is used in the simulation). This extra degree of design freedom carries with it the tradeoffs of requiring extra components and the efficiency implications of power losses and transformer leakage energy.

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Fig. 3. RP-MII, auxiliary winding.

is needed to prevent sudden changes in the capacitor’s voltage because of the switching effect. Assuming a unity power factor at the output (grid) side, the output power has both an average value and a component pulsating at twice the mains frequency as follows: p0 (t) = V0 I0 sin2 (ωo t) p0 (t) = PPV + PPV cos(2ωo t).

(1)

The role of the ripple port is to process the power at the dc link, which implies that the effect of the output low-pass filter (Lf −Cf filter) should be taken in consideration in order to achieve an accurate ripple cancellation at the input side. This can be accomplished by considering the power at the input of the output Lf −Cf filter. The voltage at the input side of the output Lf −Cf filter is calculated in (2), where just the fundamental component is considered. Thus, v0 (t) = V0 sin(ωo t + θ) v0 (t) =

Z C f + Z Lf v0 (t) Z Cf

(2)

where zCf and zLf are the capacitor and inductor impedances, respectively. An ideal output LC filter will not alter the phase of the output voltage. However, in practice, both the inductor and the capacitor have series resistance, and thus, the amplitude and the phase of the output voltage will be affected, over a large range of frequency, due to the lowering of the Q-factor of the LC filter. The impact of the LC filter on the amplitude is insignificant and can be neglected. Consequently, the power that is processed by the output side H-bridge is given in (3), i.e., p0 (t) = PPV + PPV cos (2(ωo t + θ)) .

(3)

On the other hand, the input power, which is extracted from the PV module, is controlled to be a constant level, i.e., PPV . Then, the ripple port will be processing the difference between the input and output power values as given in (4), i.e.,

IV. R IPPLE -P ORT P OWER P ROCESSING

prip (t) = PPV − p0 (t).

Fig. 1 illustrates the voltage polarity and current direction in the ripple-port load/source (LD and CD ). A small inductor

The power processed by the ripple port is the total power processed by the decoupling capacitor, i.e., CD , and the inductor,

(4)

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Fig. 4. Balanced power waveforms.

i.e., LD , which is calculated as follows: prip (t) = pLD (t) + pCD (t) = vLD (t)iLD (t) + vCD (t)iCD (t). (5) However, the same current flows in both LD and CD , which is given in (6). Then, Prip (t) as function of LD and CD , and the peak capacitor voltage is given in (7), i.e., dvCD (t) = VCD CD ωo cos(ωo t + φ) (6) dt V 2 CD ωo 1 − ωo2 LD CD prip (t) = CD sin (2(ωo t + φ)) . (7) 2

iCD (t) = CD

Substituting (3) and (7) in (4), the required decoupling capacitance, i.e., CD , and the phase angle of the voltage across the decoupling capacitor is calculated, as shown in (8) and (9), i.e., CD =

2PPV VC2D ωo (1 − ωo2 LD CD )

cos (2(ω0 t + θ)) = sin (2(ω0 t + φ)) π φ = ± + θ. 4

(8)

(9)

In (8), it is clear that the designer has to make a compromise between the decoupling capacitance and the peak voltage across its terminals; the latter will determine the stresses on the power switches, which, in turn, affect the efficiency and the cost of the inverter. Controlling the voltage across the decoupling capacitor according to (8) and (9) will result in a balance three-port system. Fig. 4 shows power waveforms of the RP-MII, where the double-frequency ripple, at the input side, is eliminated. The aforementioned analysis shows that the key of the ripple cancellation process, using the proposed ripple-port technique, is to control the voltage across the decoupling capacitor (vCD (t)) considering both (8) and (9). By doing so, the decoupling capacitor, which is connected through the ripple port, will store the excess power whenever the input constant power PPV is higher than the instantaneous output power (po (t)) and deliver it back to the output when the input power is lower than the output power. The controller scheme, based on sinusoidal pulse width modulation (SPWM), was presented in the next section. The proposed ripple port consists of an H-Bridge (four switches) followed by an LC filter. Selecting the switches depends on the voltage ratings, which is determined by the

Fig. 5. Block diagram of the SPWM control scheme used to control both the output and the ripple-port inverters.

peak voltage across the decoupling capacitor (VCD ). The latter, also, determines the required decoupling capacitance giving the average input power (PPV ). However, in the integrated implementation option, the dc link voltage is determined by the output (grid) voltage. Hence, VCD is determined now, and then, the decoupling capacitor is calculated using (8). Finally, the inductor is used to prevent any sudden change in the voltage across the decoupling capacitor as a result of the switching action for the H-Bridge. The inductance value (LD ) can be precisely calculated using (10); however, both the voltage across CD and the time change of the current are changing as the SPWM duty ratio changes. However, for the purpose that this inductor is being used, a precise value is not really critical. In addition, this difficulty in calculating LD can be avoided. A very small inductance, in the range of tens of microhenrys will accomplish the task. In the simulation and the experiment, in this paper, a 200 μH was used. Thus, di dt Vdc − vCD (t) . = ΔI

vLD = LD LD

(10)

V. C ONTROLLING THE P ROPOSED RP-MII One of the proposed RP-MII advantages is a simple control. The most commonly used SPWM control scheme is used to control both H-Bridge (output and Ripple ports) inverters. Fig. 5 shows the block diagram of the control system. The upper SPWM process generates the gate signals that control the output H-Bridge inverter, whereas the gate signals of the ripple port are generated by the lower one. The modulating signal of the ripple-port inverter is a shifted version of the one used for the output inverter, where the phase shift (φ) is calculated from (9). The DoM of the output inverter is determined by the output (grid) voltage; however, for the ripple port, the DoM determines the peak voltage across the decoupling capacitor (VCD ). On the other hand, VCD determines the required decoupling capacitor


(CD ) for a specific power rating, as shown in (8). The latter requires a compromise decision between the used decoupling capacitance on one hand, and the voltage stressed imposed on the power switches, on the other hand, which will affect the overall efficiency of the inverter.

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TABLE I C OMPONENTS L IST U SED IN THE S IMULATION

VI. R ELIABILITY OF THE P ROPOSED RP-MII The proposed topology aims to improve the reliability of the MII by using film capacitors instead of electrolytic ones. Hence, the reliability improvement for both topologies is examined. However, from [8], it was found that the decoupling capacitor is the limiting component whether electrolytic or film is used. Hence, the failure rate of the film capacitor is found using (11) [21], i.e., λP = λb πCV πQ πE .

(11)

λb is given in (12), which is the function of the operating temperature (T (◦ C)) and the voltage stress (S). These two factors are operating factors. Thus 5 18 S T +273 +1 exp 2.5 λb = 0.00099 . (12) 0.4 398 Fig. 6. Balance power waveforms.

Thus, λb , πQ , and πE all operating-related factors and will be the same for both configurations (integrated and separated options). Hence, they can be factored out, and λp is the function of just the capacitance factor, i.e., πCV , which, for the film capacitor, is calculated by (13), i.e., πCV = 1.1C 0.085 .

(13)

Then, the failure rate of the decoupling capacitor is given (14), i.e., λP = πCV K

(14)

where

Fig. 7. Zoom in of the input power waveform showing attenuation of the double-frequency ripple.

K = λ b πQ πE . Evaluating the failure rate for both configurations, with 36 μF used in the first configurations in Fig. 2, and two 5 μF capacitors in the second configuration in Fig. 3, the capacitance factors are calculated in (15), i.e., πCV 1 = 1.1(36)0.085 = 1.492 ⇒ λP 1 = 1.492K πCV 2 = 1.1(5)0.085 = 1.261 ⇒ λP 2 = 2(1.261)K = 2.522K.

where L0 is the basic (test) lifetime, Vop is the operating voltage, Vref is the rated voltage, T is the operating temperature, and Tref is the test temperature. As a result, from a reliability point of view, using a film capacitor, regardless of its value, will improve the overall reliability of the inverter.

(15) Then, the conclusion is that the number of capacitors used has a stronger effect on the failure rate than the value of the capacitance itself. Moreover, the lifetime projection formula in (16) [22] does not depend on the capacitance value, and consequently, both decoupling will have the same expected lifetime providing the same operating conditions. Thus, L0 2(Tref −T )/10 (16) L = 2.6087[(V /V )+0.5167] op r Vop Vr

VII. S IMULATION R ESULTS For the 235-W system, the component values of the RP-MII are listed in Table I. PSIM was used to verify the validity of the proposed RP-MII. Fig. 6 shows that the input, output, and ripple power waveforms match the theoretical predictions in Fig. 4. Fig. 7 reveals that processing 238-W results in less than a 1-W ripple (0.42% power ripple) at the input. DC link, output, and decoupling capacitor voltages are shown in Fig. 8. Fig. 9 shows the fast Fourier transform (FFT) waveform of the input power.

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TABLE II E XPERIMENTAL C OMPONENTS VALUES

Fig. 8. DC link, output, and decoupling capacitor voltage.

Fig. 9. FFT of the input power waveform.

Fig. 11. Experimental waveform: ac0 output voltage, ripple-port decoupling capacitor voltage, and the input current ripple.

Fig. 10. Ripple-port experimental setup.

VIII. E XPERIMENTAL R ESULTS

Fig. 12. Input current (top trace), and the FFT experimental measurement (bottom trace).

The ripple-port concept was experimentally tested using the new Solar_HV_DC_AC kit from Texas Instruments (TMDSHV1PHINVKIT) [23]. It is simply an insulated-gate bipolar transistor-based full-bridge inverter followed by a lowpass filter (LC-filter). Two boards were used to implement the output inverter and the ripple-port inverter, as shown in Fig. 10. Table II lists the values of the components used in the experiment test. Both boards were controlled by the pulse width modulation signals generated using a single TI Delfino microcontroller (TMS320F28335). Fig. 11 shows the output and decoupling capacitor voltages and the resulting ac component of the input current. The DoM for the output H-Bridge was kept

constant at 0.85. The DoM of the ripple-port H-Bridge (DoMr) and the phase angle (ϕ) were manually tuned to minimize the double-frequency ripple at the input side. The waveform in Fig. 10 shows that the ripple current is suppressed to less than 10% peak-to-peak, and this at DoMr = 0.848 and ϕ = 51.5◦ . Fig. 12 shows the input current along with its experimentally measured FF, which confirms that the 120-Hz frequency has been suppressed to the same amplitude as the other low-order harmonics. To examine the efficacy of the ripple port, the DoMr was reduced to 0.5, whereas the value of ϕ is kept the same as in the


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ACKNOWLEDGMENT The authors would like to thank Texas Instruments for their in-kind support of this research.

R EFERENCES

Fig. 13. Output voltage, decoupling capacitor voltage, and the input current when ripple port is purposely misadjusted.

Fig. 14. (Top trace) Input current and the FFT for reduced DoMr.

previous case. The results (see Fig. 13) clearly show the doublefrequency ripple at the input side. In this case, the input ripple was 476-m peak-to-peak. Fig. 14 shows the input current and its experimentally measured FFT, which is 30 dB higher than what was achieved with manual tuning in Fig. 12.

IX. C ONCLUSION This paper has proposed a new inverter topology that implements the double-frequency ripple cancellation concept. The proposed MII is based on the commonly used two-stage inverter. A third port is added for ripple cancellation purposes; it simply attached to the dc link. This implies that the ripple port could be added to many commercially available inverter topologies. A very small capacitance is required, where a highreliability film capacitor can be used instead of the bulky lowreliability electrolytic ones. Consequently, MII reliability is improved. Two configurations for implementing the proposed MII were examined by simulation, and the best was experimentally tested.

[1] S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, “A review of single-phase grid-connected inverters for photovoltaic modules,” IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1292–1306, Sep./Oct. 2005. [2] L. Quan and P. Wolfs, “A review of the single phase photovoltaic module integrated converter topologies with three different DC link configurations,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1320–1333, May 2008. [3] H. Haibing, S. Harb, N. Kutkut, I. Batarseh, and Z. J. Shen, “Power decoupling techniques for micro-inverters in PV systems-A review,” in Proc. IEEE ECCE, 2010, pp. 3235–3240. [4] W. Bower, “The AC PV building block-ultimate plug-n-play that brings photovoltaics directly to the customer,” presented at the National Center Photovoltaics (NCPV)/Solar Program Review Meeting, Denver, CO, USA, 2003. [5] R. S. Balog, Y. Y. Kuai, and G. Uhrhan, “A photovoltaic module thermal model using observed insolation and meteorological data to support a long life, highly reliable module-integrated inverter design by predicting expected operating temperature,” in Proc. IEEE ECCE, 2009, pp. 3343–3349. [6] E. D. Dunlop, D. Halton, and H. A. Ossenbrink, “20 years of life and more: Where is the end of life of a PV module?” in Conf. Rec. 31st IEEE Photovolt. Spec. Conf., 2005, pp. 1593–1596. [7] J. Liu and N. Henze, “Reliability consideration of low-power grid-tied inverter for photovoltaic application,” in Proc. 24th Eur. Photovolt. Solar Energy Conf., 2009, pp. 3688–3694. [8] S. Harb and R. S. Balog, “Reliability of candidate photovoltaic moduleintegrated-inverter topologies,” in Proc. 27th Annu. IEEE APEC, 2012, pp. 898–903. [9] S. B. Kjaer and F. Blaabjerg, “Design optimization of a single phase inverter for photovoltaic applications,” in Proc. 34th Annu. IEEE PESC, 2003, vol. 3, pp. 1183–1190. [10] T. Shimizu, K. Wada, and N. Nakamura, “Flyback-type single-phase utility interactive inverter with power pulsation decoupling on the DC input for an AC photovoltaic module system,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1264–1272, Sep. 2006. [11] T. Shimizu and S. Suzuki, “A single-phase grid-connected inverter with power decoupling function,” in Proc. IPEC, 2010, pp. 2918–2923. [12] T. Shimizu and S. Suzuki, “Control of a high-efficiency PV inverter with power decoupling function,” in Proc. 8th IEEE ICPE/ECCE, 2011, pp. 1533–1539. [13] A. C. Kyritsis, E. C. Tatakis, and N. P. Papanikolaou, “Optimum design of the current-source flyback inverter for decentralized grid-connected photovoltaic systems,” IEEE Trans. Energy Convers., vol. 23, no. 1, pp. 281–293, Mar. 2008. [14] C. R. Bush and B. Wang, “A single-phase current source solar inverter with reduced-size DC link,” in Proc. IEEE ECCE, 2009, pp. 54–59. [15] Y.-M. Chen and C.-Y. Liao, “Three-port flyback-type single-phase microinverter with active power decoupling circuit,” in Proc. IEEE ECCE, 2011, pp. 501–506. [16] S. Harb, H. Hu, N. Kutkut, I. Batarseh, and Z. J. Shen, “A three-port photovoltaic (PV) micro-inverter with power decoupling capability,” in Proc. 26th Annu. IEEE APEC, 2011, pp. 203–208. [17] H. Hu, S. Harb, X. Fang, D. Zhang, Q. Zhang, Z. J. Shen, and I. Batarseh, “A three-port flyback for PV microinverter applications with power pulsation decoupling capability,” IEEE Trans. Power Electron., vol. 27, no. 9, pp. 3953–3964, Sep. 2012. [18] P. T. Krein and R. S. Balog, “Cost-effective hundred-year life for singlephase inverters and rectifiers in solar and LED lighting applications based on minimum capacitance requirements and a ripple power port,” in Proc. 24th Annu. IEEE APEC, 2009, pp. 620–625. [19] T. P. Parker, “Reliability in PV inverter design: Black art or sciencebased discipline?” SolarBridge Technologies, May 16, 2011, White Paper Rev. 1.0. [20] S. J. Castillo, R. S. Balog, and P. Enjeti, “Predicting capacitor reliability in a module-integrated photovoltaic inverter using stress factors from an environmental usage model,” in Proc. NAPS, 2010, pp. 1–6. [21] Military Handbook MIL-HDBK-217F, Reliability Prediction of Electronic Equipment, United State Dept. Defense, Washington, DC, USA, 1991.

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Souhib Harb (S’10) received the B.S. degree in electrical engineering from Yarmouk University, Irbid, Jordan, in 2008, and the M.S. degree in electrical engineering from the University of Central Florida, Orlando, FL, USA, in 2010. He is currently working toward the Ph.D. degree in electrical engineering in the Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA. During his Master’s studies, he worked on a new three-port microinverter with power decoupling capability for photovoltaic applications. During his Ph.D. studies, he has focused on designing, simulating, building, and testing dc/ac inverters for gridconnected PV applications. His research interests include power electronics for renewable energy applications, reliability of power electronic converters, dc/dc and dc/ac converters, and nonlinearity phenomenon in power electronics.

Mehran Mirjafari received the B.S. degree in electrical engineering from Isfahan University of Technology, Isfahan, Iran, in 2002, the M.S. degree in electrical engineering—power electronics and electric machines from Sharif University of Technology, Tehran, Iran, in 2005, and the Ph.D. degree in electrical engineering (power electronics) from Texas A&M University, College Station, TX, USA, in 2013. His research interests include optimization of power electronic converters and renewable energy systems.

Robert S. Balog (S’92–M’96–SM’07) received the B.S. degree in electrical engineering from Rutgers, The State University of New Jersey, New Brunswick, NJ, USA, and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign, Urbana, IL, USA. From 1996 to 1999, he was an Engineer with Lutron Electronics, Coopersburg, PA, USA. From 2005 to 2006, he was a Researcher with the U.S. Army Corp of Engineers, Engineering Research and Development Center, Construction Engineering Research Laboratory, Champaign, IL, USA. From 2006 to 2009, he was a Senior Engineer at SolarBridge Technologies, Champaign, IL, USA. He then joined Texas A&M University, College Station, TX, USA, where he is currently an Assistant Professor with the Department of Electrical and Computer Engineering. He is the holder of 13 issued and pending U.S. patents. His current research interests include power converters for solar energy, particularly microinverters for ac photovoltaic modules and highly reliable electrical power and energy systems, including dc microgrids. Dr. Balog is a Registered Professional Engineer in the State of Illinois. He received the IEEE Joseph J. Suozzi INTELEC Fellowship in Power Electronics in 2001. He is a member of Eta Kappa Nu, Sigma Xi, National Society of Professional Engineers, American Solar Energy Society, and Solar Electric Power Association. He was the recipient of the 2011 Rutgers College of Engineering Distinguished Engineer Award.