Communication Ultrathin Electronics
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Wafer-Scale Fabrication of Ultrathin Flexible Electronic Systems via Capillary-Assisted Electrochemical Delamination Heng Zhang, Youdi Liu, Chao Yang, Li Xiang, Youfan Hu,* and Lian-Mao Peng* manufacturing. To assist the process, a rigid supporting substrate is commonly added with sufficient adhesion to survive the harsh microfabrication circumstances. However, detachment of an ultrathin and often fragile polymer film from the underlying supporting substrate after fabrication raises new issues related to maintenance of the integrity and performance of the electronic systems. A high delamination efficiency at large scale is therefore necessary. In a generic manner, a sacrificial layer can be introduced between the polymer substrate and the rigid support. Accordingly, the flexible electronic system on a polymer substrate can be obtained in a final delamination step after removal of the sacrificial layer via a wet etching process. However, this method is inefficient and usually takes tens of minutes to few hours, as limited by slow reaction and diffusion.[29,30] In addition, dissolution of an inorganic layer normally requires harsh etchants (e.g., HF, HNO3, NaOH, etc.) that might have adverse effects on electronic devices and systems.[18,21,31,32] Although selected water-soluble polymers such as dextran, poly(vinyl alcohol) (PVA), etc., are of less concern, they confine the processing to a water- or solvent- free method.[16,19,33–35] Alternatively, a dry etching process via reactive ion etching was reported that eliminates a thin layer of Si or polyimide (PI) as a temporary support, eventually leaving a flexible electronic system.[36–39] Despite the ease of microfabrication on these supporting materials, the dry etching approach is slow and costly. Recently, laser-assisted delamination has emerged as a promising method of exfoliating flexible electronic devices from a supporting substrate by eliminating a laser-reactive exfoliation layer.[40–43] However, this technique requires expensive apparatus and requires sophisticated design of processing parameters to circumvent laser-induced damage. In this work, we propose a handy and rapid capillary-assisted electrochemical delamination (CAED) approach to peel-off of a wafer-scale ultrathin film from a rigid substrate without degeneration of the performances of the electronic devices on the film. The film delamination takes place quickly, without any stress-induced damage, and the electronic components on the film are completely immune from solution exposure and impairment. Moreover, the delamination scheme is versatile and applicable with a 100% success rate to various plastic
Electronic systems on ultrathin polymer films are generally processed with rigid supporting substrates during fabrication, followed by delamination and transfer to the targeted working areas. The challenge associated with an efficient and innocuous delamination operation is one of the major hurdles toward high-performance ultrathin flexible electronics at large scale. Herein, a facile, rapid, damage-free approach is reported for detachment of wafer-scale ultrathin electronic foils from Si wafers by capillary-assisted electrochemical delamination (CAED). Anodic etching and capillary action drive an electrolyte solution to penetrate and split the polymer/Si interface, leading to complete peel-off of the electronic foil with a 100% success rate. The delamination speed can be controlled by the applied voltage and salt concentration, reaching a maximum value of 1.66 mm s−1 at 20 V using 2 m NaCl solution. Such a process incurs neither mechanical damage nor chemical contamination; therefore, the delaminated electronic systems remain intact, as demonstrated by high-performance carbon nanotube (CNT)-based thin-film transistors and integrated circuits constructed on a 5.5 cm × 5.0 cm parylene-based film with 4 µm thickness. Furthermore, the CAED strategy can be applied for prevalent polymer films and confers great flexibility and capability for designing and manufacturing diverse ultrathin electronic systems.
The momentum of flexible electronics development has created a spectrum of relevant applications in optoelectronics,[1–4] energy harvesting,[5–9] energy storage,[10] integrated circuits,[11,12] wearable sensors,[13–17] and implantable devices.[18–21] The active electronic elements, whether composed of organic, inorganic, or hybrid materials, are generally fabricated on a polymer substrate.[15,22–27] Scale-down of the polymer thickness (i.e., to a few or tens of microns) is necessary to render the electronic system more flexible, conformable, and imperceptible, characteristics that are particularly beneficial for epidermal and implantable electronics.[14,15,25,26,28] Regardless of these virtues, the polymeric nature and ultrathin geometries of the substrate create tremendous challenges in H. Zhang, Y. Liu, C. Yang, L. Xiang, Prof. Y. Hu, Prof. L.-M. Peng Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics Peking University Beijing 100871, China E-mail:
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[email protected] The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adma.201805408.
DOI: 10.1002/adma.201805408
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mechanical and chemical damages, thus guaranteeing a 100% successful delamination outcome. The proposed method surpasses other delamination techniques due to its uniquely simple, commendably rapid, nondestructive, versatile, and scalable features. Figure 2a and Movie S1 (Supporting Information) show the complete delamination process of a wafer-scale electronic foil. The foil consists of a 4 μm thick parylene-Cbased substrate (5.5 cm × 5.0 cm) and electronic devices. The detailed fabrication process is described in the Experimental Section. The ultrathin electronic foil was exfoliated from the Si wafer in 45 s under an applied voltage of 20 V using 1 m NaCl solution. At the onset of the delamination process, the electrolyte solution invades the parylene/Si interface along the side edges of the Si wafer. The peeling process quickly Figure 1. a,b) Schematic illustrations of a) electronic foil preparation on a heavily doped Si wafer (a) and the capillary-assisted electrochemical delamination process in which NaCl electrolyte extends to the mid-bottom portion of the Si wafer, leading to two fan-shaped domains solution penetrates the plastic/Si interface and climbs along the surface of the inclined Si wafer, prior to merging. Once the solution merges as highlighted by the red arrow (b). c) Schematic diagram of electrochemical etching of the Si wafer and capillary force-driven delamination of an electronic foil from the Si wafer. in the middle and levels up almost horizontally with the solutions in the fringes, the solution climb up at exactly the same pace along the substrates commonly used in large areas, such as parylene-C, inclined Si wafer but gradually slow until the remainder of the PI, poly(methyl methacrylate) (PMMA), and styrene ethylene film is peeled off. The top electronic components remain clear butylene styrene (SEBS), leading to high flexibility and capaof the solution while the substrate film is subjected to gentle bility for various system designs. Finally, as a proof of concept, exfoliation forces such that no mechanical damage occurs. carbon nanotube (CNT)-based transistors and circuits are fabriIt was observed that wrinkling emerges on the film due to cated via this approach on an ultrathin parylene film and exhibit trapped O2 bubbles beneath the film, revealing the ultrathin high fidelity to performance after peel-off, thus highlighting the robustness of this delamination technique. nature of the film, which can be easily ruffled by minor perFigure 1 illustrates a typical CAED process. First, an ultrathin turbations due to its low bending strength.[28] At the end, a polymer film is prepared on a heavily doped Si wafer as a rigid free-standing film is obtained that can recover its flatness after support, followed by fabrication of various electronic devices pick-up and be conformably laminated onto target surfaces, on the top via generic microfabrication approaches (Figure 1a). such as the rolled paper shown in Figure 2b. Furthermore, we Then, the Si wafer is tilted and just touches the surface of NaCl should mention that the Si wafer can be reused for the CAED electrolyte aqueous solution with its lower edge (Figure 1b). Note process with proper treatment. During the electronic foil that the polymer film along the edges of the Si wafer is trimmed delamination, H2SiO3 precipitated on the Si wafer turns the to allow the top surface of the Si wafer to contact the electrosurface into hydrophilic and highly resistive, which is adverse lyte solution. Thereafter, positive and negative potentials are to initiate the CAED process again on the same wafer. Thus, applied to the Si wafer and the electrolyte solution, respectively. before reuse the Si wafer, some etching treatment is needed, To ensure efficient electrochemical reactions, the Si wafer has such as immersed in buffered oxide etch for 1 min, to dissolve sufficiently low resistivity, in this case 0.009 Ω cm. Subsequently, the precipitate on the Si wafer, recovering a hydrophobic and the positively polarized Si wafer induces an anodic reaction: highly conductive surface. Then, another CAED process can Si (s) − 8e− + 8OH− → H2SiO3(s) + 3H2O + 2O2(g) (Figure 1c). be carried out on the same Si wafer, as shown in Figure S1 in the Supporting Information. The reproducibility of Si wafer Consequently, the anodic etching generates gaps between the makes the CAED process more cost-effective. The surface of plastic and Si wafer, triggering capillary forces that aid the the Si wafer was roughened after delamination. The root mean solution in climbing upward through the plastic/Si interface. square (RMS) value of roughness reaches 1.05 nm. The scanThe generated O2 bubbles produce a mild buoyancy force that ning electron microscopy (SEM) image inserted in Figure 2b generally facilitate the delamination process.[44] Simultaneand the atomic force microscopy (AFM) image in Figure S2 ously, H2SiO3 precipitates passivate the etched Si surfaces from (Supporting Information) prove the formation of micropores further corrosion. At the same time, the top electronic comand channels on the etched Si surface by the anodic electroponents on the thin film remain dry, clean, and intact during chemical reactions. These features can generate capillary the process. As the reaction progresses, the ultrathin film forces that contribute to water penetration into the parylene/ with the electronic systems on it completes the detachment Si interface and thus ease detachment of the parylene film.[44] from the supporting Si wafer without suffering any appreciable
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Figure 2. a) Photographs showing the progress in detachment of an ultrathin (≈4 µm) parylene-based electronic foil with dimensions of 5.5 cm × 5.0 cm from a Si wafer tilted by 40° under an applied voltage of 20 V using 1 m NaCl solution. The scale bars represent 1 cm. b) Photograph of ultrathin parylene-based electronic foil laminated on rolled paper and inset SEM image showing the etched surface of the Si wafer after peel-off of the parylene film. c–e) Plots of average delamination speeds as a function of applied voltage from 10 to 20 V (c), NaCl concentration from 1 × 10−3 m to 5.43 m (oversaturation) (d), and tilt angle of Si wafer (e), with the other two fixed variables addressed in the graphs. f–h) Pictures showing delamination of PI (f), PMMA (g), and SEBS (h) films with dimensions of 6.5 cm × 6.5 cm deposited with Au electrical wires.
Pursuit of a reproducible and efficient delamination outcome mandates an understanding of the key parameters that govern such a process. Given the occurrence of the electrochemical reactions, the applied voltage and NaCl concentration were tailored to investigate their influences on peel-off from Si wafers of parylene films of 2 µm thickness with the same sizes. Because the delamination speed is not uniform during the entire process, an average exfoliation speed is evaluated by dividing the sample length along the delamination direction by the elapsed time. It is not surprising that the average speed increased when the applied voltage was increased from 10 to 20 V with a fixed concentration of the NaCl electrolyte solution at 2 m (Figure 2c). It should be mentioned that although a voltage of 1.229 V theoretically sets the threshold for initiation of water electrolysis and thus the electrochemical etching of the Si wafer,[45] the peeling process proceeded quite slowly when the applied voltage was less than 10 V due to the limited electrochemical reactions. With the increase in voltage from 10 to 12 V, the delamination efficacy was promoted by the expedited anodic reactions. The exfoliation rate was gradually maximized and leveled off at 20 V, which could be attributed to the fact that the delamination was ultimately restrained by the capillary force-driven processes of water penetration and climbing. Even so, the delamination operation
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attained an average speed of 1.66 mm s−1, which is considerably faster than that of conventional wet or dry etching of a sacrificial layer, which generally takes tens of minutes to few hours. In addition, the delamination process can be accelerated by increasing the concentration of NaCl solution until oversaturation (i.e., 5.43 m at 293 K, 101.325 kPa) due to the enhanced electrical conductivity of the solution and thus promotion of the electrochemical reactions (Figure 2d). Interestingly, the delamination speed was nearly independent of the inclined angle of the Si wafer from 10° to 60°, which is the maximum range tunable by our clamping equipment (Figure 2e). The reason for this observation might be that in addition to fluctuation of the capillary action, the gravity of the liquid resistance to the CAED process changes minimally in response to the tilt angle due to the limited volume in the narrow gaps, making the delamination speed nearly independent of the inclined angle of the Si wafer. This finding is of practical importance in that arbitrary angles can be adopted in a certain range during the CAED process, thus supplying a large tolerance for equipment settings. Furthermore, the efficient delamination procedure uses low voltage and a low-cost mild solution together with simple equipment and operations, which can be feasibly scaled up for mass production.
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Figure 3. a,b) Comparisons of transfer characteristics (a) and output characteristics (b) of a carbon nanotube-based p-type TFT before and after delamination. c) Transfer characteristics of 115 p-type TFTs after delamination at a bias voltage Vds = −2 V with inset SEM image of the p-type TFT arrays. d) Statistical results of Ion/W values of the p-type TFTs after delamination at Vds = −2 V.
The validity of the CAED method was verified by testing on different types of prevalent polymer substrates, including PI, PMMA, and SEBS (Figure 2f–h; Figure S3, Supporting Information). For demonstration, pairs of Au electrical wires with a thickness of 50 nm were patterned on the polymer substrates. The delamination operation was successfully implemented on all of these electronic foils, especially the PMMA-based foil, which is less than 100 nm thick and notably fragile. Regardless of the investigated polymer types, all of the obtained electronic foils were even and damage-free. Therefore, the CAED approach manifests its great versatility and offers a possible option for processing of ultrathin electronic systems, which is problematic by conventional means. The large-area electronic foil can be transferred onto human skin or organs, which is promising for next-generation devices in human–machine interfaces and in situ recordings of physiological signals for health monitoring.[13,18,19,46] To further highlight the potency of the CAED, this approach was validated by delaminating an electronic foil composed of electronic systems on a parylene film. The performances of the CNT-based thin-film transistors (TFTs) and integrated circuits (ICs) on the film were examined before and after exfoliation. First, a layer of parylene, 2 μm thick, was grown on a heavily doped Si wafer with dimensions of 5.5 cm × 5.0 cm via chemical vapor deposition. The solution-processed high-purity semiconducting CNT networks were deposited on this layer as channel materials. P-type TFTs were fabricated by choosing palladium (Pd) as the source/drain contact metal with a channel length L = 5 µm and width W = 50 µm. Finally, a top encapsulation layer of parylene was deposited, creating a total thickness of the
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system near 4 µm. Figure 3a,b shows the typical transfer and output characteristics of the TFT recorded before and after the delamination process. Despite a slight attenuation (
