Scheduling Semiconductor Manufacturing Operations - CiteSeerX

Multidisciplinary International Conference on Scheduling : Theory and Applications (MISTA 2009) 10-12 August 2009, Dublin, Ireland

MISTA 2009

Scheduling Semiconductor Manufacturing Operations: Problems, Solution Techniques, and Future Challenges Lars Mönch • John W. Fowler • Stéphane Dauzère-Pérès • Scott J. Mason • Oliver Rose

Abstract In this paper, we discuss scheduling problems in semiconductor manufacturing. Starting from describing the manufacturing process, we identify typical scheduling problems that can be found in semiconductor manufacturing systems. We describe batch scheduling problems, job shop scheduling problems, scheduling problems with secondary resources, multiple orders per job scheduling problems, and scheduling problems related to cluster tools. We also present important solution techniques that are used to solve these scheduling problems by means of specific examples, and report on known implementations. Finally, we summarize some challenges in scheduling semiconductor manufacturing operations. 1

Introduction Recently, the electronics industry has become the largest industry in the world. A key aspect of this industry is the manufacturing of integrated circuits. In semiconductor manufacturing, integrated circuits are produced on silicon wafers. In the past, efforts for reducing costs included decreasing the size of the chips, increasing the wafer sizes, and improving the yield, while simultaneously trying to improve operational processes inside the semiconductor manufacturing systems. Currently, it seems that the improvement of operational processes creates the best opportunity to realize the necessary cost reductions. Semiconductor manufacturing is very capital intensive. Lots (denoted as jobs throughout the rest of this paper to conform with the scheduling literature) are the moving entities in semiconductor manufacturing systems. Each job contains a fixed number of wafers. The process conditions are very complex. We have to deal with parallel machines (also referred to as tools), different types of processes (batch and serial), sequence-dependent setup times, prescribed customer due dates for the jobs, and re-entrant process flows. Very often, we also have to cope with a large number of different products and a product mix that changes over time. Semiconductor manufacturing systems are prototypical examples for complex job shops. Lars Mönch University of Hagen E-mail: [email protected] John W. Fowler Arizona State University, Tempe E-mail: [email protected] Stéphane Dauzère-Pérès Ecole des Mines de Saint-Etienne E-mail: [email protected] Scott J. Mason University of Arkansas, Fayetteville E-mail: [email protected] Oliver Rose Dresden University of Technology E-mail: [email protected]

192


Crucial factors of competitiveness in semiconductor manufacturing are the ability to rapidly incorporate advanced technologies in electronic products, ongoing improvement of manufacturing processes, and, last but not least, the capability of meeting due dates for optimal customer satisfaction. In a situation where prices as well as the state of technology have settled at a certain level, the capability of meeting due dates along with the reduction of cycle time probably has become the most decisive factor to stand the fierce competition in the global market place. Cycle time is defined in this context as the time a job of wafers needs to travel through the semiconductor wafer manufacturing process including queue time, processing time, and transit time. Consequently, operations managers are under increasing pressure to ensure short and predictable cycle times. Production control strategies based on dispatching rules are very popular in semiconductor manufacturing (cf. the recent survey [55]). But at the same time, scheduling approaches attracted researchers and people from industry working in semiconductor manufacturing for the last two decades (cf. [5], [58] for some older references). This is mainly because of a relatively high degree of automation (compared to other industries) that even 20 years ago allowed for automated real-time data collection and because of the fact that manual production control often leads to strange or unexpected behavior of the systems due to the complexity of the manufacturing process. The well-known book on intelligent scheduling [61] describes several large-scale scheduling prototypes from the semiconductor manufacturing domain. Until recently, full factory scheduling methods seemed to be too costly in comparison to dispatching methods. However, with the recent dramatic increase in computer efficiency full fab scheduling methods have become more competitive. Because of the increasing automation pressure caused by automated material handling systems (AMHS) and new requirements on production control, it seems that scheduling approaches are both promising and necessary in the semiconductor manufacturing domain (cf. [43] for a survey related to scheduling requirements in semiconductor manufacturing). There is a lot of material from academia and also from software vendors related to scheduling in wafer fabs. However, except for the survey paper [53] from the early 1990s and a more current paper [30], there is no current source that reports on the breadth of scheduling problems within semiconductor manufacturing in one place. All the present authors worked in the past and will continue work in the future on different aspects of scheduling for semiconductor manufacturing. In this paper, we will give a concise summary of the different problems and solution techniques as well as comments on problems that need more research efforts in the future. We note that this paper is not a complete review of the vast literature, however we hope to stimulate even more research and some successful real-world implementations in scheduling wafer fabs. The paper is organized as follows. In Section 2, we describe the semiconductor wafer fabrication process briefly. We identify important scheduling problems in Section 3 and discuss solution techniques related to these scheduling problems. Finally, we identify some challenges for future research in Section 4. 2

Semiconductor Manufacturing Process Description A semiconductor chip is a highly miniaturized, integrated electronic circuit consisting of thousands of components. Every semiconductor manufacturing process starts with raw wafers, thin discs made of silicon or gallium arsenide. Depending on the diameter of the wafer, up to a few hundred identical chips can be made on each wafer, building up the electronic circuits layer by layer in a wafer fab. Next, the wafers are sent to Probe, where electrical tests identify any individual die that is not likely to be good when packaged. The bad dice are either physically marked or an electronic map is made of them so that they will not be put in a package. The probed wafers are sent to an Assembly facility where the "good" dice are put into the appropriate package. Finally, the packaged dice are sent to a Test facility where they are tested in order to ensure that only good products are sent to customers. Wafer fab and Probe are often called the "Frontend" and Assembly and Test are often called the "Backend."

193


Considering the scale of integration, the type of chip, the type of package, and customer specifications, the whole manufacturing process may require up to 700 single processing steps and up to three months to produce. The four main stages of semiconductor manufacturing are shown in Figure 1.

Probe

Wafer Fab

DAP-3XC

Test

Assembly

Figure 1: Main Stages of Semiconductor Manufacturing Many authors have remarked on the difficulties of semiconductor manufacturing (cf. [2], [42], [50], [53], [55], [58] amongst others). Wafer fabrication has a number of unusual facets that are described below. In a typical wafer fab, there often are dozens of process flows. Each process flow contains 200-700 processing steps and more than one hundred machines. These machines are expensive, ranging in price from a couple of hundred thousand dollars to over twenty million dollars per tool. The economic necessity to reduce capital spending dictates that such expensive machines be shared by all jobs requiring the particular processing operation provided by the machine, even though they may be at different stages of their manufacturing cycle. This results in a manufacturing environment that is different in several ways from both traditional flow shops as well as job shops. The main consequence of the re-entrant flow nature is that wafers at different stages in their manufacturing cycle have to compete with each other for the same machines. The typical re-entrant flow of a wafer fab is shown in Figure 2.

Material Preparation

Deposit Film

Etch Film

Pattern Film

Test

Figure 2: Re-entrant Flow in Wafer Fabs Furthermore, the nature and duration of the various operations in a semiconductor flow differ significantly. Some operations require 15 minutes or less to process a job, while others may require over 12 hours. Many of these long operations involve batch processes. In reality, it is not uncommon for one-third of the fab operations to be batch operations. Batch machines tend to off-load multiple jobs (1 to 12) onto machines that are capable of processing only one job at a time. This leads to the formation of long queues in front of these serial machines and ultimately a non-linear flow of products in the factory. The probabilistic occurrence of long tool failures results in large variability in the time a job spends in process. High variability in cycle times prevents accurate prediction of production cycle times, resulting in longer leadtime commitments. There are some machines, such as implanters, that require significant sequence-dependent setups. If not scheduled well, these tools can become bottlenecks. Finally, some processing steps require an auxiliary resource (a so-called secondary resource), such as a reticle in photolithography, in order to process the job. Some of these auxiliary resources are quite expensive, so only a very limited number of them are purchased. Therefore, the challenge is to ensure that the machine and the auxiliary resource are available at the same time.

194


In modern 300-mm wafer fabs, wafers are transported in front-opening unified pods (FOUP) using an AMHS. Because of the increase in area and weight of the wafers, it is obvious that a manual handling of the wafers has to be eliminated. This fact increases the need for scheduling approaches. Automated material handling is always a critical operation in modern wafer fabs (cf. [1], [23], [33] for more details on AMHS in semiconductor manufacturing). Next, we discuss backend operations. There are usually more types of parts being made in an assembly factory than in a wafer fab, but each part type requires 10-20 steps instead of 200700. One difficulty in modeling these operations is the fact that a job is often divided into subjobs with each sub-job being sent to the next machine when it completes an operation. Thus, one job may be being processed across several machines at the same time. Another difficulty is that there is often a very significant amount of setup required to change over from one product type to another. Finally, batching machines are also often present in assembly factories. Test operations have several problems that are difficult to model. First, the sequence of test operations and the test times are not always fixed. These can be changed based on recent product yields, maturity of a product, and such. Second, there are two major types of equipment used in test operations. These are the test system itself (tester) and the loading mechanism (handler). The tester may have a single or multiple test heads connected to it. The interactions between the tester, the test heads, and the handler can be quite complex to model accurately. Finally, there can be significant sequence-dependent changeover times. In this paper, we will restrict ourselves due to space limitations mainly to the wafer fab part of semiconductor manufacturing. But in a few situations, we will also discuss scheduling problems related to the backend stage. 3

Scheduling Problems and Solution Techniques

3.1 Batching Problems A batch is defined as a group of jobs that have to be processed jointly. The completion time of a batch is determined as the completion time of the last job in the batch. A batch scheduling problem consists in grouping the jobs on each machine into batches and in scheduling these batches. Two types of batching problems are considered. The first type is called s-batching. Here, the processing time of a batch is the sum of the processing times of all jobs that form the batch. The second type is p-batching. In this case, the processing time of the batch is given by the maximum processing time of jobs contained in the batch (cf. [45], [30] for recent surveys related to batching in general and to batching for semiconductor manufacturing respectively). In semiconductor manufacturing, there are some situations where s-batching is important. For example, several scheduling problems related to steppers in the photolithography area lead to s-batching problems. Here, runs are formed. A run is a group of jobs of the same mask layer. Therefore, the same reticle is required for processing. Forming a run and processing the jobs of the run in a consecutive manner avoids frequent reticle changes. But p-batching is much more important in semiconductor manufacturing. The common assumption is that there exists a fixed batch size B as capacity of the batch machine. Burn-in ovens for semiconductor manufacturing are used to heat-stress test IC chips. Several chips can be tested in a burn-in oven simultaneously, so that a burn-in oven is a batch processing machine. The processing time of each batch is determined by the longest job processing time among those of all the jobs contained in the batch. There are many papers that deal with burnin ovens, for example, the paper [56], where a dynamic programming formulation is coupled with a random key genetic algorithm. Simulated annealing-based heuristics are suggested in [31] for a burn-in scheduling problem. The diffusion furnaces in wafer fabs are an example of batch machines. Here, the jobs are assigned to incompatible job families. While several jobs can be processed at the same time, jobs of different families cannot be processed together due to the chemical nature of the

195


process. The processing time of all jobs within one family is the same. Therefore, batching jobs with incompatible families is a special case of p-batching. We refer to [3], where the problem Pm | batch , incompatible | TWT is discussed. We denote by batch, incompatible the pbatching with incompatible families, while the performance measure of interest is minimizing total weighted tardiness TWT := ∑ w j max C j − d j ,0 . The notation w j is used for the

(

)

weight of job j, C j is used for the completion time, and d j for the due date of job j. [3] extends solution techniques for 1 | batch , incompatible | ∑ T j presented in [32]. Dispatching rules are used to form batches. Genetic algorithms assign the batches to machines and sequence them. This approach is extended to Pm | r j , batch , incompatible | ∑ w j T j in [35]. This problem is harder because the given release dates r j of the jobs require a decision whether it makes sense to wait for future jobs arrivals in case of incomplete batches or to start a non-full batch. Machine learning techniques applied to batching problems in semiconductor manufacturing are considered in [20], [36]. The problem Pm | r j , batch , incompatible | L max

{

}

where Lmax := max C j − d j | j = 1,K , n denoting the maximum lateness, is solved in [27] using genetic algorithms. 3.2 Job Shop Problems A wafer fab can be modeled as a complex job shop [28], [42]. This type of job shop contains unrelated parallel machines with sequence-dependent setup times and dedications, parallel batch machines, re-entrant flows, and ready times of the jobs. Using the α | β | γ notation these problems can be expressed by FJ | r j , s jr , batch , incompatible , recrc | ∑ w j T j ,

(1)

where FJ denotes the flexible job shop, s kj refers to sequence-dependent setup times, and the term recrc is used for the re-entrant flows. Alternatively, the scheduling problem can be modeled as FJ | r j , s jr , batch , incompatible , recrc | Lmax .

(2)

Problems of type (1) and (2) have been studied very intensively over the last ten years. Most of the solution approaches are based on disjunctive graphs [7]. A good documentation of attempts to solve problem (2) for test facilities can be found in [42]. Several variants of the shifting bottleneck heuristic are used. This heuristic decomposes the job shop scheduling problem into a set of smaller scheduling problems related to parallel machines. These smaller scheduling problems are called sub problems. Several aspects, like identifying appropriate sub problem solution procedures and determining an appropriate sequence to solve the sub problems, are discussed in a series of papers by Uzsoy and his group (cf., for example, [14], [15], [54]). Mason et al. suggested a modified shifting bottleneck heuristic to tackle problem (1) for wafer fabs in [28]. The performance of this scheme was assessed within a rolling horizon setting using discrete event simulation in [37]. Sub problem solution procedures based on genetic algorithms are suggested. A distributed variant of the shifting bottleneck heuristic for wafer fabs using information from an upper planning layer is discussed in [34]. This distributed

196


scheduling scheme is the base for the hierarchically organized multi agent system FABMAS [38]. While very often only single instances were considered, [49] contains the results of a rolling horizon scheme for problem (2). Later, several attempts were made to reduce the number of nodes in the scheduling graph by considering only specific bottleneck machines explicitly. Experiments with this approach for jobs shops that include machine breakdowns are presented in [4], [51], [52]. Only little is known on the impact of rescheduling techniques for complex job shops [29]. A multi-criteria approach for scheduling wafer fabs based on the shifting bottleneck heuristic is suggested in [44]. While some progress was made related to the integration of transportation operations and other generalizations in scheduling research for job shops (cf. [7] for a documentation of state of the art approaches), it seems that only some first steps into this direction were done in semiconductor manufacturing (cf. [16], [46]). Even the simulation of the base system for manufacturing and for transportation is sophisticated in the case of wafer fabs. But this is a requirement for assessing the performance of rolling horizon schemes. Many current scheduling techniques for large-scale job shops with a makespan objective are based on metaheuristic search using the disjunctive graph formulation [7]. Because of the reentrant flows and different objectives, only initial steps are known to apply such methods to scheduling problems in semiconductor manufacturing [60]. Simulated annealing techniques based on a generalized disjunctive formulation for several batch machines and up-and-down stream machines are discussed in [59]. The resulting scheduling software called Batch Optimization Solver (BOS) is designed to solve real-world scheduling problems in the diffusion area of a wafer fab. Beside the global scheduling problems (1) and (2), there are many papers that discuss scheduling approaches for specific machine environments in semiconductor manufacturing. We refer, for example, to [11] where a genetic algorithm is used to schedule jobs on furnace machines including sophisticated process conditions. Another example is given by [48] where ant colony optimization approaches are used to schedule jobs on a group of machines that is the leading bottleneck in a wafer fab. The use of mixed integer and constraint programming approaches for solving real-world scheduling problems in a wafer fab is described in [6], [19]. Instead of considering the entire scheduling problem, a decomposition into different sub problems is performed before using mathematical programming tools. 3.3 Problems with Secondary Resources As already described in Section 2, secondary resources are an important restriction in semiconductor manufacturing. Secondary resources are typically related to parallel machines. Photolithography steppers that require product and mask layer specific reticles are a typical example for such type of machines. Scheduling heuristics based on dispatching rules for the problem Pm | r j , aux | ∑ w j C j are described, for example, in [12]. Here, we denote by aux the secondary resource. Several heuristics for stepper scheduling based on appropriate modifications of the Apparent Tardiness Cost (ATC) dispatching rule are described in [13]. The scheduling of a single batch processing machine with job families motivated by burn-in operations in a test facility is discussed in [24]. Load boards are considered as secondary constraints. Several heuristics are presented. 3.4 Multiple Orders per Job Problems The combination of decreased line widths and more area per wafer in 300-mm wafer fabs result in fewer wafers being needed to fill an IC order of a customer. Each wafer fab will have only a limited number of FOUPs as they are expensive. A large number of FOUPs have the potential to cause overload in the AMHS. In addition, some batching tools have the same

197


processing times regardless of the number of wafers in the batch. Thus it is not reasonable to assign an individual FOUP to each order. Therefore, 300-mm manufacturers often have the need and the incentive to group orders from different customers into one or more FOUPS to form production jobs. These jobs have to be scheduled on the various types of tool groups in the wafer fab and processed together. This class of integrated job formation and scheduling problems are called multiple orders per job (MOJ) scheduling problems. There is a series of papers from Mason and his group that deal with single and parallel machine MOJ scheduling problems [21], [22], [47]. Metaheuristics, dispatching rules, and column generation techniques are used to solve the MOJ scheduling problems. The special case of a two-machine flow shop MOJ scheduling problem is presented in [25]. 3.5 Scheduling of Cluster Tools Cluster tools combine single-wafer processing modules with wafer handling robots in one closed environment (cf. [26] for a recent survey of cluster tool scheduling). Scheduling of cluster tools is challenging because the cycle time of wafers in a cluster tool depends on the used wafer recipes, cluster tool control and architecture, wafer waiting times, and sequencing [17]. A discrete event simulation tool is used in [17] to determine appropriate cycle times for wafers within cluster tools. Several techniques based, for example, on neural networks and beam search are suggested in [39], [40], and [41]. A simulated annealing approach is discussed in [57]. 4

Future Challenges

There are several directions for future research related to scheduling in semiconductor manufacturing. The usage of modern metaheuristics for scheduling wafer fabs globally has to be researched. Furthermore, the impact of rescheduling strategies has to be investigated in much more detail. Future research requires a better incorporation of AMHS decisions into the job scheduling decision-making process. Algorithms are expected that take various specific properties of modern AMHS into account. It seems that a direct extension of the results presented for related problems in [7] is not straightforward. There is a definite need to better understand the relationship between planning and scheduling decisions for complex manufacturing systems like wafer fabs. Some promising initial steps towards reaching this goal are described in [9]. Here, the interaction of more global and local scheduling decisions is studied. Based on the experiences with the FABMAS multi agent system [38] and the distributed shifting bottleneck heuristic [34], a hierarchical decomposition of wafer fab scheduling problems offers some advantage. However, more theoretical insights are necessary. So far, only little is known on the interaction of Advanced Process Control (APC) and scheduling decisions. However, APC information should definitely impact scheduling constraints and criteria. For instance, scheduling some lots with the same process on a tool might be prioritized based on the requirements for the tool to get data on the process. Finally, very often we find it hard to transfer scheduling results from an academic environment to the shop floor. This is mainly caused by data problems. Therefore, appropriate software representations of our scheduling algorithms are required that can better deal with distributed and with missing data. References 1.

Agrawal, G. K., Heragu, S. S., A Survey of Automated Material Handling Systems in 300mm Semiconductor Fabs, IEEE Transactions on Semiconductor Manufacturing, 19(1), 112-120, (2006)

198


2. 3.

4.

5. 6.

7. 8. 9.

10.

11.

12. 13.

14. 15. 16.

17. 18. 19.

20. 21.

22.

Atherton, L., Atherton, R. W., Wafer Fabrication: Factory Performance and Analysis. Kluwer Academic Publishers, Boston, Dordrecht, London, (1995) Balasubramanian, H., Mönch, L., Fowler, J. W., M. Pfund, Genetic Algorithm Based Scheduling of Parallel Batch Machines with Incompatible Job Families to Minimize Total Weighted Tardiness, International Journal of Production Research, 42(8), 1621-1638, (2004) Barua, A., Narasimhan, R., Upasani, A., Uzsoy, R., Implementing Global Factory Schedules in the Face of Stochastic Disruptions, International Journal of Production Research, 43(4), 94-109, (2005) Bitran, G. R., Tirupati, D., Development and Implementation of a Scheduling System for a Wafer Fabrication Facility, Operations Research, 36(3), 377-395, (1988) Bixby, R., Burda, R., Miller, D., Short-Interval Detailed Production Scheduling in 300mm semiconductor manufacturing using Mixed Integer Programming, Advanced Semiconductor Manufacturing Conference, 148-154, (2006) Brucker, P., Knust, S. Complex Scheduling, Springer, Berlin, Heidelberg, (2006) Brucker, P., Gladky, A., Hoogeveen, H., Kovalyov, M. Y., Potts, C. N., Tautenhahn, T., van de Velde, S., Scheduling a Batching Machine, Journal of Scheduling, 1, 31-54, (1998) Bureau, M., Dauzere-Peres, S., Yugma, C., Vermarien, L., Maria, J.-B., Simulation Results and Formalism for Global-Local Scheduling in Semiconductor Manufacturing, Proceedings of the 2007 Winter Simulation Conference, 1768-1773, (2007) Chandra, S. M., Mathirajan, M., Gopinath, R., Sivakumar, A. I., Tabu Search Methods for Scheduling a Burn-in Oven with Non-identical Job Sizes and Secondary Resource Constraints, International Journal of Operational Research, 3(1-2), 119-139, (2008) Chien, C.-F., Chen, C.-H., A Novel Timetabling Algorithm for a Furnace Process for Semiconductor Fabrication with Constrained Waiting and Frequency-Based Setups, OR Spectrum 29, 391-419, (2007) Cakiki, E., Mason, S. J. Parallel Machine Scheduling Subject to a Auxiliary Resource Constraints, Production Planning and Control, 18(3), 217-225, (2007) de Diaz, S.L.M., Fowler, J. W., Pfund, M.E., Mackulak, G.T., Hickie, M. Evaluating the Impacts of Reticle Requirements in Semiconductor Wafer Fabrication, IEEE Transactions on Semiconductor Manufacturing, 18(4), 622- 632, (2005) Demirkol, E., Mehta, S., Uzsoy, R., A Computational Study of Shifting Bottleneck Procedures for Shop Scheduling Problems, Journal of Heuristics, 3, 111-137, (1997) Demirkol, E., Uzsoy, R. Decomposition Methods for Reentrant Flow Shops with Sequence Dependent Setup-Times, Journal of Scheduling, 3, 155-177, (2000) Driessel, R., Mönch, L. An Integrated Scheduling and Automated Material Handling Approach for Complex Manufacturing Systems, Proceedings of the 2008 IEEE International Conference on Industrial Engineering and Engineering Management, (2008) Dümmler, M. Using Simulation and Genetic Algorithms to Improve Cluster Tool Performance, Proceedings of the 1999 Winter Simulation Conference, 875-879, (1999) Erramilli, V., Mason, S. J., Multiple Orders per Job Compatible Batch Scheduling, IEEE Transactions on Electronics Packaging Manufacturing, 29 (4), 285-296, (2006) Fordyce, K., Bixby, R., Burda, R., Technology that Upsets the Social Order – A Paradigm Shift in Assigning Lots to Tools in a Wafer Fabricator – The Transition from Rules to Optimization, Proceedings of the 2008 Winter Simulation Conference, 2277- 2285, (2008) Geiger, C.D., Uzsoy, R., Learning Effective Sequencing Rules for Batch Processor Scheduling, International Journal of Production Research, 46, 1431-1454, (2008) Jampani, J., Mason, S. J., Column Generation Heuristics for Multiple Machine, Multiple Orders per Job Scheduling Problems, Annals of Operations Research, 159(1), 261-273, (2008) Jia, J., Mason, S. J., Semiconductor Manufacturing Scheduling of Jobs Containing Multiple Orders on Identical Parallel Machines, International Journal of Production Research, To appear, (2009).

199


23. Jimenez, J., Mackulak, G.T., Fowler, J.W., Levels of Capacity and Material Handling System Modeling for Factory Integration Decision Making in Semiconductor Wafer Fabs, IEEE Transactions on Semiconductor Manufacturing, 21(4), 600-613, (2008) 24. Kempf, K., Uzsoy, R., Wang, C., Scheduling a Single Batch Processing Machine with Secondary Resource Constraints, Journal of Manufacturing Systems, 17(1), 37-51, (1998) 25. Laub, J. D., John W. Fowler, Keha, A. B., Minimizing Makespan with Multiple-Ordersper-Job in a Two-Machine Flowshop, European Journal of Operational Research, 128(1), 63-79, (2007) 26. Lee, T.-E. A Review of Scheduling Theory and Methods for Semiconductor Manufacturing Cluster Tools, Proceedings of the 2008 Winter Simulation Conference, 21792135, (2008) 27. Malve, S., Uzsoy, R. A Genetic Algorithm for Minimizing Maximum Lateness on Parallel Identical Batch Processing Machines with Dynamic Job Arrivals and Incompatible Job Families, Computers & Operations Research, 34(10), 3016-3028, (2007) 28. Mason, S. J., Fowler, J. W., Carlyle, W. M., A Modified Shifting Bottleneck Heuristic for Minimizing Total Weighted Tardiness in Complex Job Shops, Journal of Scheduling, 5 (3), 247-262, (2002) 29. Mason, S. J., Jin, S., Wessels, M. C., Rescheduling Strategies for Minimizing Total Weighted Tardiness in Complex Job Shops, International Journal of Production Research, 42(3), 613-628, (2004). 30. Mathirajan, M., Sivakumar, A. I. A., Literature Review, Classification and Simple Metaanalysis on Scheduling of Batch Processors in Semiconductor, International Journal of Advanced Manufacturing Technology, 29, 990-1001, (2006) 31. Mathirajan, M., Sivakumar, A. I., Kalaivani, P., An Efficient Simulated Annealing Algorithm for Scheduling Burn-in Oven with Non-identical Job Sizes, International Journal of Applied Management and Technology, 2(2), 117-138, (2004) 32. Mehta, S. V., Uzsoy, R., Minimizing Total Tardiness on a Batch Processing Machine with Incompatible Job Families, IIE Transactions, 30, 165-178, (1998) 33. Montoya-Torres, J. R., A Literature Survey on the Design Approaches and Operational Issues of Automated Wafer-transport Systems for Wafer Fabs, Production Planning & Control, 17(6), 648-663, (2006) 34. Mönch, L., Driessel, R., A Distributed Shifting Bottleneck Heuristic for Complex Job Shops. Computers & Industrial Engineering, 49, 673-680, (2005) 35. Mönch, L., Balasubramanian, H., Fowler, J. W., Pfund, M. E., Heuristic Scheduling of Jobs on Parallel Batch Machines with Incompatible Job Families and Unequal Ready Times, Computers & Operations Research 32, 2731-2750, (2005) 36 Mönch, L., Zimmermann, J., Otto, P., Machine Learning Techniques for Scheduling Jobs with Incompatible Families and Unequal Ready Times on Parallel Batch Machines, Journal of Engineering Applications of Artificial Intelligence, 19(3), 235-245, (2006) 37. Mönch, L., Schabacker, R., Pabst, D., Fowler, J. W., Genetic Algorithm-based Subproblem Solution procedures for a Modified Shifting Bottleneck Heuristic for Complex Job Shops, European Journal of Operational Research, 177(3), 2100-2118, (2007) 38. Mönch, L., Stehli, M., Zimmermann, J., Habenicht, I., The FABMAS Multi-AgentSystem Prototype for Production Control of Waferfabs: Design, Implementation, and Performance Assessment, Production Planning & Control, 17(7), 701-716, (2006) 39. Niedermayer, H., Rose, O., Solution Approaches for the Cluster Tool Scheduling Problem in Semiconductor Manufacturing, Proceedings of the 16th European Simulation Symposium, (2004) 40. Niedermayer, H., Rose, O., Approximation of the Cycle Time of Cluster Tools in Semiconductor Manufacturing, Proceedings of the 2004 Industrial Engineering Research Conference, (2004) 41. Oechsner, S., Rose, O., Scheduling Cluster Tools Using Filtered Beam Search and Recipe Comparison, Proceedings of the 2005 Winter Simulation Conference, (2005)

200


42. Ovacik, I. M., Uzsoy, R., Decomposition Methods for Complex Factory Scheduling Problems, Kluwer Academic Publishers, Massachusetts, (1997) 43. Pfund, M., Mason, S., Fowler, J. W., Dispatching and Scheduling in Semiconductor Manufacturing, Handbook of Production Scheduling, J. Herrmann, (eds.), Springer, Heidelberg, 213-241, (2006) 44. Pfund, M. E., Balasubramanian, H., Fowler, J. W., Mason, S. J., Rose, O., A MultiCriteria Approach for Scheduling Semiconductor Wafer Fabrication Facilities, Journal of Scheduling, 11(1), 29-47, (2008) 45. Potts, C. N., Kovalyov, M. Y., Scheduling with Batching: a Review, European Journal of Operational Research, 120, 228-249, (2000) 46. Qu, P., Steinmiller, B., Mason, S. J., Incorporating Automated Material Handling Systems Into a Disjunctive Graph, Proceedings of the 2004 Industrial Engineering Research Conference, Houston, (2004) 47. Qu, P., Mason, S. J., Metaheuristic Scheduling of 300mm Jobs Containing Multiple Orders, IEEE Transactions on Semiconductor Manufacturing, 18 (4), 633-643, (2005) 48. Song, Y., Zhang, M. T., Yi, J., Zhang, L., Zheng, L., Bottleneck Station Scheduling in Semiconductor Assembly and Test Manufacturing using Ant Colony Optimization, IEEE Transactions on Automation Science and Engineering, 4(4), 569 – 578, (2007) 49. Souriraja, K., Uzsoy, R., Hybrid Decomposition Heuristics for Solving Large-Scale Scheduling Problems in Semiconductor Wafer Fabrication, Journal of Scheduling, 10, 4165, (2007) 50. Sze, S. M., Semiconductor Devices: Physics and Technology, John Wiley & Sons, New York, Second Edition, (2001) 51. Upasani, A. A., Uzsoy, R., Sourirajan, K., A Problem Reduction Approach for Scheduling Semiconductor Wafer Fabrication Facilities, IEEE Transactions on Semiconductor Manufacturing, 19(2), 216-225, (2006) 52. Upasani, A. A., Uzsoy, R., Integrating a Decomposition Procedure with Problem Reduction for Factory Scheduling with Disruptions: a Simulation Study, International Journal of Production Research. 46 (21), 5883-5905, (2008) 53. Uzsoy, R., Lee, C. Y., Martin-Vega, L., A Review of Production Planning and Scheduling Models in the Semiconductor Industry, Part II: Shop Floor Control, IIE Transactions, 26, 44-55, (1994) 54. Uzsoy, R., Wang, C.-S., Performance of Decomposition Procedures for Job-Shop Scheduling Problems with Bottleneck Machines, International Journal of Production Research, 38, 1271-1286, (2000) 55. Varadarajan, A., Sarin, S. C., A Survey of Dispatching Rules for Operational Control in Wafer Fabrication, Proceedings INCOM 2006, (2006) 56. Wang, C. S., Uzsoy, R, A Genetic Algorithm to Minimize Maximum Lateness on a Batch Processing Machine, Computers & Operations Research, 29, 1621-1640, (2002) 57. Yim, S. J., Lee, D. Y., Scheduling Cluster Tools in Wafer Fabrication Using Candidate List and Simulated Annealing, Journal of Intelligent Manufacturing, 10, 531–540, (1999) 58. Wein, L., Scheduling Semiconductor Wafer Fabrication, IEEE Transactions on Semiconductor Manufacturing, 1, 115-130, (1988) 59. Yugma, C., Dauzere-Peres, S., Derreumaux, A., Sibille, O., A Batch Optimization Software for Diffusion Area Scheduling in Semiconductor Manufacturing, Advanced Semiconductor Manufacturing Conference 2008 (ASMC 2008), 327-332, (2008) 60. Zoghby, J., Barnes, J. W., Hasenbein, J. J., Modeling the Reentrant Job Shop Scheduling Problem with Set-ups for Metaheuristic Searches, European Journal of Operational Research, 167, 336-348, (2005) 61. Zweben, M., Fox, M. S. Intelligent Scheduling, Morgan Kaufman Publishers, San Fransisco, (1994)

201