Selective Harmonic Mitigation Technique for multilevel Cascaded H ...

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multilevel Cascaded H-bridge Converters. Javier Napoles, Jose I. Leon, Leopoldo G. Franquelo, Ramon Portillo and Miguel A. Aguirre. Electronic Engineering ...
Selective Harmonic Mitigation Technique for multilevel Cascaded H-bridge Converters Javier Napoles, Jose I. Leon, Leopoldo G. Franquelo, Ramon Portillo and Miguel A. Aguirre Electronic Engineering Department, School of Engineering University of Seville Seville, Spain 41092 Email: [email protected] Abstract—The increasing demand of energy and proliferation of non-linear loads have leaded to the appearance of new grid codes which limit the maximum acceptable harmonic levels. In this context, multilevel topologies are very attractive because can generate output waveforms with a low harmonic content using a low switching frequency. In this paper, the recently presented selective harmonic mitigation technique (SHMPWM) is adapted to a nine-level converter. Its flexibility is exploited to meet the EN 50160 and CIGRE WG 36-05 grid codes without any additional filtering system using 10 switching angles per quarter of period in a wide range of amplitudes of the fundamental harmonic from 0.70 to 1.22. Some results validating this technique applied to this topology are presented. A comparison with the well known selective harmonic elimination method is included showing the advantages of the SHMPWM technique.

I. I NTRODUCTION The power losses when solid state devices are used limit the maximum switching frequency that can be used in a power electronic converter. Reducing the number of switchings per cycle generates higher harmonic content. In order to reduce the harmonic distortion content, an appropriate modulation technique has to be chosen. Another strategy to reduce the harmonic content keeping the number of switchings is increasing the number of levels of the converter using a more complex topology. This fact leads to a higher number of devices but it could save energy and the extra cost of filtering systems. Several studies related with pulse width modulation (PWM) techniques have been published presenting different strategies to generate the most interesting harmonic content. The well known selective harmonic elimination (SHEPWM) technique [1] can set the amplitude of the fundamental harmonic and make it zero the amplitude of k − 1 desired harmonics (if k switching angles are used per quarter of period). The recently presented selective harmonic mitigation technique (SHMPWM) [2], [3] generates output waveforms that completely fulfil specific grid codes (for instance, the EN 50160 [4] and CIGRE WG 36-05 [5]) with a lower switching frequency than SHEPWM. The SHMPWM technique has been previously presented using a three-level converter but, as happens with the SHEPWM technique, it can be extended to converters with a higher number of levels independently of the specific converter topology. Several papers dealing with the SHEPWM technique applied to these type of converters have been previously published

[6], [7]. This paper presents the results obtained using the SHMPWM technique in a nine-level converter. In this case, the study is focused on the application of the SHMPWM to a two-cell cascaded H-bridge converter (2-cell CHB) with a dc voltage ratio equal to 1:3. However, it has to be noticed that other nine-level converter topologies as the diode-clamped or flying capacitor [8]–[10] could use exactly the same switching angles achieving the same results. This paper is organized as follows; in section II the characteristics of the topology under study are summarized. Next section describes the SHMPWM principle and how it is extended to a nine-level topology. In section IV, the results obtained using the SHMPWM method are presented. Finally, the conclusions of the paper are detailed. II. N INE -L EVEL C ASCADED H- BRIDGE TOPOLOGY Several three-level power cells formed by full H-bridges can be associated to build a converter with a higher number of levels as can be observed from Fig. 1. In fact, connecting several three-level cells it can be obtained a converter with many levels as desired [9]. In general, if n power cells are connected in series to build the converter and all the cells have the same dc voltage, the number of levels that can be achieved is 2n+1. This topology is named n-cell CHB converter and it presents great properties as a high modularity and reduced number of switches. A very interesting multilevel converter topology based on the cascaded H-bridge concept can be obtained connecting two three-level cells (called in this work 2-cell CHB) with different dc voltages. This topology is represented in Fig. 1 where the dc voltages are denoted by VA for the upper cell and VB for the lower cell respectively. The number of levels depends on the ratio of the dc voltages (VA :VB ) as can be observed in Table I. A very interesting case is obtained when the dc voltage ratio is 1:3, i.e. VB =3VA , because nine symmetrical levels are obtained using a low number of switches. The disadvantage of this topology is that, as two different dc sources are needed, the converter is not symmetrical. The modularity property, present on the symmetrical CHB topology is lost when the dc voltages are different. Usually, different power semiconductors are needed in order to build the converter, i. e. IGBTs and IGCTs are used for the lowest and highest voltage cells respectively. The switching frequency

VA0

Power Cell V SA1 VA

SA3 VOUT+

+ SA2

π

SA4

0

π

2

ωt

α0 α1 α2 α4



α3 SB3

SB1 VB

+ -

α0 ≤ α1 ≤ ... ≤ αk-1 ≤ π/2

-V

VOUTSB4

SB2

Fig. 2. Three-level pre-programmed PWM switching pattern with five switching angles (α0 ,α1 ,α2 ,α3 ,α4 ).

Fig. 1. Cascade H-bridge converter based on the series connection of two three-level power cells. TABLE I M AXIMUM AVAILABLE LEVELS IN A TWO CELLS CASCADE CONVERTER dc Values

dc Ratio

Number of levels

Symmetrical

VB = VA VA < VB < 2VA VB = 2VA 2VA < VB < 3VA VB = 3VA VB > 3VA

1:1 1:x, 1