Self-Assembly Technologies with High-Precision Chip Alignment and Fine-Pitch Microbump Bonding for Advanced Die-to-Wafer 3D Integration T. Fukushima1, Y. Ohara2, M. Murugesan1, J.-C. Bea1, K.-W. Lee1, T. Tanaka2, 3, and M. Koyanagi1 1 New Industry Creation Hatchery Center (NICHe), Tohoku University, 2 Dept. of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University 3 Dept. of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku University Email:
[email protected], Phone: +81-22-795-4119, Fax: +81-22-795-4313
We have demonstrated surface-tension-driven chip selfassembly for 3D stacking of a large number of known good dies (KGDs) on silicon substrates in batch processing. In this work, we employed small droplets of ultra-pure water as a liquid to precisely align chips having fine-pitch indium/gold microbumps with a size/pitch of 5/10 or 10/20 m. By using the self-assembly technique, these chips were aligned in a face-down configuration and flip-chip bonded onto hydrophilic bonding areas formed on silicon substrates. The hydrophilic areas are surrounded by hydrophobic areas that have above 100º in water contact angle. The wettability contrast between the hydrophilic and hydrophobic areas was found to be a key parameter to obtain high alignment accuracy. All chips having the indium/gold microbump arrays were self-assembled with high alignment accuracy of approximately 1 m or superior accuracy, and then, successfully bonded at 200 ˚C with thermal compression. The resulting resistance measured with the indium/gold daisy chain patterns was sufficiently low (< 20 m/bump) and comparable to one obtained by a conventional mechanical alignment technique.
Introduction Figure 1 illustrates several disadvantages facing conventional system in package (SiP) and system on a chip (SoC). In particular, long bonding wires used in SiP and long global wirings used in SoC are crucial issues for high-speed operation and low-power consumption in LSI. In contrast, 3D integration technologies using a huge number of very short and fine through-silicon vias (TSVs) can not only reduce the chip size but also dramatically increase signal processing speed and decrease power consumption without further scaling down device sizes. 3D integration using wafer-towafer bonding methods is a promising technology due to its high production throughput [1]-[4]. On the other hand, 3D integration using die-to-wafer bonding methods can provide high production yield due to the use of KGDs [5], [6]. However, conventional die-to-wafer 3D integration decreases production throughput because robotic pick-and-place assembly using the sequential chip stacking processes is employed. To overcome the problem, we have proposed and developed “Super Chip Integration” of a novel die-to-wafer 3D integration using self-assembly technologies with liquid surface tension by which a large number of KGDs can be simultaneously, instantly, and precisely assembled on wafers to create “3D Super Chips”, as shown in Fig.1 [7]-[12].
978-1-61284-498-5/11/$26.00 ©2011 IEEE
System in Package (SiP）
System on a Chip（SoC）
• Low wiring density • Long bonding wire • High structural limitation
• Large chip size • Long global wiring • Low design flexibility
3D-LSI MEMS / Sensor chip CMOS RF IC / MMIC Analog LSI Power IC / Control IC Logic LSI Flash memory DRAM SRAM Microprocessor
30 m
Abstract
Interposer
3D Super Chip
• • • • • • •
Metal microbump TSV
Short wire length (TSV) High wire density High-speed operation Low power consumption High design flexibility High functionality High potential application
Fig.1 Background on high research activity of 3D-LSI and introduction of “3D Super Chip”. Figure 2 introduces two types of self-assembly-based 3D integration technologies: one is reconfigured wafer-to-wafer 3D integration. The reconfigured wafer-to-wafer 3D integration involves a chip self-assembly process to a support wafer named “Reconfigured Wafer” and a batch transfer process of a chip array to an target LSI wafer. KGDs without metal microbumps are tightly bonded in a face-up configuration to the reconfigured wafer by self-assembly in the rightmost reconfigured wafer-to-wafer 3D integration we have previously reported [8], whereas KGDs with metal microbumps are just placed (not bonded) to the reconfigured wafer by self-assembly in the leftmost and cetral reconfigured wafer-to-wafer 3D integration. The KGDs having metal microbumps are transferred in batch to the faced LSI wafer having the same metal microbumps through the microbumpto-microbump bonding after self-assembly. TSVs can be formed after the chip transfer and the subsequent chip thinning. The other 3D integration is based on multichip-to-wafer stacking by which many KGDs with metal microbumps are directly self-assembled upside down to an target LSI wafer with the same metal microbump pattern in a face-to-face bonding manner, followed by heating up to eutectic temperature of the metal microbumps. After that, the selfassembled KGDs are bonded to the LSI wafer through the microbump-to-microbump interconnection with thermal compression. The most striking feature of this 3D integration is that no support wafers are required for chip stacking. In addition, various kinds of KGDs having metal microbumps,
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e.g., thick or thinned KGDs with/without TSVs, can be used for the advanced die-to-wafer 3D integration. When thinned chips with TSVs are preliminarily employed, we can skip TSV formation and thinning processes and advance additional chip stacking by self-assembly.
Reconfigured wafer-to-wafer 3D integration Microbump Liquid
Self-assembly TSV
Temporary bonding & TSV/microbump formation Reconfigured wafer Wafer alignment
In this paper, we demonstrate chip self-assembly with both high-precision chip alignment and metal microbump-tomicrobump bonding for the advanced die-to-wafer 3D integration. Many chips having arrays of indium/gold microbumps can be directly self-assembled in a flip-chip bonding manner to silicon substrates that have the same microbump array patterns. Here, we formed 5- and 10-msize and 10- and 20-m-pitch indium/gold microbumps on the many chips and substrates for the self-assembly experiments. This paper also introduces surface modification technologies to form both high hydrophilic and hydrophobic areas to precisely align KGDs, and in addition, describes the electrical characteristics obtained with the indium/gold microbump daisy chains formed between self-assembled chips and the host substrates.
Experimental The designs of indium/gold microbump arrays on chips and substrates are shown in Fig.3. Chip size is 4 mm by 5 mm and substrate size is 7 mm-square in which a hydrophilic bonding area with a size of 4 mm by 5mm was formed. The chip thickness is approximately 140 m. Bump sizes are 5- or 10-m-square and bump pitches are respectively 10 or 20 m. Two vernier patterns are located on the left and right sides of the chips and substrates for evaluating alignment performance.
LSI wafer
Chip transfer
10 or 20m
5 or 10m
Passivation Wiring In/Au microbump Contact hall
3D integration
Vernier
Advanced die-to-wafer 3D integration TSV
KGDs with Liquid microbump
Self-assembly
Vernier
5mm
LSI wafer (No support wafer) Bonding
Chip
7mm Substrate
Bonding area (hydrophilic)
Fig.3 Designs of chips and substrates with indium/gold microbump arrays used in this study.
LSI wafer
Thick chip Thick chip Thin chip Thin chip w/o TSV with TSV w/o TSV with TSV Microbump Chip Chip TSV thinning thinning formation formation Microbump Microbump TSV formation formation formation Microbump formation
7mm
4 mm
Surrounding area (hydrophobic)
3D integration
Fig.2 A category of self-assembly-based 3D integration called “Super Chip Integration”.
Figure 4 shows process flows for the fabrication of chips and substrates with indium/gold microbump arrays. First, Al/W wirings were formed on thermally oxidized wafers by sputtering, photolithography, and RIE. Then, a plasma-TEOS (tetraethylorthosilicate) oxide layer was deposited by CVD on the Al/W wirings, followed by contact hole formation by RIE. After that, metal microbumps consisting of 3-m-thick indium and the following 0.3-m-thick gold were formed by our unique lift-off technique with RIE and evaporation [13]. The region around chip bonding areas was rendered hydrophobic by a coating technique with a fluorocarbon material. Finally, the chips were obtained by mechanical dicing with a ceramic blade. Figure 5 shows a process flow for the self-assembly of chips to substrates using liquid surface tension. First, 2-l droplets of water were provided onto hydrophilic bonding
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areas formed on substrates, and then, the 4-mm-by-5-mm chips were roughly prealigned upside down to the bonding areas. Immediately after chip release, the chips were precisely aligned onto the bonding areas by liquid surface tension as a driving force. After liquid evaporation at room temperature, the surface-tension-driven chips were bonded to the wafers with thermal compression at 200ºC.
Cross-sectional view
3. Al mask formation & In/Au evaporation
Chip
1) Immediately after chip release
Thermal SiO2 P-TEOS SiO2
In/Au (t = 3m/0.3m) 3) 0.10 sec after chip release
Fig.6 Video frames from a short movie of chip self-assembly taken with two high-speed cameras.
4. Lift-off
(a) 5. Hydrophobic treatment
Chip
Substrate
Fluorocarbon
Alignment accuracy (m)
5. Dicing
Fig.4 Process flows for the fabrication of chips and substrates with indium/gold microbump arrays.
Oxide
Tweezers
2) 0.02 sec after chip release
Al hard mask Lift-off resist
Chip
Hydrophobic area
Hydrophilic bonding area
Al/W wire (t = 1m/50nm)
2. SiO2 passivation & contact hole formation
Top view
Hydrophobic area
Wiring In/Au microbump Hydrophobic area
Hydrophilic area
(b) 10 9 8 7 6 5 4 3 2 1 0
Liquid volume: 0.2 l/mm2 * 0.02 l/mm2 of liquid was used for the 5-mm-square chips.
Liquid volume (l) 0.20 / 0.45 / 0.80 / 1.25 / 1.80 / 0.50*
0 0.5 1.0 1.5 2.0 2.5 3.0 5.0 Side length of square chips (mm)
Alignment accuracy (m)
1. Al/W wiring formation
gravitational forces acting on the chips. On the other hand, initial misalignment (X, Y, and directions) before chip release would not strongly affect the alignment accuracy.
10 9 8 7 6 5 4 3 2 1 0
Chip size: 3 × 3 mm
0 0.5 1 1.5 2 2.5 3 3.5 Liquid volume (l)
Fig.7 Dependence of alignment accuracy on chip side length (a) and liquid volume (b).
Liquid Substrate Chip release
Self-assembly
Thermal compression
Fig.5 A process flow for the self-assembly of chips to substrates using liquid surface tension.
Capability of Chip Self-Assembly Technologies Using Surface Tension of Water In this section, we introduce potential capability of our self-assembly technologies. Figure 6 shows video frames from a short movie of chip self-assembly taken with two high-speed cameras. As seen from Fig.6, a chip is intentionally misaligned in X, Y, and directions prior to chip release, however, the chip is driven by the surface tension of water and then precisely aligned to the hydrophilic bonding area within 0.1 sec. Figure 7 shows dependence of alignment accuracy on chip size and liquid volume. The left figure shows chip size effects and the right figure shows liquid volume effects. When chips ranging in size from 1 mm to 5 mm are employed, alignment accuracy is very high in any case. Liquid volume hardly effects on alignment accuracy, but excess liquid volume tends to largely decrease alignment accuracy. Figure 8 shows the dependence of alignment accuracy on the tilt angle of silicon substrates wafers. High alignment accuracy was obtained with the wafer tilt angle of less than 0.1º. When the tilt angle was 0.3º, however, the alignment accuracy remarkably decreased due to the
Fig.8 Dependence of alignment accuracy on wafer tilt angle.
Investigation on Wettability Contrast for High Alignment Accuracy Photomicrographs of the resulting chip and substrate with indium/gold microbump arrays are shown in Fig.9(a) and an image of a part of the resulting 20-m-pitch indium/gold microbump array taken with a laser microscope is shown in Fig. 9(b). The resulting bump height was approximately 3.3 m. Figure 10 shows a schematic of self-assembly phenomena on aligning of chips to low or high hydrophilic bonding areas. The chips are precisely aligned to the bonding areas when wettability contrast between hydrophilic bonding areas and the surrounding hydrophobic areas is high. On the other hand, the chips result in alignment failure in the case of low
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wettability contrast. High hydrophobic surrounding areas can confine the water droplets to the center of hydrophilic bonding areas, leading to high alignment accuracy. However, the contact angle of the resulting hydrophilic bonding areas was nearly 80º, whereas the contact angle of the surrounding hydrophobic areas was around 110º, which means wettability contrast (~30º) is low. To dramatically increase the wettability contrast without lowering hydrophobic properties on the surrounding areas, we studied a selective hydrophilization technology for only increasing the hydrophilic property on the bonding areas. By using a unique selective hydrophilization technology of mask-less batch processing, we can provide high wettability contrast between hydrophilic bonding areas and the hydrophobic surrounding areas. Figure 11 shows relationship between the selective hydrophilization time and contact angle on both bonding areas and the surrounding areas. The contact angle of the resulting hydrophilic bonding areas was less than 20º, whereas the contact angle of the surrounding hydrophobic areas was more than 100º, which has high potential to precisely align chips to substrates because water droplets are strongly confined to the central bonding areas.
(a)
increased with an increase in wettability contrast. Wettability contrast indicating a difference in water contact angle between bonding areas and the surrounding areas was kept at above 80º that is enough to give high alignment accuracy, as shown in Fig.12. Actually, chips were precisely aligned to hydrophilic bonding areas by water surface tension. The resulting alignment accuracy observed from verniers on the surface both chips and host substrates was found to be 0.1 m in X direction, as shown in Fig.13. From the self-assembly experiments, it was noted that alignment accuracy intensively depends on wettability contrast between hydrophilic bonding areas and the surrounding hydrophobic areas. (a) High contrast Chip
Substrate
(b) Low contrast Chip
Successful alignment Bonding area (hydrophilic) Surrounding area (hydrophobic)
Substrate
Chip
Substrate
4 mm
7 mm
Alignment failure
Fig.10 A schematic of chip self-assembly phenomena when wettability contrast between hydrophilic bonding areas and the surrounding hydrophobic areas is high (a) and low (b).
5 mm 7 mm (b)
In/Au microbump Wiring Passivation
7 m 3 m 50 25 0 0
25
50
75 m
Fig.9 Photomicrographs of the resulting chip and substrate with indium/gold microbump arrays (a), an image of a part of the resulting 20-m-pitch indium/gold microbump array by a laser microscope (b).
Fig.11 Relationship between selective hydrophilization time and contact angle on both bonding areas and the surrounding areas.
By controlling the time of selective hydrophilization treatment, the chips are self-assembled to the substrates: they have the small-size and fine-pitch indium/gold microbumps on their surface. Figure 12 shows dependence of alignment accuracy on wettability contrast between bonding areas and the surrounding areas. The alignment accuracy dramatically
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was successfully formed on the substrate. I-V characteristics measured using the daisy chain patterns with 5- and 10-msize and 10- and 20-m-pitch microbumps were investigated. Table 1 shows comparisons of the resulting chain resistance per a pair of two bonded indium/gold microbumps between self-assembly and conventional flip-chip assembly. As shown in Table 1, we have confirmed that chain resistance of the indium/gold daisy chains resulted from the chips bonded with self-assembly was almost the same to one obtained by conventional mechanical flip-chip bonding. The daisy chains obtained with 5-m-size/10-m-pitch and 10-m-size/20-mpitch indium/gold microbumps showed approximately 18 and 160 m/bump in chain resistance. (a)
In/Au microbump
Al/W wiring 5m
(b)
Fig.12 Dependence of alignment accuracy on wettability contrast between bonding areas and the surrounding areas. 5mm
10m
Left side vernier
Fig.14 Cross-sectional images of indium/gold microbumps before (a) and after (b) self-assembly and the following thermal compression. Table 1 The resulting chain resistance of indium/gold microbumps between self-assembly and mechanical assembly.
Right side vernier
Alignment accuracy
X axis： 0.1 m
Y axis： 1.3 m
θ axis： 0.017º
Fig.13 A photomicrograph of self-assembled dies on a substrate and IR images of the resulting representative vernier patterns.
Electrical Characteristics of Self-Assembled Chips with Indium/Gold Microbump Arrays Thermal compression of precisely aligned chips by selfassembly to substrates gave flip-chip interconnections with the metal microbump-to-microbump bonding. Figure 14 shows cross-sectional images of the resulting daisy chain pattern with indium/gold microbumps before and after selfassembly and the following thermal compression at 200ºC. It was clearly seen from the Fig.14(b) that indium/gold microbumps are tightly bonded each other and the daisy chain
Size/pitch
5/10(m)
10/20(m)
Self-assembly
164 mΩ/bump
17.8 mΩ/bump
Conventional flip-chip assembly
208 mΩ/bump
15.2 mΩ/bump
By using the self-assembly techniques, large chips with a side length of 20 mm can be precisely aligned to wafers as shown in Fig.15(a). In addition, chips having cavity structures can be also self-assembled to substrates. The former selfassembly is toward 3D stacking of microprocessors and silicon interposer chips. The latter self-assembly is targeting for MEMS chips and passive device chips such as coils [12]. The self-assembly technologies will be applicable to 3D and hetero integration based on advanced die-to-wafer stacking in batch processing and in high yield. Our self-assembly researches are further investigated for the creation of “3D Super Chips”.
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Top view
(a)
(b)
Top view
[4]
Cross-section Liquid
20 mm
[5]
3 mm Liquid supply
Liquid supply
[6]
Liquid wetting Cavity chip
[7]
Tweezers
Chip release
0.09 sec after release
Chip release
[8]
0.16 sec after release
0.1 sec after release
[9]
Fig.15 Self-assembly of a large chip (a) and a chip having a cavity structure (b).
Conclusions A novel die-to-wafer 3D integration using self-assembly called “Super Chip Integration” has been developed. Millimeter-scale chips having indium/gold microbump arrays with bump pitches of 10 and 20 m were precisely selfassembled to substrates having the same indium/gold microbump arrays. High wettability contrast more than 80º provide very high alignment accuracy of within 1 μm by the surface tension of water. Compared with the I-V characteristics of the indium/gold microbump daisy chains resulted from conventional flip-chip bonding, the selfassembly method showed as low chain resistance as the mechanical alignment. The self-assembly technology can significantly increase production yield and throughput with high alignment accuracy for die-to-wafer 3D integration. Acknowledgments This work was performed in the Micro/Nano-machining research and education Center (MNC) and Jun-ichi Nishizawa Research Center at Tohoku University. This research was supported from 2010 to 2011 by Japan Society for the Promotion of Science (JSPS), Grant-in-Aid for Scientific Research "Grantin-Aid for Scientific Research (S)", No. 21226009. References [1] M. Koyanagi, “Roadblocks in Achieving ThreeDimensional LSI”, Proc. 8th Symposium on Future Electron Devices, pp. 55-60 (1989). [2] M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, and H. Itani “Future System-on-Silicon LSI Chips”, IEEE Micro, 18, pp. 17-22 (1998). [3] M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, “ThreeDimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections”, IEEE Trans. Electron Devices, 53, pp. 2799-2808 (2006).
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[10]
[11]
[12]
[13]
M. Koyanagi, T. Fukushima, and T. Tanaka, “HighDensity Through Silicon Vias for 3-D LSIs”, Proc. IEEE, 97, pp. 49-59 (2009). A. Klumpp, R. Merkel, P. Ramm, J. Weber, and R. Wieland, “Vertical System Integration by Using InterChip Vias and Solid-Liquid Interdiffusion Bonding”, Jpn. J. Appl. Phys., 43, L829-L830 (2004). T. Fukushima, Y. Yamada, H. Kikushi, and M. Koyanagi, “New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration”, Jpn. J. Appl. Phys., 45, pp. 3030-3035 (2006). T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, “New Three-Dimensional Integration Technology Using Self-Assembly Technique”, IEDM Tech. Dig., pp. 359362 (2005). T. Fukushima, H. Kikuchi, Y. Yamada, T. Konno, J. Liang, K. Sasaki, K. Inamura, T. Tanaka, and M. Koyanagi, “New 3D Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique”, IEDM Tech. Dig., pp. 985-988 (2007). T. Fukushima, T. Konno, K. Kiyoyama, M. Murugesan, K. Sato, W.C. Jeong, Y. Ohara, A. Noriki, S. Kanno, Y. Kaiho, H. Kino, K. Makita, R. Kobayashi, C.K. Yin, K. Inamura, K.W. Lee, J.C. Bea, T. Tanaka, and M. Koyanagi, “New Heterogeneous Multi-Chip Module Integration Technology Using Self-Assembly Method”, IEDM Tech. Dig., pp. 499-502 (2008). T. Fukushima, E. Iwata, Y. Ohara, A. Noriki, K. Inamura, K.W. Lee, J.C. Bea, T. Tanaka, and M. Koyanagi, “ThreeDimensional Integration Technology Based on Reconfigured Wafer-to-Wafer and Multichip-to-Wafer Stacking Using Self-Assembly Method”, IEDM Tech. Dig., pp. 349-352 (2009). T. Fukushima, E. Iwata, T. Konno, J.C. Bea, K.W. Lee, T. Tanaka, and M. Koyanagi, “Surface Tension-Driven Chip Self-Assembly with Load-Free Hydrogen FluorideAssisted Direct Bonding at Room Temperature for ThreeDimensional Integrated Circuits”, Appl. Phys. Lett., 96, 154105 (2010). T. Fukushima, T. Konno, E. Iwata, R. Kobayashi, T. Kojima, M. Murugesan, J.C. Bea, K.W. Lee, T. Tanaka, and M. Koyanagi, “Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration”, Micromachines, 2, pp. 49-68 (2011). T. Matsumoto, Y. Kudoh, M. Tahara, K.-H. Yu, N. Miyakawa, H. Itani, T. Ichikizaki, A. Fujiwara, H. Tsukamoto, and K. Koyanagi, “Three-dimensional integration technology based on wafer bonding technique using micro-bumps”, Proc. SSDM, pp. 1073-1074 (1995)
