of semiconductor manufacturing as well as material properties and device behavior since the first integrated circuit appeared. From this time, a proliferation of ...
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO. 2, MAY 2000
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EST structures have been used to evaluate many aspects of semiconductor manufacturing as well as material properties and device behavior since the first integrated circuit appeared. From this time, a proliferation of measurement techniques, test structure designs, and data interpretation and data analysis methods have evolved, with them becoming more important as the development of high-density and high-performance VLSI circuits continues. Many of these developments are now reported at the IEEE International Conference on Microelectronic Test Structures (ICMTS). This meeting focuses on test structures for material and process characterization, reliability and product failure analysis, wafer fabrication process control, device and circuit modeling, replicated features metrology, new sensors and devices, as well as measurement methods and utilization strategies. This issue of IEEE TRANSACTIONS OF SEMICONDUCTOR MANUFACTURING contains a special section devoted to progress in microelectronic test structures. The papers published are based on recent presentations made at the ICMTS held in Göteborg, Sweden, on March 16–18, 1999. Initially, 59 papers were submitted from 21 countries, and of these, 43 were selected for oral and poster presentation. This is the seventh special issue that has been devoted to the ICMTS, and this year, eight papers have been selected for wider dissemination in the semiconductor manufacturing community. The papers presented in this issue cover a broad spectrum of test structure research, including the development of new structures and measurement procedures. Papers on test structure development include a thermal van der Pauw test structure for measuring in-plane thermal sheet conductivities of thin films. Another paper evaluates four different test structures for inter-
Publisher Item Identifier S 0894-6507(00)03621-6.
connect reliability control. In order to characterize mask misalignment, some new null holographic test structures are presented. Using these test structures, overlay and its statistical variation has been investigated. A very dense hexagonal transistor structure with excellent matching properties is suggested for use in high-speed applications in which both good matching and the small device area are demanded. Finally, the last two papers suggest an improved method for determining the emitter and base series resistances of bipolar transistors from one single dc measurement and a simple and efficient method for characterizing the capacitance matrix of multilayer VLSI interconnects. The above papers provide a flavor of the types of papers presented at ICMTS, and for those with further interest in microelectronic test structures, many more interesting papers are in the conference proceedings (which are available from the IEEE). We would both like to thank all of the authors for their efforts in preparing extended manuscripts of their conference presentations and for their admirable job in responding to the criticism of the reviewers (and in keeping with the sometimes very tight deadlines). They would also like to thank the reviewers for the time they devoted in reviewing the submitted manuscripts and for their valuable comments. Last but not least, they would like to thank the editor, Dr. G. May, and his assistant, D. Bush, for their assistance and guidance through the IEEE TSM review procedure.
KJELL O. JEPPSON, Guest Editor Chalmers University of Technology Göteborg, Sweden ALAN MATHEWSON, Guest Editor National Microelectronics Research Center (NMRC) Cork, Ireland
Kjell O. Jeppson (S’68–SM’76–SM’83) received the Ph.D. degree in solid-state electronics from Chalmers University of Technology, Göteborg, Sweden, in 1977. He became Senior Lecturer at the Department of Solid-State Electronics in 1978. Since 1996, he has been a Professor at the Department of Microelectronics. He spent the academic year 1973–1974 with Rockwell International, Anaheim, CA, and the fall semester 1985 at the Southampton University Microelectronics Centre, U.K. His main research interest is focused on MOS and bipolar device modeling and parameter extraction, and CMOS VLSI design. He has published several papers on MNOS nonvolatile memories, transistor modeling and parameter extraction, CMOS gate delay, and hierarchical DRC of VLSI circuits. He has also authored a textbook (in Swedish) on semiconductor devices. Since 1993, he has been Vice Dean, responsible for the undergraduate school of electrical engineering, for which he has initiated the E-96 project for implementation of a new undergraduate curriculum. In 1999, he was General Chairman for the International Conference on Microelectronic Test Structures (ICMTS’99). 0894–6507/00$10.00 © 2000 IEEE
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Alan Mathewson (M’96–SM’97) graduated from the University of Newcastle (U.K.) in 1978. He is an Assistant Director of the Irish National Microelectronics Research Centre and Director of the Technology Characterization and Modeling Group in that institute. He is responsible for work on the characterization of advanced industrial MOS and bipolar technologies and is involved in technology development for advanced process technology modules. He worked for Plessey Research (Caswell) and Racal Research Limited in the U.K. until 1982 when he joined the NMRC. Since then he has been responsible for technology development and device characterization issues in the centre. His major research interests include numerical process and device simulation, reliability characterization and modeling, as well as the extraction of models for interconnect and transistor behavior for use in circuit simulation. He has published approximately 180 journal and conference papers on many aspects of silicon technology. Dr. Mathewson is a member of SPIE.
