SiGe W-CDMA transmitter for mobile terminal application - IEEE Xplore

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 9, SEPTEMBER 2003

SiGe W-CDMA Transmitter for Mobile Terminal Application Duljit S. Malhi, Member, IEEE, Lawrence E. Larson, Fellow, IEEE, Dawn Wang, Cuneyt Demirdag, and Victoria Pereira

Abstract—This paper presents the design considerations and experimental results of a transmitter integrated circuit (IC) for wide-band code division multiple access (W-CDMA) mobile terminal application based on a superheterodyne architecture. Implemented by utilizing IBM’s 0.5- m SiGe BiCMOS technology, the transmitter IC consumes approximately 270 mW with a 3.0-V power supply. The radio-frequency IC features a third-order output intercept point (OIP3) of 25.0 dBm, a 95-dB dynamic range, and 6.3% error vector magnitude.

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Index Terms—Automatic gain control, baluns, error vector magnitude, wideband code division multiple access (W-CDMA).

I. INTRODUCTION

W

IRELESS communication is evolving rapidly from low-bit-rate voice services to high-bit-rate multimedia applications. Internet access and video and picture transfer services are key drivers. These applications require a few tens of kilobits per second to approximately 2 Mb/s data rate. Thus, the capability targets for the third-generation (3G) cellular system have been defined as 144 kb/s for high-speed vehicular traffic, 384 kb/s for pedestrian or low-speed vehicular traffic, and 2 Mb/s for indoor offices and/or local wireless loops. The standardization of the 3G cellular systems [1] is quite mature and systems are in deployment state. The systems are known as UMTS or IMT-2000. In Europe and Japan, the wide-band code-division multiple-access (W-CDMA) scheme has been adopted as the air interface [2]–[3]. The W-CDMA mobile terminals or User Equipment (UE) Power Class 3 are targeted for a maximum transmission power of 24 dBm and a minimum of 50 dBm power levels at the antenna, which translates into 74 dB of dynamic range. To account for manufacturing processes, operating temperature, and power supply variation, extra margin in the dynamic range is essential. At the antenna, the adjacent channel leakage ratio (ACLR), which determines how much of the mobile terminal’s transmitted power is

Fig. 1.

Block diagram of W-CDMA transmitter.

allowed to leak into the first adjacent (5-MHz) and second adjacent (10-MHz) channel, is 33 and 43 dBc, respectively, until the noise floor is reached. The maximum rms error vector magnitude (EVM) allowed, as per 3GPP specifications [1] for complete transmitter chain at antenna is 17.5% at all output power levels greater than 20 dBm. The EVM below 20 dBm of output power is not well defined in 3GPP documents. A maximum of 9.5% rms EVM is budgeted for this integrated circuit (IC). The EVM is a measure of modulation accuracy in the transmit chain, and is dominated by performance characteristics of the modulator, phase-locked loop (PLL) phase noise and modulator is at the RF driver/power amplifier. Since the beginning of the transmit chain, its characteristics, such as low noise floor, unwanted sideband suppression, and carrier leakage, are the key design challenges for this IC. Carrier leakage and sideband suppression better than 35 dBc over process, temperature, and power-supply excursion are key parameters for good EVM. 3GPP ACLR mask, transmit (TX) and receive (RX) band spurs, regional requirements, and the required noise floor set the limits for emission at all critical output power levels. II. ARCHITECTURE AND CIRCUIT DESIGN A. Architecture

Manuscript received November 18, 2002; revised April 10, 2003. D. S. Malhi was with TriQuint Semiconductor, Lowell, MA 01854 USA. He is now with Synopsys, Mississauga, ON L5B 1M2, Canada (e-mail: [email protected]). L. E. Larson is with the Center for Wireless Communications, Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA (e-mail: [email protected]). D. Wang was with IBM, Lowell, MA 01852 USA. She is now with TriQuint Semiconductor, Lowell, MA 01854 USA. C. Demirdag was with IBM, Lowell, MA 01852 USA. He is now with Kenet, Inc., Reading, MA 01867 USA. V. Pereira was with IBM, Lowell, MA 01852 USA. She is now with Northrop Grumman, Palm Harbor, FL 34683 USA. Digital Object Identifier 10.1109/JSSC.2003.815908

Fig. 1 shows the block diagram of the highly integrated dual upconversion W-CDMA transmitter. It consists of a balanced modulator, an IF variable gain amplifier (VGA), upconverter, an RF VGA, and a driver amplifier. Off-chip IF and RF matching networks are used to improve out-of-band spurs and noise. B. I/Q Modulator modulator core is shown in A block diagram of the Fig. 2. It is based on a double-balanced BiCMOS Gilbert-cell

0018-9200/03$17.00 © 2003 IEEE

MALHI et al.: SiGe W-CDMA TRANSMITTER FOR MOBILE TERMINAL APPLICATION

Fig. 2.

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Schematic of BiCMOS I=Q modulator core. Fig. 3.

mixer architecture where balanced baseband inputs are fed into high-impedance nFET differential pairs (N1–N2 and N3–N4). The upper quads of two mixers, which consist of SiGe heterojunction bipolar transistors (HBTs) (Q1–Q8), are differential and are driven by 90 out-of-phase local oscillator (LO) signals. Both mixers are biased via a bandgap, supplying temperature and power-supply independent reference current to the nFET (N5–N8) current sources. A combination of n-p-ns and field-effect transistors (FETs) are used to enhance and optimize noise and linearity performance for low current consumption. The mixers’ outputs are summed via two resistors (R1–R2). The LO input signal (760 MHz) is single-ended and converted to a differential signal through a differential pair. One end of the pair is tied to external LO signal and other is connected to ground via a 10-pF on-chip capacitor. The differential LO signal is first multiplied by a low-noise low-power frequency-tuned doubler, as shown in Fig. 3. HBTs and stacked inductors are used to The high simultaneously achieve high linearity and low noise for low power dissipation [4]. Two 3.3-nH stacked inductors (L1–L2) of 110 110 m and two capacitors (C1–C2), each 1 pF, are used to bias and frequency tune the doubler, as shown in Fig. 3. Stacked multilayer inductors reduce the inductor area by approximately 50%, compared with a traditional planar inductor [5]. These stacked inductors maintain a moderate quality factor of 5 within the operating frequency range. The capacitive coupled signal then drives a divide-by-four to generate 90 out-of-phase quadrature IF carrier (380-MHz) signals. Asymmetrical latches are used to construct a very lownoise-floor (i.e., 160 dBm/Hz) divide-by-four, as shown in Fig. 4. Since the divide-by-four has a feedback path and asymmetrical current latches, this aids in increasing driving level and reducing total integrated switching time, which reduces the noise contribution. C. IF VGA The IF VGA is a five-stage cascaded differential amplifier with more than 80 dB of linear gain-control range [6]. Linear-in-dB gain control allows low current digital-to-analog converters (DACs) to use the full available gain range. An output 1-dB compressor point (P1dB) of 1.5 dBm with total

Schematic of frequency doubler.

Fig. 4. Diagram of D-type flip-flop with asymmetrical latches.

current consumption of 25 mA is achieved by employing components and LC matching off-chip high quality factor network to the open collector output of the IF VGA. The ) LC matching network is output high quality factor ( utilized to construct a bandpass filter, which also serves as an input matching network for the following stage. S-parameter measurements show the bandwidth of the filter to be approximately 80–100 MHz with center frequency at 380 MHz. This arrangement helps to achieve 30-dBc suppression of third harmonic ( 1140 MHz) with reference to desired signal. Usable dynamic range better than 80 dB is also achieved while maintaining the minimum ACLR (5-MHz offset) requirement of 55 dBc over the entire available dynamic range. This stringent requirement of 55 dBc ACLR (5-MHz offset) is set modulator and IF VGA block to meet the for the cascaded 33-dBc requirement at the antenna. D. RF Upconverter The RF upconverter is a doubly balanced Gilbert-style mixer with a resistive degeneration and capacitive feedback in the lower differential pair to achieve the desired third-order intercept point (IP3) and noise figure (NF). The IF and LO inputs and RF outputs are reactively tuned to the desired center frequencies to improve the out-of-band spur rejection and lower power consumption. The balanced output of the mixer is converted to single ended by reactively tuned on-chip 4:1 planar transformer. The transformer is designed by utilizing two

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0.0 dBm, respectively. The LO-to-RF, IF-to-RF, and LO-to-IF isolations are 34, 32, and 60 dB, respectively. E. RF VGA

Fig. 5. Layout of cross-coupled planer transformer.

RF amplification and variable gain function at 1.95 GHz is performed with a class-A VGA. The single-stage VGA is based on current-steering architecture for gain control. It is temperature and process compensated and offers 30-dB gain-control range and 18 dB of gain. It consumes only 28 mA while providing 7 dBm output P1dB and 5-dB NF. Open collectors of the RF VGA allow greater off-chip and on-chip matching flexibility to improve linearity, gain, and single-ended or differential operation. In this particular version of the transmitter, an off-chip RF transformer is used to convert balanced outputs to unbalanced signal. This off-chip flexibility helps in controlling cascaded performance in optimizing the first iteration of the integrated design. F. Class-AB Driver

Fig. 6. Lumped model of planer 4:1 transformer.

pairs of tightly coupled inductors, one of which is connected in series and other in parallel to achieve a 4:1 inductance ratio. It is necessary to use capacitive tuning to minimize the insertion loss of the transformer. The transformer has minimum insertion loss when used for a 4:1 impedance transformation ratio, but can be used for higher or lower impedance ratios with increased insertion loss [5], [7]. Due to the true differential nature of both the input and output ports, it allows us to interface differentially with an off-chip LC bandpass filter or single-ended, whichever provides optimum performance. The layout of the each tightly coupled pair of inductors (half transformer) has a size of 266 266 m . The full transformer is shown in Fig. 5. To achieve 3-dB insertion loss, 4- m-thick 10- m-wide top-level metal is used to design the coupled inductors and a thin lower metal layer is used for the underpass. The lumped model of the complete transformer is shown in Fig. 6. All four tightly coupled inductors (L1–L4) and corresponding resistors (R7–R10), which determine the quality factor of individual inductors, carry the same value. C7 and C8 are coupling capacitors between the tightly coupled inductors. Capacitors C1–C6 and resistors R1–R6 represent substrate loss. The coupling coefficients, represented by K1 and K2, are approximately 0.7 for this transformer. The mixer core and LO buffer are precisely biased by an on-chip bandgap circuit and off-chip precision resistor to tailor the bias current to achieve optimum overall performance. The measured conversion gain, NF, and output P1dB over process, temperature, and power-supply variation are within 5% of nominal values, which are 3, 11, and

The class-AB driver is a single-ended single-stage commonemitter amplifier with C-B negative feedback for improved stability and linearity. The Class-AB design was chosen to achieve high linearity and low noise for minimum bias current of 16 mA. ) high-linearity SiGe HBTs [8], [9] are High-breakdown ( used to achieve very high linearity for low quiescent current consumption. The driver provides 14-dB gain, 4-dB NF, and 15-dBm output P1dB while consuming only 16 mA of quiescent current at 7-dBm output power. Again, the open collector design allows higher low-loss off-chip matching. It also provides an added flexibility in optimizing power gain and ACLR for an optimum performance interface with the high-power amplifier (HPA). This amplifier has a gain variation of less than 2 dB over process and 1 dB over temperature and supply voltage, permitting manufacturing to take place with no expensive tuning or calibration. III. EXPERIMENTAL RESULTS A transmitter IC for W-CDMA mobile terminal application was implemented using IBM 0.5- m SiGe BiCMOS production technology. This technology offers dual breakdown SiGe HBTs and CMOS devices as well as planar inductors. Custom stacked inductors and transformers are developed to implement high-density integrated RF circuits with optimum performance. A photomicrograph of the chip is shown in Fig. 7. The active area of the IC is 2.54 mm 2.54 mm and is compatible for a 32-pin exposed-paddle BCC32++ or QFN32 package. Measurements of individual building blocks and fully cascaded TX chains were performed. The total power dissipation of approximately 270 mW was achieved with a 3.0-V typical voltage supply. The IF LO was chosen at a fixed frequency of 760 MHz and the RF LO was varied from 1540 to 1600 MHz. Both continuous-wave (CW) and hybrid phase shift keying (HPSK) modulated input signals were used to characterize the TX IC for dynamic range, linearity, noise, spurs, and EVM. An input sine-wave signal of 500 kHz frequency with varied input voltage swing (i.e., typical 1.0 V differential) was used to

MALHI et al.: SiGe W-CDMA TRANSMITTER FOR MOBILE TERMINAL APPLICATION

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Fig. 9. Modulated output power versus ACLR.

Fig. 7. Photomicrograph of chip.

Fig. 10.

Fig. 8. Measured adjacent and alternate channel characteristics for output power.

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measure the input and output P1dB and dynamic range of the integrated IC. Cascaded input P1dB of 4.0 V differential and output P1dB of 15 dBm was measured. signal of 1.3 V difThe typical HPSK modulated input ferential with a peak-to-average ratio of multimode transmission of approximately 6 dB, as well as a chip rate of 3.84 MHz and ) was used to measure ACLR, ACLR a Kaiser window ( mask, and EVM. The close-in or TX band noise floor is specified in the spectrum emission mask. Fig. 8 shows the detailed ACLR measurement as per 3GPP requirements for an output of 7 dBm at 5 MHz and 10-MHz offset. The CW measurement also shows that the TX and RX band noise floor is less than 130 dBm/Hz and 150 dBm/Hz, respectively. The TX band noise floor improves as the output power levels are reduced. The RX band noise floor remains constant over the whole dynamic range. Fig. 9 shows the modulated output power of TX IC versus ACLR at 5-MHz offset for both up and down channels. It can be seen that the ACLR of 49 dBc for 7-dBm modulated power can be achieved at 5-MHz offset. It is well above the minimum

Measured HPSK constellation for output power of

+7 dBm.

requirement of 33 dBc at the antenna for the complete transmitter including the HPA stage. The Advantest R3267/73 test setup was used to analyze constellation and EVM characteristics. The measured worst case EVM is less than 6.3%, which is sufficiently small to satisfy the 9.5% budgeted for this IC. The constellation plot of HPSK modulated signal is shown in Fig. 10. IV. CONCLUSION A highly integrated and production RF transmitter IC designed in IBM’s 0.5- m SiGe BiCMOS process has been presented for W-CDMA applications satisfying or exceeding all 3GPP requirements. For a typical output modulated power of 7 dBm, 49-dBc ACLR at 5-MHz offset, TX band noise floor of 141 dBm/Hz at 8.5-MHz offset for low output power levels, RX band noise floor of 144 dBm/Hz for all output signal levels, and rms EVM of 6.3% are achieved. The IC consumes 270 mW of total power for 3.0-V typical voltage supply. ACKNOWLEDGMENT The authors would like to thank Dr. K. Itoh, H. Joba, Y. Matsunami, S. Shinju, and Dr. N. Suematsu of Mitsubishi

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Electric Corporation for their contributions and for many valuable discussions. They would also like to thank G. Lindsay and S. Simmers for layout, L. Prestia, R. Festa, S. McGoldrick, and M. Deering for measurements, B. Mangla and his team for manufacturing support, and J. Ardizzoni for application notes.

REFERENCES [1] The 3rd Generation Partnership Project. (1998–2003). [Online]. Available: http://www.3gpp.org [2] E. Dahlmann, P. Beming, J. Knutsson, F. Ovesgo, M. Persson, and C. Roobol, “W-CDMA—The radio interface for future mobile multimedia communications,” IEEE Trans. Veh. Technol., vol. 47, pp. 1105–1118, Nov. 1998. [3] L. B. Milstein, “Wideband code division multiple access,” IEEE J. Select. Areas Commun., vol. 18, pp. 1344–1354, Aug. 2000. [4] D. Wang, K. Krishnamurthi, S. Gibson, and J. Brunt, “A 2.5-GHz low noise high linearity LNA/Mixer IC in SiGe BiCMOS technology,” in IEEE Radio Frequency Integrated Circuit Symp. Dig. Papers, May 2001, pp. 249–252. [5] L. Tao, J. Gillis, D. Wang, and P. Cooper, “Design and modeling of compact on-chip transformer/balun using multi-level metal winding for RF integrated circuits,” in IEEE Radio Frequency Integrated Circuit Symp. Dig. Papers, May 2001, pp. 117–120. [6] H. Joba, Y. Takahashi, Y. Matsunami, K. Itoh, S. Shinjo, N. Suematsu, D. S. Malhi, D. Wang, K. Schelkle, and P. Bacon, “W-CDMA SiGe TX-IC with high dynamic range and high power control accuracy,” in IEEE Radio Frequency Integrated Circuit Symp. Dig. Papers, June 2002, pp. 27–30. [7] J. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368–1382, Sept. 2000. [8] G. Niu, Q. Liang, J. D. Cressler, C. S. Webster, and D. L. Harame, “RF linearity characteristics of SiGe HBT’s,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 1558–1565, Sept. 2001. [9] S. Shinjo, K. Mori, H. Joba, and N. Suematsu, “Low quiescent current mirror type self bias control circuit,” in Proc. Eur. Microwave Conf., vol. 3, 2001, pp. 207–210.

Duljit S. Malhi (M’01) received the B.Sc. and M.Sc. degrees from the University of Delhi, Delhi, India, in 1979 and 1981, respectively, the M.Tech. degree from the Indian Institute of Technology, Delhi, in 1983, and the M.A.Sc. degree in electrical engineering from the University of Toronto, Toronto, ON, Canada, in 1991. From 1990 to 1999, he was with Nortel Networks, Ottawa, ON, as a Senior Member of Scientific Staff working on the design of various analog and digital integrated circuits in various internal and external Si and SiGe BiCMOS technologies for their application in optical and wireless networks. From 1999 to 2003, he was with IBM and its divestiture TriQuint Semiconductor, where he built various RF and mixed-signal integrated circuits for their application in third-generation (3G) wireless handsets. He is currently with Synopsys, Mississauga, ON, as a Senior R&D Engineer. He has published over 14 research papers in various IEEE journals and conferences and has received four U.S. patents. His current research interests include building RF and mixed-signal systems-on-chip for wireless and wireline applications.

Lawrence E. Larson (S’82–M’86–SM’90–F’00) received the B.S. and M. Eng. degrees in electrical engineering from Cornell University, Ithaca, NY, in 1979 and 1980, respectively, the Ph.D. degree in electrical engineering and MBA degree from the University of California at Los Angeles in 1986 and 1996, respectively. From 1980 to 1996, he was with Hughes Research Laboratories, Malibu, CA, where he directed the development of high-frequency microelectronics in GaAs, InP, Si/SiGe, and MEMS technologies. He joined the faculty of the University of California at San Diego (UCSD), La Jolla, in 1996, where he is the Inaugural Holder of the Communications Industry Chair. He is currently Director of the UCSD Center for Wireless Communications. During the 2000–2001 academic year, he was on leave with IBM Research, San Diego, where he directed the development of RFICs for third-generation applications. He has published over 150 papers, coauthored three books, and holds 25 U.S. patents. Dr. Larson was the recipient of the 1995 Hughes Electronics Sector Patent Award for his work on RF MEMs, a corecipient of the 1996 Hughes Electronics Lawrence A. Hyland Patent Award for his work on low-noise millimeter-wave HEMTs, and the 1999 IBM Microelectronics Excellence Award for his work in Si/SiGe HBT technology.

Dawn Wang received the B.S.E.E. and M.S.E.E. degrees from Tsinghua University, Beijing, China, and the M.S. degree in solid-state physics from Arizona State University, Tempe. She was with Texas Instruments of Tucson from 1995 to 1998, where she was involved with device electrical characterization and analog and mixed-signal product engineering. In 1998, she joined the Boston Wireless Design Center, IBM Microelectronics, Lowell, MA, focusing on front-end highly integrated RF IC designs in SiGe BiCMOS technology for handset applications. She was also actively engaged with the IBM technology development team to define high-performance devices for RF applications. Since June 2002, she has been with TriQuint Semiconductors, Boston, MA, working on SiGe power amplifier circuit design and characterization. She has published more than ten technical papers in RF IC design areas.

Cuneyt Demirdag received the B.S. degree in electrical engineering from the Middle East Technical University, Ankara, Turkey, in 1995 and the M.S.E.E. degree from The Ohio State University, Columbus, in 1997. From 1997 to 2000, he was a Design Engineer with Fujitsu Microelectronics, Dallas, TX. From 2000 to 2002, he was a Design Engineer with the W-CDMA chipset development team at IBM Microelectronics, Lowell, MA. In 2002, he joined Kenet Inc., Reading, MA. His main research interests are in RF and analog IC designs.

Victoria Pereira received the B.S. degree in electrical engineering from the University of Southern California, Los Angeles, in 1990. She was with Hughes Electronics, now Raytheon, from 1990 to 1996 designing mixed-signal analog ICs, hybrid and module for radar applications. She transferred to Raytheon Advanced Products to work on high-speed converter designs in IC, hybrid and module design from 1996 to 1999. She joined the IBM Wireless Design Center in 1999, where she was involved in developing transceiver ICs for handset applications using IBM’s SiGe process. She is currently with Northrop Grumman, Palm Harbor, FL, where she is involved in high-end integrated communication ICs in 0.35-m SiGe process.