Silicon Carbide Epitaxy Silicon Carbide Epitaxy

Silicon Silicon Carbide Carbide Epitaxy Epitaxy Editor Editor Francesco LaLa ViaVia Francesco

Silicon Carbide Epitaxy Editor

Francesco La Via CNR-IMM, Z.I. Strada VIII 5, 95121 Catania, Italy

Research Signpost, T.C. 37/661 (2), Fort P.O., Trivandrum-695 023 Kerala, India

Published by Research Signpost 2012; Rights Reserved Research Signpost T.C. 37/661(2), Fort P.O., Trivandrum-695 023, Kerala, India E-mail IDs: [email protected]; [email protected] [email protected]; [email protected] Websites: http://www.ressign.com http://www.trnres.com http://www.journals.academicpursuits.us http://www.signpostebooks.com Editor Francesco La Via Managing Editor S.G. Pandalai Publication Manager A. Gayathri Research Signpost and the Editor assume no responsibility for the opinions and statements advanced by contributors ISBN: 978-81-308-0500-9

Preface Recently there are been numerous books written on SiC, which is a demonstration of the importance of this material and its potential impact on society. The majority of these books attempt to cover all the aspects of the technology from the growth, to the processing and the devices. In this book, instead, we will focalize on the epitaxial growth of 4H silicon carbide and on the hetero-epitaxial growth of 3C-SiC on different substrates. I think, in fact, that in the last ten years a large evolution of the epitaxial and hetero-epitaxial processes of silicon carbide has been made. The introduction of chloride precursors, the epitaxial growth on large area substrate with low defect density, the improvement of the surface morphology, the understanding of the CVD reactions and epitaxial mechanisms by advanced simulations are just the main results obtained in the homo-epitaxy process of 4H-SiC. Also in the hetero-epitaxy process of 3C-SiC on different substrates several important steps have been made. A more advanced knowledge on the strain formation during epitaxial growth and on the evolution of different defects has produced a large improvement of the material grown on silicon or on the hexagonal polytipes. After this large progress in the process of SiC epitaxial growth it is time to collect this knowledge in an e-book that can be easily accessible from all the silicon carbide community and that can be a reference point for the future work in this interesting field. Then I have decided to contact all the major experts of this field to write ten chapters on the growth, defects reduction and simulations of both 4H-SiC and 3C-SiC. The structure of the book is the following. After an introduction chapter on the evolution and history of the epitaxial growth of 4H-SiC on large area substrate, the introduction of chlorinated precursors in the epitaxial process is reviewed and explained in detail and the effect of this new process on Schottky diodes characteristics is shown. The improvement of the epitaxy process is strictly related to the improvement of the simulation of the growth that helps the researchers to understand the effect of different parameters on this complex process. Then the third chapter is dedicated to the simulations of the CVD systems, the reaction in the gas phase of the different precursors and the surface reaction models. The fourth chapter shows some important results obtained by simulation on the study of different growth parameters that influence the formation of defects and their evolution both on 4H-SiC and 3C-SiC. Some of these defects and the reduction of costs focus the research toward the reduction of the off-axis angle and finally to growth on an on-axis substrate. Then a chapter is dedicated to this important aspect of the growth

and shows all the difficulties and the parameters of the epitaxy process that should be changed to obtain a good material on these substrates. Both homoepitaxy (4H on 4H) and heteroepitaxy (3C on hexagonal substrate) are addressed. Finally the section on the homo-epitaxy of 4H-SiC is finished with a chapter that explain the influence of different process parameters on the formation or the reduction of the principal defects that are observed in the epitaxial layers. The section on the hetero-epitaxy of 3C-SiC starts with a chapter on the growth of 3C-SiC on large area silicon wafers. In this chapter it is described the typical process and the defects and strain that are generated during the growth on this substrate. After this introduction chapter to the hetero-epitaxy problematic, the next chapter show a possible approach for the realization of a bulk 3C-SiC growth by CVD. In this chapter it is shown the effect of different type of defects on the devices and several techniques to reduce this defects to a level compatible with the devices realization. While in the two previous chapters the hetero-epitaxy is realized on a silicon substrate, in the ninth chapter the process is realized on a hexagonal SiC politype. In this way the lattice and thermal mismatch is reduced but is also reduced the diameter of the wafer and the cost of the final wafer is greatly increased. Furthermore in this way only (111) 3C-SiC can be obtained and this can be a problem for the realization of MOSFET devices. Finally, in the last chapter of the e-book, an interesting application of the 3C-SiC material is presented in the field of advanced biomedical devices that could be one of the most interesting applications of 3C-SiC. Francesco La Via

Contents

Chapter 1 SIC epitaxial growth on large area substrates: History and evolution O. Kordina, A. Henry and E. Janzén

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Chapter 2 Fast growth rate epitaxy by chloride precursors F. La Via

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Chapter 3 SiC CVD simulation Shin-ichi Nishizawa

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Chapter 4 Theoretical Monte Carlo study of the formation and evolution of defects in the homo-epitaxial growth of SiC Massimo Camarda and Antonino La Magna Chapter 5 Epitaxial growth on on-axis substrates A. Henry, S. Leone, X. Li, J. Hassan, O. Kordina, J.P. Bergman and E. Janzén Chapter 6 4H-SiC epitaxial growth and defect characterization T. Kimoto, G. Feng, K. Danno, T. Hiyoshi and J. Suda

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Chapter 7 3C-SiC epitaxial growth on large area silicon: Thin films Andrea Severino

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Chapter 8 Bulk growth of 3C-SiC using vapor phase epitaxy Hiroyuki Nagasawa

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Chapter 9 3C-SiC epitaxial growth on α-SiC polytypes Gabriel Ferro

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Chapter 10 3C-SiC epitaxial growth for advanced biomedical applications Christopher W. Locke, Christopher L. Frewin and Stephen E. Saddow

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Research Signpost 37/661 (2), Fort P.O. Trivandrum-695 023 Kerala, India

Silicon Carbide Epitaxy, 2012: 1-25 ISBN: 978-81-308-0500-9 Editor: Francesco La Via

1. SIC epitaxial growth on large area substrates: History and evolution O. Kordina, A. Henry and E. Janzén

Department of Physics, Chemistry, and Biology, IFM, 581 83 Linköping, Sweden

Abstract. In the past decades, the commercial requirements have steered the development of SiC materials to increasing perfection in quality, size, uniformity, and reproducibility. It has indeed been intense and captivating and we have yet to see the end of this development. This brief review gives a short historic background trying to highlight the main technological achievements which have advanced the technology to the point where we stand today. The need for a high throughput has made the development of multi-wafer reactors particularly fascinating. Today there are warm-wall reactors with a capacity of 10 x 100 mm and dual chamber hot-wall reactors with a capacity of 7 x 100 mm and with auto-loading capability. The growth rate increase seen in the past decade has lead to an interesting situation as it is no longer the growth rate that limits the throughput but rather the heat- and cooldown times. At the end of this chapter a brief outlook for the future is also given.

History Silicon Carbide is interesting on account of its superior properties for high power device applications. The power devices that are of particular interest are devices that can pass large currents in the forward direction and block several Correspondence/Reprint request: Dr. O. Kordina, Department of Physics, Chemistry, and Biology, IFM, 581 83 Linköping, Sweden. E-mail: [email protected]

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hundred volts in the reverse direction. This requires large area devices which makes the demands on the deposition techniques a challenge. The substrate material has in the past recent years improved both in size and quality – however not sufficiently to process devices directly on them – which puts additional requirements on the quality and uniformity of the epitaxial layers. The epitaxial growth technique of choice is chemical vapor deposition (CVD) which has gone through a significant development in the recent decade as the demands on the material quality and throughput increases. There are two significant reports by Westinghouse on CVD from the 60‟s by Jennings et al. [1] and by Campbell and Chu [2]. In both studies they used SiCl4 and CCl4 as precursors, however, Jennings et al. used a vertical coldwall reactor with the gas inlet at the top and the substrate facing the gas flow, see Figure 1, and Campbell and Chu used a horizontal cold-wall reactor. These publications are interesting as they managed to deposit 6H on 6H Siface Lely platelets. An in-situ hydrogen etch was performed prior to growth. In the report given by Jennings et al. mechanically polished substrates and temperatures above 1725 °C were required to achieve 6H growth. Campbell and Chu, however, produced hexagonal material between 1700 °C to 1730 °C but no growth occurred at higher temperatures. They also produced doped layers using N2, PH3, AsH3, and B2H6. Von Muench and Pfaffeneder [3] also reported on a process using SiCl4 and C6H12. They used a vertical cold-wall reactor, however, the substrates were placed on an incline on the side of the susceptor i.e. not directly facing

Figure 1. Left. Schematic of the reactor used in reference 1 Top. The temperature dependence of the growth rate as measured by the authors of reference 1.

SIC epitaxial growth on large area substrates: History and evolution

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the gas flow. They produced doped layers using nitrogen, ammonia, diborane, and organometallic aluminum compounds. The organometals were added in small amounts to the hexane. The efficiency in doping was significantly better when ammonia was used as compared to nitrogen. They managed to produce very nice blue LEDs from their material. In these reports the polytype homogeneity is not very good and it appeared difficult to achieve homoepitaxial growth of 6H on 6H at lower temperatures. At higher temperatures the growth rate starts to decrease due to excess etching. The substrates were very small and of irregular shape as they used Lely substrates. An epitaxial technique of some significance was introduced by Tairov et al. which was the sublimation sandwich technique [4]. This technique was further developed by Vodakov et al. [5] using a Ta-container. The technique developed by Vodakov could produce homoepitaxial SiC at growth rates of several hundred µm/h depending on the conditions. In 1978 the seeded sublimation growth of SiC crystals was presented by Tairov and Tsvetkov [6]. This was a major breakthrough for the development of SiC as round wafers with large diameters now could be anticipated which would have an impact on the development of the epitaxial CVD systems. In figure 2 a schematic of their growth reactor is shown in cross section and also some photographs of crystals grown in it. In 1983, Nishino et al. developed a process for depositing 3C-SiC on Si substrates by introducing a buffer layer between the Si substrate and the SiC layer [7]. This was the first time thick SiC (at the time up to 34 µm thick) layers could be grown on large area substrates. Previous attempts to grow 3C on sapphire substrates yielded only thin films of less than 1 µm [8]. The work

Figure 2. The Seeded sublimation system used by Tairov and Tsvetkov. Small crystals are shown in the photograph on the right hand side. This work is a major milestone for SiC as it shows for the first time a promise of producing large diameter round wafers of SiC.

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also bears significance since it was the first time a large area epitaxial film could be produced at a moderate temperature. In 1987 Kuroda et al. demonstrated the growth of uniform hexagonal 6HSiC on off-axis 6H substrates at temperatures around 1500 °C [9]. The offangled substrates created steps which allowed the temperature to be lowered as is illustrated in figure 3. The authors called the new technique „stepcontrolled VPE‟.

Figure 3. Illustration of the ‟step-controlled VPE‟ invented by Kuroda et al. reference 9.

All these techniques were done in cold wall single wafer reactors and on rather small substrates. In the early „90s, the size of the substrates started to become significant and in the late ‟90s they had reached a size of two inches in diameter. This could be seen as the start of the development of large area epitaxial CVD reactors.

Cold-wall reactors The cold-wall reactor was by far the most common reactor up until the mid „90s [10, 11, 12] when the hot-wall reactors became popular. The reactors were normally horizontal reactors with an rf heated graphite susceptor as illustrated in figure 4. The gases used were usually silane and propane in a hydrogen carrier gas and the growth temperature was around


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1500 °C. The graphite was normally coated with SiC as the reactions between hydrogen and the graphite otherwise could change the C/Si ratio of the process as well as add a lot of impurities to the growing layer. Typically layers with a background doping concentration around 10 15 cm-3 could be obtained but the layers were not very uniform with today‟s standards. The high thermal gradients were also detrimental for the coating which sublimed and deposited on the backside of the substrates. Often all coating could be removed from the susceptor after one run which then had to be changed. The cold-wall reactors could produce layers up to about 10 µm thick but after that the morphology was typically too rough. In the report by Kimoto et al. [10], the effects of using off-oriented substrates were shown in a standard SiH4-C3H8-H2 process on 6H substrates. With well-oriented on-axis substrates, the growth produced 3C-SiC, however with a low off-cut angle the growth resulted in a single 6H-SiC film. The growth rate increased with increasing off-angle up until approximately 4° off-axis. To avoid the 3C inclusions the authors emphasized that the supersaturation in the gas phase must be kept low.

Figure 4. Schematic of a cold-wall CVD reactor. From reference 11.

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Hot-wall reactors The hot-wall reactor concept was first introduced in 1993 and has since then been scaled and developed [16, 17]. The susceptors normally consist of a top half, a bottom half and two sidewalls thus providing a rectangular growth chamber. The substrate is located on the “floor” of the susceptor, on a rotating satellite, a load plate, or on a load plate located in the center of the gas stream as illustrated in figure 5. Thermal insulation is placed around the susceptor to block all radiation coming from it which gives low energy consumption. Normally, the gases are forced through the rectangular opening using a quartz liner which gives good utilization of the gases [15]. This type of reactor was a significant step forward in terms of producing material of high quality. The material is of substantially better morphology and lower background doping. Typically the background doping was in the low 1013 cm-3 range and thicknesses greater than 50 µm could readily be grown. The growth rates were in the order of 3 – 5 µm/h initially, but they have later been increased to about 10 µm/h after some development. Thanks to the low thermal gradient [16, 17], the backside deposition was not as severe as in the cold-wall reactors and the lifetime of the susceptors could be substantially prolonged. Due to these compelling advantages, the hot-wall reactor has become increasingly popular and is today used by most groups working on SiC. A similar type of reactor which has a non-actively heated ceiling (the ceiling is heated through radiation from the susceptor) is the planetary warm-wall reactor which is by far the most common production tool for thinner layers; more on this type of reactor later. At the onset of the development of the hot-wall reactor, the susceptors were cut from a single piece to improve the coupling to the rf field. The current density was, however, much higher in the thin sides of the susceptor leading to a higher temperature on the sides. This usually resulted in premature

Figure 5. A hot-wall CVD reactor shown in cross section with the load plate located in the center of the gas stream. A quartz liner will connect to the transition piece on the left.


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breakdown of the SiC coating and erosion of the graphite underneath. To prevent this, the susceptors were split into four parts with two sidewalls and a top and bottom plate as described earlier. However, if the sidewalls were made from graphite, there was significant arcing between the sidewalls and the susceptor plates giving rise to bright hot-spots which also degraded the coating. Sidewalls of pure CVD grown polycrystalline SiC will eliminate this issue as described by Henry et al. in reference [14]. Another way to eliminate the hot spots caused by arcing is to simply use resistive heating, however, to our knowledge there has only been one attempt at making a resistively heated CVD reactor which is by Chassagne et al. [18]. They produced 3C-SiC on Si substrates in a resistively heated hot-wall reactor with very low thermal gradients. It was early recognized that the achievable growth rates and material quality from the hot-wall reactors were superior to what had been possible to achieve previously. The effective masses, for instance, had been only loosely determined in 6H by Suttrop et al. [19] and 4H by Götz et al. [20] by way of assigning IR absorption lines and applying the Faulkner theory [21]. Later, Son et al. could accurately determine the effective masses in 6H and 4H using cyclotron resonance on thick high purity layers grown in the hot-wall reactor [22, 23]. The hot-wall reactor was commercialized by Epigress (now Aixtron) and has gone through significant development but is in essence the same reactor. Wafer rotation using gas foil rotation is now standard [24, 25]. When the rotation was initially introduced the satellite rotation was disturbed by the rf field which could force the satellite to rotate in the opposite direction. This has now been sorted out through the introduction of a heater consisting of a uniform cylinder inside which the susceptor is placed. The susceptor consists of two main parts; the bottom and a top and walls in one piece. In the bottom, the rotating satellite is placed. The heater heats the susceptor through radiation. This concept is very nice as it completely eliminates arcing and hot spots and the rotation is also unaffected due to the screening of the heater. The drawback with this arrangement is the long cool down time. Such a reactor provides a very good thickness and doping uniformity; typically, the thickness uniformity is better than 3% and the doping uniformity is better than 15% (sigma/mean) over a single 100 mm wafer using standard chemistry (silane together with propane/ethylene). The horizontal hot-wall reactor has been scaled up to a 3 x 3-inch configuration using gas foil rotation for both wafer and susceptor rotation. In a 6 x 2” horizontal configuration without wafer rotation the reactor achieved an excellent 1.2% and 5.4% thickness and doping uniformity (expressed as (max – min)/(max + min)) when using a chlorinated chemistry which has a

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better chance of reaching good uniformity [26]. In a 3 x 3” configuration with wafer and susceptor rotation a 1.6% and 4.8% thickness and doping uniformity was obtained using standard chemistry [27]. On account of the success of the hot-wall reactor, a multi-wafer planetary style hot wall reactor was developed with an actively heated ceiling. Wischmeyer et al. came out with the first results in 2001 on a 7 x 2” configuration which gives extremely good thickness and doping uniformity with a thickness and doping uniformity of 0.4% and 6% (sigma/mean), respectively and a wafer to wafer thickness and doping uniformity of 0.6% and 3.6%, respectively [28].

Planetary reactors As mentioned in the previous section, the hot-wall planetary reactor is a multi-wafer type reactor that gives excellent uniformity and reproducibility. A very similar and much more common type of production reactor is the planetary warm-wall reactor which has a passively heated ceiling that reaches a temperature above the Si melting point. The schematics of a planetary warm-wall reactor are shown in figure 6. The reactors have an rf heated mechanically rotating susceptor with several rotating satellites placed along the periphery. The satellites are rotated with gas foil rotation i.e. a small flow of Ar lifts the satellite and rotates it through viscous forces as it flows in shallow grooves shaped as a spiral that are cut into

Figure 6. A warm-wall planetary reactor. A) Water cooled gas injector. B) Radiatively heated warm-wall ceiling. C) Exhaust gas collector. D) Susceptor. E) Substrate on rotating satellite. F) Rotating susceptor support. Ref. 31.


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the susceptor. The gas inlet is in the center and the outlet along the edge of the rotating susceptor. The velocity of the gas is hence decreasing proportionally to the square of the distance from the center. This generates a very strong depletion profile over the wafer position. Ideally this depletion should be perfectly linear in which case the result will be a uniform film when the wafer rotates. The first warm-wall planetary reactor for SiC was a 7 x 2” reactor built by Aixtron and developed by Burk et al. and the first results were published in 1997 [12]. Thickness and doping uniformities were already then quite good with a uniformity of 4% and 7%, respectively. Shortly after a hot-wall version of the reactor was made with a capacity of 7 x 2” wafer. As mentioned earlier and as may be seen in the schematic drawing in figure 7, this reactor has an actively heated ceiling with a separate coil and rf unit for the ceiling. Naturally, the hot-wall version becomes a more expensive tool due to the added complexity and extra rf unit. Results from the hot-wall version were presented as a poster at the ICSCRM 2001 conference. It has an impressive thickness and doping uniformity of 0.4% and 6%, respectively [28]. Results from a 5 x 3” hot-wall reactor has been presented by Thomas et al. at the ICSCRM conference in 2005 [29] giving a 2% and 10% thickness and doping uniformity, respectively. The AIX 2800G4 WW is an impressive reactor which has a capacity of 10 x 100 mm wafers or 6 x 150 mm wafers. As illustrated in figure 8, the gases are introduced via a triple injector with the process gases flowing through the center cushioned by a flow of hydrogen on either side i.e. toward the ceiling and susceptor. HCl may be added to the flow as well. The temperature can be

Figure 7. The actively heated hot-wall planetary reactor. Ref 31.

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Figure 8. Schematic of the AIX 2800G4 10 x 100 mm reactor with a triple gas injector. Ref 30.

monitored on each individual wafer through a small hole located right above the wafer center. Excellent temperature uniformities have been measured over each individual wafer and between wafers which is essential in order to obtain a good thickness and doping uniformity. The first results on the AIX 2800G4 WW showed a thickness and doping reproducibility of 1% - 2% and 2% - 6%, respectively in the 10 x 100 mm configuration. Wafer-to-wafer uniformities are also very good; 2% - 3% and 4% - 10%, respectively, but need further improvement for production purposes according to the authors [30]. Thickness and doping uniformities can be seen in figure 9 for a fully loaded 10 x 100 mm run. In this publication the authors also comment on that the step bunching and hence roughness of the layers is lower in the AIX 2800G4 WW compared to the smaller hot-wall planetary reactor which has an actively heated ceiling. The RMS roughness is around 1 nm for the warm-wall and around 2 nm for the hot-wall. Furthermore particle contamination is consistently lower from the warm-wall reactor than from the hot-wall reactor which according to the authors is due to a careful design of the hot zone parts. In terms of material quality, the planetary warm-wall reactors compare favorably to the horizontal hot-wall reactors. The background doping reported by Burk [31] is in the low 1014 cm-3 range with minor Al compensation and the carrier lifetime of a 80 µm thick layer was 719 ns. The number of epitaxial defects was also very low; only about 0.2 cm-2 caused by particles and the density of carrots [32] is about 2 cm-2. It is not only Aixtron that makes multi-wafer reactors for SiC. Tokyo Electron Limited recently developed a multi-wafer reactor for SiC called Probus-SiC together with Kyoto University and Rohm Co., Ltd. The reactor


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Figure 9. The thickness and doping uniformities obtained with the AIX 2800G4 reactor of a fully loaded 10 x 100 mm run. Ref. 30.

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is a hot-wall reactor with a capacity of 10 x 3-inch, 7 x 4-inch, or 3 x 6-inch wafers. It has an impressive uniformity in thickness and doping on 3-inch wafers with an intra-wafer uniformity of 0.478% and 3.67% σ/mean for thickness and doping, respectively. The wafer-to-wafer uniformity is 0.376% and 2.91% for thickness and doping, respectively, and the run-to-run reproducibility is 0.187% and 4.93% for thickness and doping, respectively. The tool also can accommodate two process chambers and an auto-loader [33].

Turbo disc The turbo disc reactor is a vertical reactor in the sense that the gas inlet is from the top. The substrates are placed on a rapidly rotating susceptor facing the gas inlet. Thanks to the rapid rotation the gases are forced down toward the susceptor and wafers. The gases flow across the wafers and then down and out as illustrated in figure 10. Due to the strong thermal gradient and the high concentration of gases close to the susceptor area strong Si clustering can be observed as an irradiant layer hovering over the susceptor. The irradiant layer was first noticed by Rupp et al. and with the aid of simulations it could be determined that it was caused by homogenous nucleation of Si [34]. Figure 10 shows the schematic of the reactor and a photograph of the irradiant layer observed by the authors. The simulations shown in figure 10 confirmed the theory that the irradiant layer was caused by Si clusters. In terms of uniformity, the single wafer reactor yielded fairly good results with a doping uniformity over a 35 mm diameter wafer of 12%, however, the 6 x 2-inch version did not give such excellent uniformities as the planetary reactor gives with a ± 30% and ±10% uniformity for the doping and thickness, respectively [35]. The problem with this type of system is that in the multi wafer construction there is no inter wafer rotation which makes scaling up very challenging for SiC epitaxial growth which is conducted at such high temperatures. The turbo-disc rector concept for SiC has nowadays been abandoned but it remains successful for the Group III/N material systems. Multiwafer systems for SiC are today when this book is published to our knowledge exclusively done using the planetary style reactors developed by Aixtron or the horizontal hot-wall style reactor developed by Tokyo Electric Limited.

Homogeneous nucleation One very important aspect to consider when growing SiC at high growth rates is the homogeneous nucleation which, as mentioned, was first observed by Rupp et al. [34] in the turbo disc rector concept. This is the clustering of


Figure 10

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Figure 10. Top left. Schematic of the turbo-disc reactor for SiC. Top right. The observed irradiant layer which was identified to be caused by Si-clusters. Left. Simulations of the gas flow and Si droplet formation showing a high density of droplets right above the wafer which confirmed the identity of the irradiant layer. Ref. 34.

silicon in the gas phase which can become so extreme that visible droplets (visible as a white smoke) appear in the gas phase. It is by no means something unique to the turbo disc reactor but may occur in all types of reactors particularly when the growth rate is increased. The increasing demand for higher throughput has made the need for higher growth rates ever more important and has hence made the homogeneous nucleation such an important issue. There are different ways to overcome this issue: A higher growth temperature can be employed which is the chimney reactor concept developed by Ellison et al.; a significantly lower pressure and/or higher carrier gas flow can be used when growing the material which is a method used by Tsuchida et al.; and finally a different chemistry can be used which reduces or eliminates the formation of Si-Si bonds to be replaced by other species that can be used for deposition.

Chimney reactor The first type of reactor that successfully managed the Si cluster formation was an elegant type of reactor developed by Ellison et al. [36].


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Instead of fighting the problem the authors used it to their advantage. Figure 11 shows the schematics of the chimney reactor. It is a vertical reactor with the inlet at the bottom inspired by the HTCVD growth which had been developed some years before [37]. By reducing the carrier flow significantly and using a growth pressure between 200 – 400 mbar the silane would decompose and form large clusters. As the Si clusters moved into the growth zone, they would dissociate and deposit onto the substrate located in the center of the growth zone. Parasitic deposition was kept low due to the cluster formation, however, there was significant parasitic deposition in the funnel-shaped inlet of the reactor. The growth temperature was kept between 1650 °C – 1850 °C and the higher growth temperatures generally gave the highest growth rates as seen in figure 12. The right hand figure also shows the dependence on the pressure. A sharp drop in growth rate caused by etching is observed at pressures lower than about 200 mbar. Typical growth rates were around 25 µm/h. The material quality was indeed very good but a major drawback was the poor uniformity of the thickness and doping owing to the dissociation of the clusters. Moreover, the carrier lifetimes were low due to the high growth temperatures and lack of proper coating materials of the susceptor, and the reproducibility was not very good.

Figure 11. Schematic of the chimney reactor developed by Ellison et al. Ref 36.

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Figure 12. The growth rate as a function of temperature (left) and as a function of pressure (right) in a chimney reactor. Ref. 36.

Due to the reduced pressure, the buoyancy effect would in fact not play a major role which was tested by Zhang et al. in a chimney reactor with the flow entering from the top [38]. Indeed, the results obtained by Zhang et al. showed that there was no major difference in the behavior of the reactor whether the flow was entered through the top or the bottom. The buoyancy effect had very little impact.

Low pressure, high carrier flow growth Another method used for dealing with homogeneous nucleation would be to reduce the operating pressure and increase the hydrogen flow. This has been the traditional way to deal with Si clusters when using the standard SiH4-C3H8-H2 chemistry as it became apparent that the morphology improved by reducing the pressure and increasing the carrier flow using otherwise standard CVD conditions. The technique was beautifully expanded and improved by Tsuchida et al. [39] where the authors reduced the pressure to below 40 mbar while maintaining a high flow rate of hydrogen of 50 – 70 SLM. In doing so, the growth rate could gradually be increased up to 250 µm/h by increasing the silane and propane flow rates. A schematic of their reactor is shown in figure 13. When the Si/H2 ratio reached 0.5%, the authors observed a saturation of the growth rate as is seen in figure 14 (left) and the layers started to become very rough. The dependence of the pressure was also investigated and it was found that the growth rate was greater than 200 µm/h at a pressure of 13 mbar,


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Figure 13. Schematic of the low pressure – high carrier flow reactor. Ref. 39

Figure 14. The growth rate as a function of silane flow (left): At a SiH4/H2 ratio of 0.5% the growth rate saturates and rough layers are produced. Right: The growth rate as a function of pressure. A slight increase in growth rate can be seen between 13 mbar and up to 40 mbar followed by a sharp decrease in growth rate caused by homogeneous nucleation. In the pressure range between 13 and 40 mbar the layers were specular, however, at 67 mbar the layers were rough. Ref. 39.

increased slightly with increasing pressures up to 40 mbar but then dropped markedly at a growth pressure of 67 mbar (figure 14, right). At this pressure the drop in growth rate was accompanied by a rough morphology. The hydrogen flow, temperature, silane flow, and C/Si ratio were kept at, 50 SLM, 1750 °C, 300 sccm, and 1, respectively during this experiment. Similarly, when the hydrogen flow rate is reduced to below 40 SLM, the growth rate starts to decrease. This behavior can be explained by the formation of Si clusters in the gas phase. The formation of Si clusters is inhibited at low pressures and/or high carrier flows. However, if the pressure is increased or the carrier flow is reduced, clusters form which have a low likelihood of participating actively in the growth but they will rather move

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through the reactor and get trapped in filters or stick on the reactor walls. If the clusters impinge on the surface of the growing crystal it is even worse as they will be a disturbance and cause poor morphology. The slight decrease in growth rate seen when going from 40 to 13 mbar is likely due to an increased etch rate of the surface which should not cause a degradation of the surface morphology. This is also seen by the authors as they report on mirror like morphology throughout this pressure range. The results are indeed impressive from this reactor. The surface roughness is around 0.2 nm even for layers with an overall thickness greater than 200 µm. Doping levels around 1 – 2 x 1013 cm-3 are achieved with little or no compensation of acceptors as evidenced by the low temperature photoluminescence spectra. A very good uniformity is also achieved with a thickness and doping uniformity of 1.2% and 6.7% (σ/mean), respectively over a 65 mm radius corresponding to a wafer diameter of greater than 5-inches [40].

Chloride-based epitaxy The last way to avoid issues with homogeneous nucleation that will be described here is to take the aid of chemistry. The bond strength between silicon atoms is not very high and by introducing a chemical which bonds harder to silicon than silicon itself one can avoid homogeneous nucleation. A natural choice of chemical is chlorine which forms bonds with Si at a strength of 400 kJ/mol compared to the Si-Si bond strength which is 226 kJ/mol [41]. The chloride-based chemistry is also well established in the Si industry so the various chemicals are readily available. Chloride-based chemistry has been used previously for SiC epitaxy though the first time it was used specifically to overcome homogeneous nucleation was in 2001 and formulated in a patent 2003 [42]. Using the standard chemistry, e.g. SiH4-C2H4-H2, and adding HCl will dramatically reduce the amount of Si clusters in the gas phase. The growth rate increases and the morphology improves. The HCl and Si will form SiCl 2 or SiHCl species which both are stable species at the growth temperatures that are used and both are presumed active in the growth. There is no need to reduce the pressure, increase the hydrogen flow rate, or temperature. The SiCl2 species will attach to the SiC surface where it will decompose and the Cl will leave in the form of HCl. Figure 15 (right) shows the surface of a layer grown using the standard chemistry which is marred by morphological defects caused by Si droplets that have impinged on the surface and evaporated. The four smaller images on the right of figure 15 shows layers grown at different growth rates using the standard chemistry with HCl added.


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Figure 15. Left. Using the standard chemistry when growing SiC can give rise to huge problems of homogeneous nucleation as may be seen in this Nomarski image showing imprints of Si droplets that have impinged on the surface and evaporated. The bar is 100 µm long. Right. Four layers grown with chloride based epitaxy at different growth rates. Ref 44.

Of course there is great freedom to use different chlorinated precursors which also has been done by various researchers. For a good review please see [43] or chapter two in this book. The standard chemistry with HCl addition is the most tried chemistry so far however, it has been observed that using this combination is less effective than adding the chlorine in another manner. Methyltrichlorosilane (MTS) [44], trichlorosilane (TCS) [45], or silicon tetrachloride (TET) [46] are for instance substantially more efficient as a precursor. This may be understood easily simply by comparing the reaction path of silane and HCl to SiCl2 with e.g. TCS to SiCl2. In the case of silane and HCl, the silane must break four bonds and two HCl molecules must break one bond each plus the species must physically meet in the gas phase in order to form SiCl 2. This should be compared with TCS which only has to break off a hydrogen and Cl to form the desired SiCl2 and giving off HCl as a rest product. The chloride based epitaxial growth has demonstrated extremely high quality material grown at very high growth rates. Growth rates as high as 170 µm/h have been demonstrated by Pedersen et al. [47] using MTS at standard growth temperatures for SiC epitaxial growth. In a vertical arrangement Leone et al. [48] demonstrated growth rates as high as 250 µm/h (see figure 16) using the standard chemistry with HCl additions and 350 µm/h using TET at 1850 °C which equals the growth rates obtained in crystal growth conducted at significantly higher temperatures. In this paper, the authors also grew several mm thick layers and demonstrated also how beautifully the micropipes closed (see figure 17).

20

O. Kordina et al.

Figure 16. The growth rate and 3C-inclusion percentage for the growth of SiC in a vertical arrangement used by Leone et al. At a temperature of 1850 °C and higher the 3C inclusions were gone. The growth rate peaks at 1850 °C which hence was the preferred growth temperature. When using SiCl4 instead of the standard chemistry with HCl the growth rate increased to 350 µm/h. From ref 48.

Figure 17. Left. A several mm thick layer grown using TET and ethylene in a vertical reactor at 1850 °C. Right. Micropipes close beautifully in using this process. Ref 48.

Here it should be prudent to mention that overgrown micropipes is of course something desirable, however, the micropipe splits into several screw dislocations as can be seen in the right hand image of figure 17. According to a study by Rupp et al. [49], the screw dislocations are surrounded by several dislocations in the basal plane. When a Schottky diode is placed on such


21

heavily dislocated area, it will give rise to a severe temperature increase leading to a premature breakdown of the device. Generally, the purity of the chloride-based material is very high with background doping levels in the mid 1013 cm-3 range. 200 µm thick layers were grown using MTS at a growth rate of 100 µm/h displayed extraordinary high quality with a XRD rocking curve FWHM of 9 arcsec [50] (see figure 18).

Figure 18. A 200 µm thick layer grown with MTS at 1600 °C at a growth rate of 100 µm/h. The XRD FWHM rocking curve is only 9 arcsec corroborating the outstanding structural quality of the material. From ref. 50.

VLS and LPE These two techniques are related to each other as the growth is done by transporting carbon through a melt of silicon, often with a metal solvent such as scandium involved. The LPE technique has been studied by Rendakova et al. [51]. The techniques are interesting as micropipes tend to close efficiently, however this is by no means something unique to VLS or LPE as the micropipe closing occurs nicely in CVD as well as seen in the previous section (figure 17). The LPE technique can achieve growth rates as high as 300 µm/h. The VLS technique has been studied by Ferro et al. [52]. Here the carbon is supplied by decomposing a hydrocarbon at the liquid vapor interface. The carbon subsequently diffuses through the melt to the solid liquid interface where the growth occurs.

Future outlook The future of SiC epitaxy will be very interesting to follow. The great advances in growth rate that has been achieved in recent years by either the low pressure-high carrier approach embraced by Tsuchida et al. or by using

22

O. Kordina et al.

the chlorinated process which has been adopted by several groups has led to a point where the throughput is no longer limited by the growth rate even if very thick layers are grown. The heat-up and especially cool-down times are significantly longer than the growth time regardless which type of reactor is used. Furthermore, load times (which includes cleaning of the reactor components) is taking a significant amount of time. When optimizing the turnaround time, the focus must be more on increasing heat-up, cool-down, cleaning, and load times. The multi-wafer reactors are impressive tools in many aspects but the question is if this truly is the future for high volume commercial epitaxial growth? The larger the reactor, the longer it will take to heat up, cool down, and clean and it will cut into the gain in capacity. Single wafer reactors may be the way to go in the future where small susceptors with a low thermal mass are used in combination with an efficient way of heating so the heat-up and cooldown times can be minimized. And why not hot loading of the reactor at e.g. 1000 °C using a robot? Cleaning of the reactor should also be made in a better manner. Perhaps an HCl and H2 etch at high temperature can be implemented at regular intervals to reset the susceptor into a condition which ensures reproducibility. Coating materials such as TaC can withstand HCl and H 2 very well and it should not cause any major difficulties in implementing such a procedure provided that the heat-up and cool-down is rapid.

References 1.

Jennings VJ, Sommers A, and Chang HC, J. Electrochemical Society, 113 (7), 728 (1966). 2. Campbell RL and Chu TL, J. Electrochemical Society, 113 (8), 827 (1966). 3. von Muench W and Pfaffeneder I, Thin Solid Films, 31, 39 (1976). 4. Tairov YuM, Tsvetkov VF, Lilov SK, and Safaraliev GK, J. Cryst. Growth, 36, 147 (1976). 5. Vodakov YuA, Roenkov AD, Ramm MG, Mokhov EN, and Makarov YuN, Phys. Stat. Sol. (b), 202, 177 (1997). 6. Tairov YM, and Tsvetkov VF, J. Cryst. Growth, 43, 209 (1978). 7. Nishino S, Powell A, and Will H, Appl. Phys. Lett., 42 (5), 460 (1983). 8. Khan H and Learn AJ, Appl. Phys. Lett., 15 (12), 410 (1969). 9. N. Kuroda, K. Shibahara, W. S .Yoo , S. Nishino, and H. Matsunami, "StepControlled VPE Growth of SiC Single Crystals at Low Temperatures", Ext. Abstr. 19th Conf. Solid State Devices and Materials, Tokyo, pp. 227-230, (1987). 10. Kimoto T, Itoh A, and Matsunami H, Phys. Stat. Sol. (b), 202, 247 (1997). 11. Tsunenobu Kimoto, PhD thesis “Step-Controlled Epitaxial Growth of α-SiC and Device Applications”, Dept. of Electronic Science and Engineering, Kyoto University, October 1995, p. 21. 12. Burk AA and Rowland LB, Phys. Stat. Sol. (b), 202, 263 (1997).


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13. O. Kordina, C. Hallin, R. C. Glass, A. Henry, and E. Janzén, “A Novel Hot-Wall CVD Reactor for SiC Epitaxy”, in proceedings of the International Conference for Silicon Carbide and Related Materials (ICSCRM-93), Washington DC, 1993, Inst. Phys. Conf. Ser., 137, 41 (1994). 14. A. Henry, J. ul Hassan, J. P. Bergman, C. Hallin, and E. Janzén, Chem. Vap. Dep., 12, 47 (2006). 15. Henry A, Leone S, Beyer FC, Pedersen H, Kordina O, Andersson S, and Janzén E, Physica B 407, 1467 (2012). 16. B. Thomas, W. Bartsch, R. Stein, R. Schörner, D. Stephani, ”Properties and Suitability of 4H-SiC Epitaxial Layers Grown at Different CVD Systems for High Voltage Applications”, in proceedings of the International Conference for Silicon Carbide and Related Materials (ICSCRM-2003), Lyon, France, 2003, Mater. Sci. Forum, 457-460, 181 (2004). 17. Ö. Danielsson, C. Hallin, E. Janzén, J. Cryst. Growth, 252, 289 (2003). 18. T. Chassagne, A. Leycuras, C. Balloud, P. Arcade, H. Peyre, and S. Juillaguet, “Investigation of 2-inch SiC layers grown in a resistively-heated LP-CVD reactor with horizontal “hot-walls”, in proceedings of the International Conference for Silicon Carbide and Related Materials (ICSCRM-2003), Lyon, France, 2003, Mat. Sci. Forum, 457-460, (2004), pp. 273-276. 19. Suttrop W, Pensl G, Choyke WJ, Stein R, and Leibenzeder S, J. Appl. Phys., 72 (11), 5437 (1992). 20. W. Götz, A. Schöner, G. Pensl, W. Suttrop, W. J. Choyke, R. Stein, and S. Leibenzeder, ”Hall Effect and Infrared Absorption Measurements on Nitrogen Donors in 4H-SiC”, in proceedings of the 5th International Conference on Shallow Impurities in Semiconductors, Kobe, Japan, Mat. Sci. Forum, 117-118, 495 (1993). 21. Faulkner RA, Phys. Rev. Lett., 1 (12), 450 (1958). 22. Son NT, Kordina O, Konstantinov AO, Chen WM, Sörman E, Monemar B, Janzén E, Appl. Phys. Lett., 65 (25), 3209 (1994). 23. Son NT, Chen WM, Kordina O, Konstantinov AO, Monemar B, Janzén E, Hofman DM, Volm D, Drechsler M, Meyer BK, Appl. Phys. Lett., 66 (9), 1074 (1995). 24. P. M. Frijlink, J. Cryst. Growth, 93, 207 (1988). 25. J. Zhang, U. Forsberg, M. Isacson, A. Ellison, A. Henry, O. Kordina, and E. Janzén; J. Cryst. Growth 241, 431 (2002). 26. D. Crippa, G. L. Valente, A. Ruggiero, L. Neri, R. Reitano, L. Calcagno, G. Foti, M. Mauceri, S. Leone, G. Pistone, G. Abbondanza, G. Abbagnale, A. Veneroni, F. Omarini, L. Zamolo, M. Masi, F. Roccaforte, F. Giannazzo, D. di Franco, and F. la Via, “New Achievements on CVD Based Methods for SiC Epitaxial Growth”, in proceedings of the 5th European Conference on Silicon Carbide and Related Materials, Bologna, Italy, September 2004, Mater. Sci. Forum, 483-485, 67 (2005). 27. J. J. Sumakeris, M. K. Das, S. Ha, E. Hurt, K. Irvine, M. J. Paisley, M. J. O‟Loughlin, J. W. Palmour, M. Skowronski, H. McD. Hobgood, C. H. Carter, Jr., “Development of Epitaxial SiC Processes Suitable for Bipolar Power Devices”,

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28. 29.

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31. 32. 33. 34. 35. 36. 37. 38. 39.

40. 41. 42. 43. 44. 45.

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in proceedings of the 5th European Conference on Silicon Carbide and Related Materials, Bologna, Italy, September 2004, Mater. Sci. Forum, 483-485, 155 (2005). F. Wischmeyer, K. Christiansen, C. Hecht, R. Berge, D. Stephani, H. Juergensen, poster presentation at ICSCRM 2001 held in Tsukuba, Japan, unpublished. B. Thomas, C. Hecht, R. Stein, P. Friedrichs, “Challenges in Large-Area MultiWafer SiC Epitaxy for Production Needs”, in proceedings of the International Conference on Silicon Carbide and Related Materials (ICSCRM-05), Pittsburgh, Pennsylvania, USA, September 2005, Mater. Sci. Forum, 527-529, 135 (2006). C. Hecht, R. Stein, B. Thomas, L. Wehrhahn-Kilian , J. Rosberg, H. Kitahata, F. Wischmeyer, “High-performance multi-wafer SiC epitaxy – First results of using a 10 x 100mm reactor”, in proceedings of the International Conference on Silicon Carbide and Related Materials (ICSCRM-09), Nürnberg, Germany, October 2009, Mater. Sci. Forum, 645- 648, 89 (2010). Burk AA, Chem. Vap. Deposition, 12, 465 (2006). Hassan J, Henry A, McNally PJ, and Bergman JP, J. Cryst. Growth, 313 1828 (2010). See www.tel.co.jp and search for probus-SiC Rupp R, Makarov YuN, Behner H, and Wiedenhofer A, Phys. Stat. Sol. (b), 202, 281 (1997). Rupp R, Wiedenhofer A, and Stefani D, Mat. Sci. And Engineering B61-62, 125 (1999). Ellison A, Zhang J, Henry A, and Janzén E, J. Cryst. Growth, 236, 225 (2002) Kordina O, Hallin C, Ellison A, Bakin AS, Ivanov IG, Henry A, Yakimova R, Tuominen M, Vehanen A, and Janzén E, Appl. Phys. Lett., 69 (10), 1456 (1996). Zhang J, Ellison A, Danielsson Ö, Linnarsson MK, Henry A, and Janzén E, J. Cryst. Growth, 241, 421 (2002). H. Tsuchida, M. Ito, I. Kamata, M. Nagano, T. Miyazawa, and N. Hoshino, “Low-pressure fast growth and characterization of 4H-SiC epilayers”, in proceedings of the International Conference on Silicon Carbide and Related Materials (ICSCRM-09), Nürnberg, Germany, October 2009, Mat. Sci Forum, 645-648, 77 (2010). Ito M, Storasta L, and Tsuchida H, Appl. Phys. Express, 1, p 015001 (2008) See for instance G. Aylward and T. Finlay, SI Chemical Data, 4th edition, Wiley, Milton, Australia, p 115 (1998). O. Kordina, US patent application 7,247, 513. Pedersen H, Leone S, Kordina O, Henry A, Nishizawa S, Koshka Y, and Janzén E, Chemical Review, Publication Date (Web): December 2, 2011. H. Pedersen, S. Leone, A. Henry, F.C. Beyer, V. Darakchieva, and E. Janzén, J. Cryst. Growth, 307, 334 (2007). S. Leone, M. Mauceri, G. Pistone, G. Abbondanza, F. Portuese, G. Abagnale, G.L. Valente, D. Crippa, M. Barbera, R. Reitano, G. Foti, and F. la Via, “SiC-4H Epitaxial Layer Growth Using Trichlorosilane (TCS) as Silicon Precursor”, in proceedings of the International Conference on Silicon Carbide and Related


46.

47. 48. 49.

50. 51. 52.

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Materials (ICSCRM-05), Pittsburgh, Pennsylvania, USA, September 2005, Mater. Sci. Forum, 527-529, 179 (2006). S. P. Kotamraju, B. Krishnan, and Y. Koshka, “Epitaxial growth of 4H-SiC with high growth rate using CH3Cl and SiCl4 chlorinated growth precursors”, in proceedings of the International Conference on Silicon Carbide and Related Materials (ICSCRM-09), Nürnberg, Germany, October 2009, Mater. Sci. Forum, 645-648, 103 (2010). Pedersen H, Leone S, Henry A, Kordina O, and Janzén E, J. Cryst. Growth, 312, 24 (2010). Leone S, Beyer FC, Henry A, Hemmingsson C, Kordina O, and Janzén E, Crystal Growth and Design, 10, 3743 (2010). Rupp R, Treu M, Türkes P, Beermann H, Scherg T, Preis H, and Cerva H, “Influence of overgrown micropipes in the active area of SiC Schottky diodes on long term reliability”, in proceedings of the 5th European Conference on Silicon Carbide and Related Materials, Bologna, Italy, September 2004, Mat. Sci. Forum, 483-485, 925 (2005). Pedersen H, Leone S, Henry A, Darakchieva V, Carlsson P, Gällström A, and Janzén E, Phys. Stat. Sol (RRL), 2 (4), 188 (2008). Rendakova SV, Nikitina IP, Tregubova AS, and Dmitriev VA, Journal of Electronic Materials, 27 (4), 292 (1998). Ferro G and Jacquier C, New Journal of Chemistry, 28, 889 (2004).



2. Fast growth rate epitaxy by chloride precursors F. La Via

CNR-IMM, Z.I. Strada VIII 5, 95121 Catania, Italy

Abstract. In this chapter the epitaxial process with chloride precursors has been described and the main parameters (Si/H2, C/Si, Cl/Si, growth rate) that influence the growth and the quality of the epitaxial layer have been discussed in detail. In particular it has been shown that the growth rate can be increased to about 100 m/h but higher growth rate can be difficult to reach due to the limited surface diffusion at the usual temperature of SiC epitaxy. Furthermore from the experimental results it seems that at least a Cl/Si ratio equal to 2 should be used to obtain a good surface morphology and a low density of point defects. Increasing the growth rate also the C/Si ratio should be changed in order to obtain a good surface morphology and a low density of defects. Finally this process gives the opportunity to reduce several kind of defects (Basal Plane Dislocations and Stacking Faults) and to decrease the surface roughness at the same time.

Introduction The homoepitaxial growth of -SiC has been performed by liquid phase epitaxy (LPE) and chemical vapour deposition (CVD) methods. Although CVD has the advantages of the precise control and uniformity of epilayer Correspondence/Reprint request: Dr. F. La Via, CNR-IMM, Z.I. Strada VIII 5, 95121 Catania, Italy E-mail: [email protected]

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F. La Via

thickness and impurity doping, the quality of the epilayers can be affected by polytype mixing. In 1986 Matsunami et al. [1] found that single crystalline 6HSiC could be grown homoepitaxially on off-oriented 6H-SiC (0001) at low temperatures (1400-1500 °C). This technique was named “step-controlled epitaxy”, since the polytype can be controlled by surface steps existing on offoriented substrates. This technique was a real breakthrough in two senses: (a) the growth temperature could be reduced more than 300 °C; (b) the quality of the resulting epilayers was very high and suitable for device applications. Typically SiC homo-epitaxial growth is done using silane (SiH4) as silicon precursor and light hydrocarbons like ethylene (C 2H4) or propane (C3H8) as carbon precursor. Hydrogen gas, sometimes mixed with argon, is used as carrier gas. The growth temperature and pressure are usually between 1500 and 1650 °C and 100-1000 mbar, respectively. Mirror-like surfaces were obtained, using this process, for C/Si ratios between 1.4 and 2.5. The growth rate was almost constant with these parameters and increased proportionally with the SiH4 flow rate. A remarkable decrease of the growth rate was observed instead for C/Si 100 µm/h) with good surface morphology (RMS ≈ 0.3 nm), high minority carrier lifetime (≈ 1 s) [20] and good thickness and doping uniformity. In a different approach, 4H-SiC epitaxial layers have been grown using trichlorosilane (TCS) as silicon precursor together with ethylene as carbon

30

F. La Via

precursor [21,22,23]. TCS is the typical precursor used in silicon epitaxy for its safety (it is not pyrophoric at room temperature) and stability in industrial processes and should also allow to avoid the homogeneous nucleation of silicon droplets in the gas phase. In fact, the simple replacement of SiH4 with SiHCl3 (TCS) produces a significant alteration of the species involved in the reaction [24]. The key is the shift from Si to SiCl2 as the dominant Si containing species for the growth. While atomic Si is the main chemical species responsible for the homogeneous nucleation of silicon droplets in the gas phase, SiCl2 is very stable and thus remains available to contribute to the film growth while suppressing homogeneous gas phase nucleation of Si during the growth [24]. The Schottky diodes realized on the epitaxial layers grown with this process show good electrical characteristics and high yield [19,22,23,25, 26,27]. This process is therefore extremely interesting for high voltage SiC devices with breakdown voltages of about 10 kV. Another process recently proposed was based on the use of methyltrichlorosilane as a single gaseous precursor [28,29]. Using this single precursor growth rates higher than 100 m/h can be reached with good epitaxial layer quality. Unfortunately no electrical data are available for this new process and, from the first results, it seems that the main limitation is related to the use of a single precursor that fixes the C/Si ratio to 1. To change this ratio, which is very important when doped layers are needed, it is necessary to introduce the classical precursors (silane and propane) into the reactor. Thus, the process becomes more complicated because there must be three different precursors, one of which is silane that is pyrophoric and potentially dangerous. In this chapter epitaxial growth by chlorinated precursors will be reviewed in detail and the effect of different growth parameters (C/Si, Cl/Si, temperature, growth rate, thickness, …) on the epitaxial layer morphology, defects and yield of Schottky diodes will be reported. All the different approaches used in literature will be compared in this chapter trying to understand the difference and the similarity between the different processes realized on different CVD reactors.

Chlorine effect For the growth of SiC epitaxial layers using a chloride based chemistry, can be chosen five main approaches to add chlorine to the gas mixture: (a) add a flow of HCl gas to the standard precursors silane and a hydrocarbon (propane or ethylene); (b) replace the silane with a chlorinated silane molecule (SiHxCly) while keeping the propane/ethylene; (c) replace the

Fast growth rate epitaxy by chloride precursors

31

carbon precursor with a chlorinated hydrocarbon (CH xCly) while keeping the silane; (d) use a molecule that contains silicon, carbon and chlorine (SiCxClyHz) or (e) use a combination of chlorinated silane molecule and chlorinated hydrocarbon molecule (SiHxCly+ CHxCly). Results from all these approaches have been reported for homoepitaxial growth and are reviewed below. In this section we will start our discussion on the effect of chlorine using the first approach described previously, i.e. adding a flow of HCl to the standard precursors. In Fig. 1 four different optical microscopies of the SiC surface are reported. In all the four growth processes the C/Si ratio was fixed to 1.5 while the Si/H2 dilution ratio was increased from 0.01 % to 0.1 %. From these microscopies, it can be observed that, while at a low (00 thus, verifying the influence of the longrange interaction on the step bunching instability.

Figure 6. Pre- and post- growth terrace width distribution (in units of the lattice parameter) as function of the long range interaction ELR. A double peak distribution (present for ELR > 0) is indicative of step bunching (as in ref.[36]).

Kinetic origin The final source of surface instabilities can be kinetic and, more specifically, it can be connected to the interaction of the train of steps with defects on the terraces such as dislocations, downfall or two dimensional defect, either generated during the growth or originating from the substrate. In the KslMC simulations we can observe island nucleation and, consequently, we can investigate the interaction between the difects (islands) and the steps. We find that the defects can reduce the local step velocity inducing step bunching and, in the worse cases, leading to micropipes and carrots. Specifically, in our simulations we have observed that, if the step reaches an island having the same symmetry, a fast reconfiguration of the island particles to the step structure occurs. This increases the lateral roughness of the step potentially leading to LSB (see Fig.3, top). Instead, when the step reaches an island of complementary symmetry two scenarios are possible: either the step imposes a modification on the island type to

Monte Carlo study of the formation and evolution of defects in the growth of SiC

79

Figure 7. Kinetic particles (i.e. both defects and adatoms) resulting from a polycrystalline growth of 150 layers, both local (A) and extended (B) defects are present. The influence of extended defects on the surface is shown (C). The system has a surface made up of 864×864 sites (refined lattice) distributed over 52 flat terraces, respectively, 18 units wide.

reproduce its stacking sequence, i.e. “healing” the defect, or, if the island is too big and consequently too stable, it wraps around it. In the latter case the islands can potentially initiate the vertical growth of a local fault in the stacking sequence (stacking fault generation) and, eventually, generate an extended polycrystalline structure. In both scenarios the encounter strongly modifies the effective step kinetics causing a deformation of the step which, in turn, favors the creation of other defects in the surface. This mechanisms is critical in the chase of large misorientation angles to correctly describe the step-flow to 2D-nucleation transition, as we will show in the next paragraph.

Defect nucleation The principal feature of our KslMC methodology is that it allows to obtain a direct evidence of the failure of the step-flow growth condition in terms of crystal quality or, equivalently, defects nucleation. Indeed, since the step flow growth controls the nucleation and the growth of islands with complementary symmetry with respect to that of the substrate which would lead to the formation of polycrystalline structures (i.e. defects), the mono-topolycrystalline transition corresponds to the step-flow to two dimensional nucleation transition. In order to coherently identify the transition, we need to define a critical islands density (cdefect) above which the proliferation of defects will be irreversible. We found that the critical deposition condition Grlim

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Massimo Camarda & Antonino La Magna

(KMC) is not significantly affected by the chosen value of cdefect, as long as this value is larger than the fluctuations (without loss of generality we have used cdefect > 0.02 [22]). The Grlim (KMC) values obtained, showed in Fig.1, as a function of the misorientation cut for a given choice of the energetic parameter can be used to calibrate and test the continuous BCF-like models. We used the value of Grlim (KMC) at = 1.3o degree of 4H[11-20] to calibrate and compare the results of the atomistic approach with the predictions of two types of Burton-Cabrera-Frank (BCF) continuous models to highlight the concurrent mechanisms described by the KslMC with respect to the simpler description given by the continuous models. Furthermore, we applied the KslMC methodology to investigate the possibility to recover polytype conversion, from the hexagonal to cubic polytype (defect engineering).

Continuous models In the continuous models of step flow growth atoms are uniformly deposited with a deposition flux Fdep on a stepped crystal substrate. The steps velocity is assumed sufficiently slow so that, the steps, terminating the terrace at ±Tw/2, can be considered stationary (i.e. no convection term [37], due to fast step motion, is included). It can be easily demonstrated that, consistently to these hypotheses, the steady state adatom density profile can only be effected by the presence of mobile clusters. Considering this result we have generalized the standard BCF model by means of the inclusion of the formation/dissolution of mobile dimers, i.e. assuming zero diffusivity for any cluster larger than a dimer. Following Refs. [38,39] we denote the adatom and dimer densities by n(x) and N(x) and the corresponding flows by j(x) and J(x). The stationary state of the growth can be described by the following set of coupled, non linear, differential equations [40]: j ( x) x

J ( x)

n( x )

2

dep

J ( x) x j ( x)

2z

F z

DA DD

dif

n( x ) x N ( x) x

1

dif

DA DD

e

En / kbT

N ( x)

dif

n( x ) 2

n( x )

dep

2

n( x ) 2

e

En / k BT

N ( x)

3.1

dif

hop

exp( 3EB / k BT ) /

hop

exp( 4 EB / k BT ) /

where z and ρ are the surface parameters representing the number of neighbors and the surface density, σ is the capture number i.e. the probability,

81


for two 1 dif

neighbor adatoms, to form a dimer.

dep

=

/F and

hop exp( 3EB / k BT ) are the characteristic times describing the deposition

rate and the adatom surface diffusion respectively, 3EB is the energy barrier for adatom diffusion, En is the dimer binding energy. The second and third terms of the right hand side of Eq.(2) represent the nucleation of the adatoms to form dimers, whereas the fourth term represents the increase of the adatom density due to the dissolution of the dimers. Evaporation of either adatoms or dimers is neglected. The last two equations represent the Fick’s law applied to the adatoms and dimers. Where DA and DD are the diffusion coefficients of adatoms and dimers respectively which are connected to the bond strength EB to be consistent with the Monte Carlo simulations [40]. The parameter [0,1] incorporates the complex paths leading to dimer diffusion. The results are almost independent of this parameter, so we can set = 1. As already noted in the introduction, the continuous models have one unknown variable, the concentration ncrit (or the related Grlim value), above which two dimensional nucleation occurs, i.e. the SF-to-2DN will occur when nmax, as determined by Eq.3.1, will be greater than ncrit, a value which cannot be defined within the theory. We used the KslMC simulations, evidencing a sharp SF-to-2DN transition for large terrace widths, to set the critical conditions. Specifically, we used the Grlim(KMC) at the misorientation cut = 1.35o (equivalent to a terrace widths of 40a, where a is the inter-site lattice distance), see Fig.5 caption. In Fig.8 we show the results of this comparison, we have included also the fit for the standard BCF model, i.e. without dimer formation, which can

Figure 8. Effect of the misorientation angle on the growth rate limit.

82


be obtained from Eq.(2), keeping only the first term on the right hand side of the equation. In the latter case Eq.3.1 can be solved analytically and we obtain the following equation defining the deposition limit Grlim: Grlim

4[Tw2

2Tw / h](ncrit DA )

As it can be seen in Fig.5, the agreement between the predicted deposition rate limits (Grlim) is limited only to small misorientation angles (below 3°) (for both continuous models considered), whereas, for larger angles, the two continuous theories predict un-physically large values of Grlim (one order of magnitude higher than the experimental values of ~ 120 µm/h [41]). A reason for this discrepancy is that, as shown in the previous paragraph, in the regime of large off-angle cuts, the surface instabilities play a central role on the on-set of two dimensional nucleation altering the standard description of the transition and rendering the BCF theories unable to correctly predict the growth rate limit, i.e., in this regime, the steps cannot be considered any more as straight and isolated objects. More generally, this hypothesis cannot be considered valid whenever the roughness of the steps (the root mean square value, RMS) becomes of the same order of magnitude of half the terrace width (i.e. when Rstep = (2 RMS) /Tw ~ 1). In order to validate this idea we have calculated this ratio in terms of the off-angle cut applying the KslMC simulations (Fig.9). As we can see, the region of validity of the continuous models and the region for which RStep < 1 completely overlap. This analysis demonstrates that, indeed, the region of validity of the BCF-like theories (as determined in Fig.1, i.e. below ~ 2.5 degrees) is the one for which RStep < 1. This fact is also confirmed by the surface morphologies of grown crystals near the SF-to-2DN transition for different terrace widths. As it can be seen in Fig.3, for small terraces there is a strong step-to-step interaction which cannot be, inherently, modeled by means of the BCF-like description (which is based on ideally straight, isolated, stationary steps) independently of the nucleation theory used for the calibration. We have also compared the Grlim value in terms of JA = ED/kBT or, equivalently, in terms of the system temperature T or material property EB. Specifically we have compared the RF = Grlim (2 0) / Grlim ( 0) value for different values of JA fixing the misorientation cut to 0 = 4o. Both the standard and the refined BCF theories predicts RF = (2 0 / 0) 2=4, independently of JA and of the value of 0, whereas, in the case of the homoepitaxial growth of Silicon Carbide, grown through chemical vapor deposition, the experimental value is ~ 1.2 [41,42]. The inset of Fig.9 shows the KMC results. As it can be seen, in the case of the atomistic simulations,


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Figure 9. Left) Dependence of Rstep = (2 RMS) / Tw in terms of the substrate geometry (off-angle). The region of validity of the BCF theory is shown. The simulation parameters are the same of Fig.5. The inset shows the dependence of RF = Flim (2 0) / Flim ( 0) in terms of JA = ED / kBT for = 4o. The BCF-limit (i.e. RF = 4 can be obtained for low values of JA and cuts with small misorientation angle (i.e. large terrace widths). Right) Snapshots of portions of grown surfaces for two different terrace widths close to the SF-to-2DN transition (Tw/a = 20 and Gr = 66 m/h, upper panel and Tw/a = 6 and Gr = 66 m/h lower one. The terrace with (Tw) before the growth is shown.

RF(KMC) changes with JA converging to the continuous result for higher temperature and “soft” semiconductors (small values of EB). The value J A* at which RF(KMC) depends on the misorientation cut α. More specifically J A* is an increasing function of α, and, as can be deduced from Fig.1, J A* ( 2 ) 3.5 . Finally, we would also like to stress the fact the two continuous theories cannot fit the numerical data in the full range of off-cut angles independently of the diffusion coefficients of the adatoms and dimers or the system temperature. This shows that the origin of the discrepancy between the BCF and the experimental (and Monte Carlo) results does not depend on the inclusion of nucleation events within the continuous theories but, rather, on the specific evolution of the moving steps, which is beyond the capabilities of any 2D step-flow model.

Heteropolytypic growth In the previous section we investigated the deposition conditions, in terms of growth rate, to hinder the nucleation of defects i.e. to avoid the polycrystalline regime. On the other hand, has been recently experimentally demonstrated [43,44,45,46,47] that it is possible to generate a controlled

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nucleation of defects to induce polytype conversion, specifically to growth cubic SiC polytype on hexagonal substrates. However, despite extensive studies and experimental results, the exact mechanism leading to the complete and sudden formation of single domain 3C-SiC is not clearly understood. The general idea is that 3C growth starts with the nucleation of a more or less equal distribution of twinned and untwined (later called SiC-I and SiC-II, see Fig.1 and 10) domains at the β-/α-SiC interface (on the (0001) terraces), this random nucleation prevents a sharp interface and leads to low quality films (Fig.10). Small miscut angles favors 2D nucleation and are supposed to promote polytype transformation, for this reason most of the experimental results have been carried out on nominally on-axis substrates. We used the KslMC code to investigate the how the substrate properties, specifically polytype (4H and 6H), initial surface morphology (with or without step bunching) and miscut angles, influence the initial nucleation and the subsequent evolution of the 3C–SiC islands. We found (Fig.11 and ref.[48]) that a proper surface preparation of misoriented 6H substrate, aimed to promote controlled step bunching, can lead to a stable configuration of only one exposed layer type (Cubic left or right, see Fig.1). This surface morphology favors only one type of 3C-SiC, leading to single domain 3C crystals. Furthermore, we found that extension of the 3C conversion region strongly depends on the misorientation of the substrate increasing for large miscut angles. This is an unexpected result, given the fact that misoriented substrates are generally used to promote the homopolytypical reproduction of the substrate. This behavior, which is very important from a technological point of view can be explained considering the density and distribution of nucleated islands for the different miscut angles and growth rate considered.

Figure 10. Hetero-polytypical growth of 3C on 6H polytype. The substrate is a 4° degree off misoriented, silicon face, 6H polytype with ideal (step-bunch free) surface. Note the different 3C domains (called I and II) nucleated on the different terraces. Red arrows indicate the annihilation of a 3C-II domain in favour of 3C-II neighbouring ones.

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Poly A)

RLR=0.06eV

B)

RLR=0.08eV

C)

RLR=0.12eV

3C-G. S.F.

Figure 11. Different growth regimes (polycrystalline growth (Poly), 3C-SiC single domain growths (3C-G.) and step flow growth (S.F.) for different growth rates and miscut angles of the substrate. Long range interaction term varies between 0.06 eand 0.12 eV.

Indeed, for small miscut angles, we have, in the 3C-G. is regime, a generation of large, stable, islands which compete with each other (through merging and Ostwald ripening) and with the steps. If the deposition rate is sufficiently low nucleation leads to well aligned 3C islands and to the generation of single domain 3C films. On the other hand, for large miscut angles, i.e. for a high density of surface steps, the distribution of nucleated islands, which are laterally confined by the steps, which acts as perfect sinks[49], will be mainly composed of many small, unstable, clusters with fast kinetics. These cluster will rapidly interact with each other and with the steps. This fast kinetics and competition leads to the generation of 3C films for a large range of growth rates. The range of 3C growths corresponds to the defective step-flow or, equivalently, to the local step bunching regime. The extension of this regime, as shown in Par.II increases increasing the miscut angle, this explains the large process window for the large miscut angles. For these reasons, the use of a misoriented 6H-SiC substrates with a large ([4°-10°] degree off) miscut angles and a proper pre-growth process, that leads to a full step-bunched surface, can be the key for the growth of high quality, twin free, 3C-SiC films.

Defects propagation In the previous paragraph we have analyzed the different growth mechanisms: pure step flow, defective step flow, polycrystalline and 3Cconversion on the basis of the deposition conditions and substrate properties. All these analysis focus on defects nucleation whereas, another important feature of our KslMC code, is the capability to selectively include defects directly into the substrate and analyze their behavior during the growth, i.e. to

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Figure 12. Evolution of a SL-SSF defect. The different colors represent the three different particles sites: A, B and C. (top) the initial configuration of the substrate, Lbox and Linit are, respectively, the computational box and the initial defect extension along the [-12-10] direction, (bottom) the system after a short-time evolution. The presence of the defect is visible underneath the surface.

Figure 13. (top) Comparison between the crystallographic structure of a defect-free crystal (left) and a crystal with a single-layer stacking fault (right), as seen from the zone axis. (bottom) Schematic evolution of the two defects as seen from the surface. The plus (+) and minus (-) signs indicate the kinetics of the steps on the basis of their local crystallographic structure. Specifically, the (+1,-1,+1,-1) and the (-1,+1,-1,+1) defects expose different step configurations at the surface. This fact will lead to different behaviors.


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Figure 14. Plan view of the growing defect for different growth rates. The dislocation cores tend to be aligned to the [11-20], equivalent, directions. We note that, at the slower growth rate of Gr = 5 m / h the defect never closes, i.e. the defect length Ldef exceeds the computational box.

analyze the mechanisms behind defect propagation rather then defect nucleation. This aspect is crucial because it is known that the substrate (either 4H or 6H) can be highly defective so that the limitations on the growth of high quality epilayers can reside on the propagation of the defects rather than their nucleation. Using the KslMC code we have simulated the homoepitaxial growth of a 4H-SiC polytype with steps either perpendicular to the [11-20] and [1-100] directions (i.e. corresponding to miscuts towards the [11-20] direction, the standard one, and towards the [1-100] direction). In contrast with the previously presented results, we consider defective substrates containing staking faults (Fig.12) and evaluate their evolutions in terms of the growth conditions and staking fault type (see ref.[5] for a description of the main SFs observed in 4H epilayers). We find that, in dependence of the deposition conditions, the defects can either extend throughout the entire epilayer (i.e. extended from the substrate up to the surface) or close in dislocation loops. This different behavior can be explained in terms of a surface kinetic competition between the defect and the surrounding crystal: if the local growth rate of the defect is larger compared with that of the perfect crystal the defect will expands, otherwise it will closes. We begin by considering the miscut direction because, as shown in par.II, in this direction the exposed steps have a periodically sequence of different crystallographic

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structures so it possible to clearly identify a correlation between the behavior of the defect and the, altered, step kinetics.

Evolution of stacking faults for miscut direction We start our analysis from a 4H-SiC, silicon face, 8° degree off misoriented substrate containing one (+1,−1, +1,−1) stacking fault (Hagg’s notation [5], see Fig.2 top, left). This defect can be generated by two opposite shears of the crystal along the [1-100] shear direction. Only two, nonequivalent, SL-SSFs exist in the 4H polytype: the (+1,−1, +1,−1) and the (−1, +1,−1, +1), see Fig.13, top. These defects can be referred as a “single layer Shockley-type stacking fault” (SL-SSF), having an extension of one single bi-layer along the direction normal to the basal plane ([0001]). In Fig.12 the final, i.e. post growth, morphology of the defect, as seen from the [0001] zone axis (i.e. in plan view), is shown. Note that the initial extension of the defect along the [12-10] direction (Linit) and the misorientation cut of the substrate (α = 8°) are the same for all the simulations. Specifically, Linit = Lbox/2 with this condition the extensions of the defective and non-defective regions (Lreg = Lbox − Linit) are equal (see also Fig.10). Furthermore, the range of explored Gr is below the step-flow to 2D island transition, i.e. below the growth rate limit Grlim ( = 80 ) ~ 120 m / h) [50]). As can be seen in Fig.14, the length of the defect on the basal plane (Ldef) decreases by increasing the growth rate (Gr), which means that the propagation of the defect can be hindered by increasing (not decreasing, as one would expect based on the intuitive idea that low deposition rates are the key for high quality films) the growth rate. In Fig.15 we extend this analysis to study the impact of the miscut angle and temperature on the propagation of the SL-SSF, finding that the extension of the defect along the [0001] direction (L0001 = Ldef sin( )), which is directly related to the density of the defect on the film surface, increases for increasing miscut and temperatures. These unexpected results can be interpreted in terms of a surface kinetic competition. That is, if the kinetic of the defect, i.e. its efficiency in capturing adatoms on the surface, is higher with respect to that of the surrounding steps the defect will tend to expand during the growth, otherwise it will shrink and, for long enough times, it will close into a dislocation loop (see Fig.14, bottom). The ratio between the lateral effective velocity of the defect and the lateral velocity of the surrounding steps, R = vdefect/vstep, specifies the evolution of the defect during the growth. In general, R depends on the


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Figure 15. Defect extension along the [0001] direction (L[0001]) as function of the different deposition parameters.

crystallographic structure of the exposed surface and on the deposition conditions. For the specific defect considered, (+1,−1, +1,−1), we obtain R ≤ 1, for Gr 20 m/h. To verify the close connection between surface kinetic and defect evolution we studied the other SL-SSF in 4H, i.e. the (−1, +1,−1, +1) SF (see Fig.13, top, right). This defect has the same bulk structure of the (+1,−1, +1,−1) and, thus, the same bulk formation energy (∆H~ 30mJ/m2[2]) but exposes an opposite surface structure and, because of this, if the surface kinetics competition mechanisms is correct, we can expect to have an opposite behavior with respect the (-1,+1,-1,+1) stacking fault. The results of the Monte Carlo simulations, in terms of the defect morphology (Fig.17) and the Ldef (Gr,T) dependence (Fig.16), agree very well with this scenario. The connection between Ldef (or, equivalently L[0001]) and the SF-to-2DN transition can be strengthened introducing an effective “order parameter” = (Grlim – Gr) / Grlim and assuming a functional dependence for Ldef ≈ Ldef (θ) close to the transition. Then, we can expand Ldef (Gr, α, T) in terms of the order parameter and obtain [51]:

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Figure 16. Defect extension along the [0001] direction as function of the growth rate and temperature of the (-1,+1,-1,+,1) defect. (left) L[0001] for different growth rates, with T=1800°C and α=8°. The temperature parameter used to study the growth dependency has been increased to overcome the limits of the computation box used (i.e. to allow for defect closure). (right) L[0001] for different temperature with α=8° and Gr=50µm/h. Red lines indicate simulations for which the defect has exceeded the computational box.

Figure 17. Plan view of the two single layer stacking faults for the same growth condition. As can be seen, for the same deposition conditions, (top) (+1,−1, +1,−1) is a closing defect whereas (bottom) (−1, +1,−1, +1) is an expanding one.

Ldef Ldef

T

( Ldef

)(

Grlim )( Grlim

)

2 ( 0)(Gr / Grlim

0)( 0)

0

( Ldef

)(

Grlim )( Grlim

T)

2 ( 0)(Gr / Grlim

0)( 0)

0

The inequalities: Grlim/ > 0 and Grlim/ T > 0 are related to the properties SF-to-2DN transition with respect to the growth parameters and have been proven both numerically [51] and experimentally[52].


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These relations show that the defects, close to the SF-to-2DN transition can be divided into two classes: classI defects will tend to close near the transition (i.e. for out-of-equilibrium conditions: low temperature and high growth rates), whereas classII defects will tend to close away from it. The only basic assumption is that the defect induces a local different growth kinetics. In the specific case of the two SL-SSFs the different growth kinetics can be attributed to the different crystallographic structures of the exposed steps [53]. In the next section we will show that, in the miscut direction the long range term ELR is responsible for the splitting of the kinetics of the defect with respect to the defect-free crystal. Finally, it is worth noting that, in the case of hetero-epitaxial growths of 3C silicon carbide on (111) silicon both twins and stacking faults will have different crystallographic structures, i.e. different kinetics and will either tend to expand or close during hetero-epitaxial growths. Furthermore, their kinetics, being related to the local crystallographic structure, will be reversed when switching the growing surface from the (abc) growth plane to the (-a-bc) plane. This is the basic mechanism for stacking faults reduction within the “switch-back epitaxy” methodology [54].

Evolution of stacking faults miscut direction In the miscut direction, as presented in par.II the exposed steps have all the same crystallographic structure so that, to correctly describe the, experimentally observed, roughening of the surface we included the long range interaction term ELR which is responsible for a splitting of the adatom surface kinetics, and as a consequence of the step kinetics. This splitting of the step kinetics, influencing also the surface roughening, is also the key for the evolution of the staking faults in this miscut direction. In order to study their behavior we considered several types of SFs: (4,4) (6,2) (7,1) and (10,2) [2,3,4,5]. All SF types considered can be referred as “cubic inclusions” [5], i.e. they all expose a larger number of cubic steps on the surface compared to that present in the perfect crystal. As noted before, the crystallographic structure of the steps for miscut along the [11-20] direction is always the same so that the steps have a tendency to swing, generating a zig-zag feature (see Fig.4d) but they do not lead to a step bunched surface unless the long range interaction term ELR is considered. In Fig.18 the size (number of particles) of the defect during the growth is shown for different values of the ELR parameter in the case of the (4,4) stacking fault. As it can be seen, the defect initially propagates during the film growth (the defect extension increases with the film thickness) and then, suddenly, closes into a dislocation loop. This behaviour changes depending

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on the strength of the long-range interaction parameter ELR. This result can be ascribed to the lower diffusion coefficient for adatoms migrating on cubic layers with respect to hexagonal ones induced by a higher value of ELR. Indeed, this lower diffusion decreases the kinetics of the steps belonging to cubic layers. Since the (4,4) SF generates, on the surface, a sequence of cubic layers [4,5], by increasing the ELR parameter we effectively decrease the kinetics of the defect with respect to the surrounding perfect crystal. This unbalanced kinetics leads to the closure of the defect during the growth process [55]. The same behaviour (not shown) has been observed also for the (6,2) (7,1) and (10,2) “in-grown” stacking faults. It is noteworthy that the considered SF closes even for a ELR=0eV value. This is due to the specific growth conditions used for the simulations (high temperature, low growth rate) which increase the probability of defect closure, consistent with what experimentally found in ref. [51]. Considering the fact that the surface kinetics of all cubic inclusions ((1,3), (4,4), (6,2), (7,1) etc.) is governed by the single parameter ELR, and that by increasing this parameter the kinetics of the cubic steps decreases with respect to that of the hexagonal ones (being DH/DC = exp(ELR/kBT) all the cubic stacking faults, in misoriented films, will behave as classI defects. As a consequence, high growth rates and low temperatures can be considered the general prescriptions for the growth of high quality films, reducing all that stacking faults. These extended

Figure 18. Evolution of a (4,4) SF as function of the grown film (number of layers) for different values of ELR. The same qualitative behaviour has been found also for the (6,2), (7,1) and (10,2) SFs.


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defects, by generating intra-gap levels inside the 4H band structure, lead to carrier trapping and act as recombination or scattering centres degrading the overall transport properties of the films.

Conclusions This work meets a requirement; i.e. the comprehensive extension of the kinetic simulations dedicated to epitaxial growth of close packed crystalline structures with an extensive applications to the 4H silicon carbide one. The motivation was the observation that, in spite of an accurate mapping of the energetic, conventional kinetics approaches can address only single or limited aspects of the complex phenomenology, characterizing these growth processes. This is a structural limit of other simulation approach and we can overcome it only releasing the restriction of using the conventional lattice of the material in study as the reference lattice of the stochastic method. Indeed, we have demonstrated that, for the case of hexagonal silicon carbide, we can formulate an efficient and reliable kinetic Monte Carlo on superlattices (KslMC), by including in the, refined, lattice all the three category of highly symmetric sites (usually called A, B, C) which characterize the one dimensional stacking of the close packed lattice. Our code aims at investigating all the concurrent aspects characterizing the microstructural evolution of the system (island nucleation, correlation between the evolution of islands with different symmetry, correlation between the island and step evolution, interaction between bulk and surface structures) on the

Figure 19. Summary of the connections between deposition conditions growth mechanisms and defect typologies, as deduced by the KslMC simulations.

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correct time scale of the process. Specifically, the impact of the islands nucleation, which preferentially occurs in system with large terraces in the high deposition regime, is correctly evaluated since islands of the two symmetries complementary to the terrace could nucleate and evolve. Islands with the same symmetry of the step do not alter substantially the step effective kinetics since they are easily incorporated by the step. The encounter between the step and islands with different symmetry strongly modifies the effective step kinetics, although the interaction between the two structures tends to change the symmetry of the adatom bounded to the island. Indeed, the encounter event could cause a strong deformation of the step (in the case of relatively small islands) or the stabilization of a region with complementary symmetry (in the case of large islands) on the exposed terrace and the consequent growth of a polycrystalline structure. Besides islands nucleation we demonstrated that our approach allows also to consider the other mechanisms, namely the Global Step Bunching and the Local Step Bunching, which can lead to a progressive deterioration of the epitaxial quality of the growing films (eventually leading to a fault in the stacking order). The point like (LSB) and the extended (GSB) encounter between two or more adjacent steps show the proper morphological character and can be investigated in dependence of the substrate geometry and the deposition conditions. Their relevance is proper of the wide angle (small terrace) substrate geometry. However, maybe the more relevant feature of our code is the concurrent access to all the degradation mechanism of the stacking order so that the correlation between, island nucleation, LBS and GSB can be rightly investigated (e.g. GBS event could lead to the enlargement of some terraces boosting island nucleation, or nucleation events of small island can deform the steps, boosting LSB and so on). Finally, we can also characterize the generation of point like defects, denoting the Defective Epitaxial Growth Regime, which is a fundamental parameter for the quality of the experimentally grown epitaxial films. Fig.19 shows a summary of the simulation results.

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5. Epitaxial growth on on-axis substrates A. Henry*, S. Leone, X. Li, J. Hassan, O. Kordina, J.P. Bergman and E. Janzén Department of Physics, Chemistry and Biology, Linköping University SE-581 83 Linköping, Sweden

Abstract. SiC epitaxial growth using the Chemical Vapour Deposition (CVD) technique on nominally on-axis substrate is presented. Both standard and chloride-based chemistry have been used with the aim to obtain high quality layers suitable for device fabrication. Both homoepitaxy (4H on 4H) and heteroepitaxy (3C on hexagonal substrate) are addressed.

Introduction Silicon carbide (SiC) is a strong candidate to fulfill the severe demands for several kinds of high functional semiconductor devices such as high temperature, high power and/or high frequency electronic devices. Bulk material can be prepared with e.g sublimation. However, the quality and purity of the crystal is not at a level requested for the active layers of devices. An epitaxial technique is thus needed for the realization of such layers. The most advance technique today to achieve the various types of high quality SiC layers needed in all electronic applications is Chemical Vapour Deposition (CVD). Already in the end of the sixties, before the invention in bulk growth of the seeded sublimation technique [1], epitaxial growth on small Lely platelets demonstrated the possibility of homo-epitaxy but only at temperatures higher than 1750 °C [2]. This was reported only when using 6H Correspondence/Reprint request: Prof. A. Henry, Department of Physics, Chemistry and Biology, Linköping University, SE-581 83 Linköping, Sweden. E-mail: [email protected]

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polytype as substrate, to the best of our knowledge. At lower growth temperatures (typically below 1500 °C) the 3C polytype of SiC is more thermodynamically stable [3] and twinned crystalline 3C epilayers were obtained during epitaxy. When large area 6H-SiC crystals obtained with seeded sublimation became available, homo-epitaxy could be performed in the temperature range 1400-1500 °C using 3° - 6° off-oriented substrates. This technique named “step-controlled epitaxy” [4, 5] was a breakthrough for the SiC technology. The high density of steps on the surface increases the probability for incoming atoms to maintain the desired stacking sequence [4]. Epilayers of very high quality and with controlled doping suitable for device fabrication were obtained. Substrates of the 4H polytype became available later and rapidly showed better properties than 6H for many applications, the epitaxial growth was found to be more sensitive to defects and polishing damages. A slightly higher growth temperature as well as a larger off-angle (typically 8°) to reduce the terrace widths, was proposed to decrease the possibility of 3C nucleation; this is mainly due to the fact that larger terrace width characterizes the 4H polytype compared to the 6H and this fact increases the probability to get 3C formation on the terraces through a twodimensional nucleation. A complete review regarding “step-controlled” epitaxial growth can be found in ref [5]. However, as it will be described more in detail below (section 3), the growth on those off-oriented substrates leads to severe problems when used for the fabrication of SiC bipolar devices. Thus the possible “re-introduction” of epitaxy on nominally on-axis substrate today gathers researcher’s interest. Homoepitaxial growth on on-axis C-face 4H-SiC was achieved with good yield when using low C/Si ratio over a whole 2 inch diameter wafer [6]. Compared with Si-face, the C-face material has better polytype stability. However, higher n-type background level and difficulty to control very high p-type doping are the main drawbacks and therefore epilayers grown on C-face are not suitable for device applications. The first attempt to re-investigate the use of Si-face on-axis material for homo-epitaxy was done with 6H polytype and the substrates were only “nearly” on-axis since the off-angle was typically 0.2 - 0.3° [7]. Few works where Si-face 4H polytype was used as substrate, for our knowledge, using CVD technique, are found in the literature; the first presented a study on mesa growth, thus very thin layer on very small area [8] and in a second study morphology after epitaxial growth was reported using different SiC polytypes [9]. In both cases the minimal off-axis was 0.2°. Growth of thicker epitaxial layers has also been successfully shown on 4H C-face and 6H Si-face, while attempts on the 4H Si-face showed large problem with polytype stability and only about 50% stable area was achieved [10].

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The first large scale 100% 4H on-axis homoepitaxial growth on Si-face was shown on 2-inch 4H-SiC substrate [11]. In-situ surface preparation in Si-rich conditions prior to the epitaxial growth on mechanically polished substrates together with slightly higher growth temperature was shown to be the key process to avoid the formation of 3C-inclusions [12]. Regarding hetero-epitaxy (growth on 3C on 4H substrate) and using CVD, the main reported investigation was again on mesa [13]; other works used 6H as substrates [14, 15]. After a description of the experimental techniques the growth of nominally on-axis will be presented and discussed both using the standard chemistry during the CVD process and with the chloride based chemistry. This will be discussed first for the homoepitaxy of the 4H polytype. However the growth of 3C on hexagonal Si-face substrate will also be addressed. At the end of this chapter we present the first device results obtained using epilayers grown on on-axis substrate and propose future aspects for the epitaxial growth of SiC.

Experimental In the Hot-Wall Chemical Vapor Deposition (HWCVD) [16, 17] process reactive compounds (precursors) are transported by a carrier gas (typically hydrogen) to a hot zone (growth temperature as high as 1550-1600 ºC) where the precursors will thermally decompose into atoms or radicals of two or more atoms which may diffuse down onto a substrate and produce an epitaxial film. In this process there are several complications: the precursors and carrier gas must be correctly chosen, the flow of the gases must be laminar and the material used for the hot part of the reactor must be chosen with great care in order not to contaminate the system. The growth is performed at reduced pressure typically 100 or 200 mbar. In our case the hot zone is a graphite susceptor coated with SiC which is first heated to about 1200 ºC with only the carrier gas as ambient and then a second temperature ramp to the growth temperature is made which can differ depending on the chemistry used, as described in the next sections. No-rotation of the substrate is used in our CVD reactors. We use propane (C3H8) or ethylene (C2H4) as carbon precursor and silane (SiH4) for the silicon. Doping can be achieved by adding suitable gas during growth to obtain n-type or p-type conductivity. Control of conductivity (doping level and uniformity over the growth surface) is a key factor for the performance of electronic devices made from epitaxial layers. For the experiments with the standard chemistry a small addition of argon to the hydrogen carrier gas was used and propane was the carbon precursor [16, 17]. When using the chloride based chemistry ethylene

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was the carbon precursor; chlorine can be added to the CVD process in various ways as recently reviewed [18]. In our case HCl was added to the standard precursor (SiH4 and C2H4) or methyltrichlorosilane (MTS, CH3SiCl3) in the CVD process.

Homo epitaxy on nominally on-axis substrates The degradation of SiC p-i-n junction is now well documented and has shown to be due to the expansion of Shockley-type stacking faults along the off-axis basal plane in the part of the devices reached by the electron-hole plasma [19, 20]. The origins of the stacking faults are basal plane dislocations that are replicated from the substrate into the epitaxial layers due to the off-axis basal plane which is used to maintain the polytype stability during epitaxial growth [21]. Different approaches have been investigated to enhance the conversion of the basal plan dislocations into threading edge dislocations [22] at the epilayer/substrate interface; however those dislocations could also be harmful for devices. In addition, those approaches will introduce additional steps in the device processing including buffer layer growth which could affect cost and yield. An alternative way of avoiding bipolar degradation and epitaxial defects along the basal plane is to abandon off-cut substrates and instead grow epitaxy on on-axis substrates, where there will be no replication of dislocations or other defects along the basal plane [23]. A second aspect will be the lower cost of large-area substrates considering that the boule growth is done on on-axis material and an off-axis angle contributes to a large loss of material after cutting. Nominally on-axis (0001) substrates as supplied from manufacturers should not have any tilt from the basal plane, therefore epitaxial growth should in principle occur only via three-dimensional growth (islands formation at screw dislocation, and their expansion through lateral step growth at the islands walls). Indeed it often happens that on-axis substrates are not cut out of the crystal boule with no off-angle, even not intentionally, resulting in substrates with small off-cut varying from 0.05 to 0.5°. Besides, due to the growth process of SiC crystals which occurs at very high temperature, a crystal bending during the growth commonly occurs, resulting in a variation of the basal plane angle across the whole wafer area. Substrates often show tiny differences of the off-angle over the wafer area. This will affect growth mechanism as shown below and is evidenced by the morphology of the epitaxial layer [24]. When using on-axis substrates the polytype stability is thus difficult to maintain and typically can result in high concentration of 3C polytype inclusions. The origin of the 3C nucleation can be randomly distributed on

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the substrate and thus lower the effective usable area of the 4H material. At the growth temperature (typically 1500-1650 °C) the low diffusion length of the adatoms will favor the formation of 3C inclusions. The 3C formation is mainly due to surface damage from polishing [23] showing the importance of the in-situ preparation of the surface prior the growth. Fig.1.a shows a typical micrograph image of a small 3C inclusion as highlighted by the white circle (the other features observed are due to the various growth mechanisms of the 4H polytype as presented below). This type of inclusion can also be investigated by high resolution synchrotron white beam X-ray topography as shown in Fig.1.b [24]. High density of basal plane dislocations (BPDs) is revealed at the interface between the 3C and the 4H polytype; BPDs are suggested to appear during epitaxial growth in order to compensate the lattice mismatch between the both polytypes [23]. A simple and rapid technique to visualize polytype inclusions in materials is UV emission imaging. The wafer is illuminated with UV excitation using a defocused UV laser line in a liquid nitrogen bath. An example is shown in Fig.2.a for an early epitaxial layer where the black areas correspond to 3C–inclusions while the remaining clear areas are 4H polytype. Fig.2.b shows the possibility to obtain 100% 4H polytype on full wafer. A very important part of this achievement beside the probable improvement of the substrate polishing by the supplier, is the in-situ surface preparation prior to the epi growth on nominally on-axis 4H-SiC substrates and the control of the growth parameters. Depending on the growth process (possibility or not to have chloride in the system) different approaches have been tested. a)

b)

500 µm Fig.1: a) Optical image from an as-grown epitaxial layer grown on Si-face nominally Figure a) Optical image from 3C an inclusion as-grownhighlighted epitaxial layer on Si-face on-axis1.4H-SiC substrate showing in the grown white circle. The 2 nominally on-axis 4H-SiC substrate showing 3C inclusion highlighted in the mm white thickness of the layer was 10 µm. b) SWBXT image (corresponding to 2x3 ) circle. The thickness of the layer was 10 µm. b) SWBXT image (corresponding to showing 2 an inclusion of 3C in a 4H-SiC epitaxial layer. The network of lines around 2x3 mm ) showing an inclusion of 3C in a 4H-SiC epitaxial layer. The network of the 3C inclusion shows basal plan dislocations. lines around the 3C inclusion shows basal plan dislocations.

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Homo-epitaxy with standard chemistry In situ surface preparation As received epi-ready substrates are known to have surface damages which could be related to polishing or bulk imperfections. This is confirmed by careful investigation of the substrate surface with atomic force microscopy (AFM) in tapping mode showing damages in form of shallow or deep pits and scratches on the surface [12]. Most of the studies reported in the literature for in-situ etching have been done using off-axis substrates. Etching at high temperature with pure hydrogen, which is used as carrier gas, has served as pre-treatment of the substrate prior to the growth to remove surface imperfections. Moreover optimal in-situ etching conditions are generally obtained by adding propane to the hydrogen flow when using 8° off Si-face 4H-SiC substrates. This leads to the removal of polishing scratches without leaving any traces of silicon droplets [25]. For on-axis 4H-SiC surface, C-rich condition did not help to avoid the formation of 3C inclusions and resulted in mixed polytypes [23] as illustrated in Fig.2.a. A systematic study comparing the effect of various etching conditions has been carried out including in-situ etching under i) pure hydrogen ambient, ii) C-rich condition (H2+ C3H8) and iii) Si-rich (H2 + SiH4) on Si-face 4H-SiC [12]. Both tapping mode AFM and Normarski imaging were used to characterize the surfaces. The optical images obtained on treated SiC surfaces at 1560 °C and 200 mbar for 20 minutes are displayed in Fig.3. The a)

b)

Fig.2: UV polytype maps taken under UV illumination at 77K from two full 50 mm Figure 2. UV polytype maps taken under UV illumination at 77K from two full 50 diam. epi-wafer with a) early CVD process and b) improved in-situ and CVD process. mm diam. epi-wafer with a) early CVD process and b) improved in-situ and CVD The black areas visualize the 3C inclusions, whereas the clear areas are from 4H-SiC process. The black areas visualize the 3C inclusions, whereas the clear areas are from material. 4H-SiC material.

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Fig.3: Optical images taken from Si-face (0001) substrate after etching for 20 min at Figure images taken b) from Si-face substrate after etching for 20 min 15603.°COptical in a) pure hydrogen, C-rich and c)(0001) Si- rich conditions. at 1560 °C in a) pure hydrogen, b) C-rich and c) Si- rich conditions.

polishing related damages are removed by these processes. Heavy stepbunching and preferential etching at defects originated from the substrate are observed and are due to the high surface energy of the Si-face. In addition the surface step structure is found to be dependent on the ambient etching. Pure H2 etching results in irregular, zig-zag macro-step structure. Using in-situ etching with C-rich conditions irregular macro-steps are also observed, but with discontinuity and rather high surface roughness. For on-axis 4H-SiC surface in-situ etching with Si-rich conditions is found to be the most effective way of obtaining low surface roughness and linear, uniform and periodic macro-step structure [12]. As mentioned before small local tilts in the basal plane or off-angles exist on the surface and are suggested to be the origin of the observed macro-steps. Furthermore, microsteps with unit cell heights are observed on the surface. Threading screw dislocations (TSDs) can intersect on the surface being the main source for the micro-steps. These micro-steps extend far away from the dislocation providing a continuous distribution of steps at the surface. In addition, Si-droplets which are expected when using in-situ etching with Si-rich conditions due to high over pressure of Si containing species in the gas phase were never observed in this study [12].

Starting growth conditions After the in-situ etching, the condition at the beginning of the growth is another very important parameter to understand and control. Most of the epilayer defects as the 3C inclusions nucleate at the interface substrate/layer and they continue to evolve during the epilayer growth [24]. An abrupt change in the gas phase can enhance defect formation. During the surface preparation a negative growth mode (etching) occurs which should be changed to positive growth mode by adding the precursor. This step may cause the formation of defects if not done in a proper way. A very slow and

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gradual change in the gas phase has to be applied. Supersaturation is the driving force for both nucleation and layer growth. Moreover it should be as low as possible in the case of homo-epitaxy of 4H-SiC on on-axis substrate. This is to avoid the two dimensional nucleation of the unwanted 3C polytype. The precursors have to be introduced into the growth chamber with very small flows which slowly and progressively are increased to the desired value for the growth. This operation, starting of the growth, typically takes 20 minutes [11]. The initial growth rate is thus extremely low but allows the nucleation of only 4H material (few hundred of nm), and it can be increased to about 3-4 µm/h for the main part of the epilayer growth. The C/Si is, in our case, always very close to 1 during this operation.

Growth mechanism Epitaxial growth occurs always at steps, when it is not due to a two dimensional nucleation. On the same substrate we could observe for the first time two different types of growth mechanism [11]. Both of them appear at steps but having different heights. When the substrate is nearly on-axis the only steps available are related to the TSDs, as described before. It is on those steps that the growth will occur and it defines as spiral growth. Illustrations are given in the inset of Fig.4.a and Fig.4.c which are tapping mode AFM images taken from a Si-face epilayer grown on on-axis substrate. The spiral growth mode is characterized by the observation of smooth islands (Fig.4.a) and even large terraces (Fig.4.c) where the density of TSDs is supposed to be low. However when the basal planes are slightly off, with probably a very small angle as only 0.3°, the growth turns to step growth mode as for the intentional off-cut material, and large irregular steps, stepa)

b)

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Fig. 4:4.Optical Figure Opticalimages imagestaken takenononthree threedifferent differentlocations locationson onthe thesame same 10 10 µm µm thick thick epilayer grown grown on on nominally nominally on-axis on-axis substrate substrate showing a) very smooth epilayer smooth morphology morphology with mechanism and and c) c) withspiral spiralgrowth growth mechanism, mechanism, b) b) rough rough surface due to step growth mechanism very morphologywith withhigh highstep step due to spiral/columnar growth. The insets very rough rough morphology due to spiral/columnar growth. The insets show 2 show tapping 100 2 µm area with associated roughness of a) 4 nm, tapping mode mode AFM AFM 100 x 100 100 xµm area with associated roughness of a) 4nm, b) 1 nm b) 1 nm and c) 40 nm. and c) 40 nm.


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bunched surface, are observed. However on those large steps the surface is very smooth and covered with macro-steps (see inset of Fig.4.b). Mixing of these two growth modes is also observed. We observed that the surface roughness as measured with AFM increased with the thickness of the layer; typically for a 40 µm thick epilayers, macro-step height could reach over 100 nm.

Temperature effect As described before the 3C nucleation is favored by the low diffusion length of the adatoms on the grown surface. Increasing the growth temperature helps to enhance the mobility of the adatoms on the surface, lowering the probability for a two dimensional nucleation of 3C. Typically when the growth temperature used in our reactor was 1580 °C for epitaxy on 8° off-axis substrate, it was increased to 1620 °C for the growth of homoepitaxial layer on nominally on-axis substrate. Using the in-situ etching to obtain micro-steps on the surface together with a slightly higher growth temperature and an initial low growth rate, we were able to grow thick epitaxial layer with complete 4H polytype replication on a nominally on-axis substrate using the standard non chlorinated chemistry. This has been both on 50 and 75 mm diameter wafers (the latest corresponding to the maximum growth area on our reactor) and for 12 µm thick epilayers. For the smallest diameter substrates, epilayers with thicknesses up to 40 µm have been demonstrated with 100% 4H polytype (Fig.2.b as example).

C/Si ratio and growth rate effect After in-situ etching better surface morphology, meaning lower roughness of the surface, is achieved when using Si-rich conditions (see section 3.1.1). This behavior could indicate that Si-rich conditions during growth could also help to obtain lower surface roughness. The effect of the C/Si ratio on the surface morphology has thus been studied; homoepitaxial growth was performed using various C/Si ratio in the range 0.8 - 1.2. Outside this range 3C formation was easily observed in the epitaxial layer. Within this range of C/Si ratio, the roughness was found to decrease when decreasing the C/Si ratio. For an area of 100 x 100 µm2, roughness of less than one nm was obtained for 10 µm thick epilayers, whereas for thicker layer (35 µm) the roughness was around 2 nm. The roughness was thus found to increase with the epilayer thickness [26]. Low supersaturation at the beginning of the growth and thus very low growth rate were found to be necessary for polytype stability. With low

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growth rate increased probability of growth process related problem such as down falls from the susceptor ceiling is expected. This could give rise to perturbation of the growth and thus to 3C inclusions. As on-axis homoepitaxy is intended for high voltage bipolar devices, very thick (more than 50 µm) and low-doped (less than 1015 cm-3) layers are requested. High growth rate is simply needed. We succeeded to increase the growth rate from 3 µm/h to 10 µm/h by increasing the silane flow but also by decreasing slightly the process pressure, keeping 100% 4H homoepitaxy with roughness of 2 nm for a 100 x 100 µm2 area [26]. Higher growth rates led to very rough surfaces and 3C nucleation.

Chlorine based homoepitaxy for nominally on-axis material The importance of adding chlorine into a CVD reactor for the growth of SiC on on-axis substrates was investigated by Xie et al in 2000 [27]. Although 6H (0001) substrate was used, homo-epitaxy was demonstrated at 1475 °C; the addition of HCl during the growth (and not only prior the growth) was suggested to provide stepped surface where the step-controlled epitaxy could occur. The growth rate was found to slightly decrease (from 1.8 to 1.3 µm/h) when adding HCl to the process with a high HCl/Si ratio of 50. HCl was also reported to etch preferentially 3C- over 6H-SiC. However surprisingly, no work regarding 4H homo-epitaxy has been reported by the same author’s group or other, to the best of our knowledge. More recently chloride-based CVD for SiC has been proposed and used to achieve high growth rate on off-axis substrates [see a recent review in Ref.18]. The presence of chlorine is necessary at high growth rate to prevent silicon cluster nucleation in the gas phase, which usually occurs at high Si/H 2 ratios. Various chloride based chemistries have been used for SiC: i) adding HCl gas to the standard chemistry, ii) replacing the silane by a chlorinated silane molecule, iii) replacing the carbon precursor by a chlorinated carbon molecule, or iv) using a precursor which contains both chlorine, silicon and carbon (see ref [18]). Chlorine has been successfully used to achieve homoepitaxial growth of SiC also on on-axis substrates at rates of 100 µm/h as described below. Besides it has been found out that chlorine addition in the CVD process widens the operating window of parameters allowing such homoepitaxial process. Below follows a description of the main parameters which could be tuned to achieve a chloride-based process for the homoepitaxial growth of 4H- or 6H-SiC on (0001) substrates: in situ treatment; temperature; Cl/Si ratio; C/Si ratio; precursors, substrates off-angle and growth rate.


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In situ surface preparation The two most successful surface preparations suitable for the chloridebased process are based either on heating up in pure hydrogen atmosphere followed by very silicon rich growth conditions [28], or on the silicon rich in situ etching [29], similar to the case using non-chlorinated CVD process as described before [12]. In the first case ramping up in pure hydrogen is necessary simply to promote desorption of contaminations or oxide formed on the surface. Experiments with HCl in situ etching have been performed as well, but they have not been proved to be really beneficial for our process, contrarily to various reports in the literature [30]. In such a case, where no special surface treatment is performed, the growth parameters at the very beginning of the growth are critical for a successful homoepitaxial process. Since this process requires very silicon rich conditions in order to suppress those nuclei which could start the formation of any 3C inclusion, a very low C/Si ratio (down to 0.3), and very high Cl/Si ratio (up to 30) were required when growing at 1600 °C. A slow ramp up of the precursors (SiH 4 + C2H4 + HCl in H2) while keeping the proper ratios was mandatory to keep polytype control either on 4H or 6H-SiC (0001). In the second case SiH4 has been used for in situ etching of the on-axis surface. 10 minutes etching with a Si/H2 ratio of 0.12 % at the growth temperature of 1600 °C was performed. Such a preparation probably renders the surface silicon terminated, and modifies it in a way that promotes only two-dimensional growth starting from steps existing on the surface, due to either a small off-angle or to the presence of screw dislocations. In this way it is possible to use a wider range of C/Si- and Cl/Si-ratios, which are important to tune the growth mode, and to allow raising the precursor concentration in order to get a higher growth rate. Comparing the two etching procedures and the related growth conditions, the first procedure keeps a growth environment permanently silicon rich, but the high amount of chlorine produces a parallel etching, which is competitive to the growth. The second procedure creates the proper silicon rich condition at the very early stage of the process, making such conditions less critical during the growth process itself.

Temperature effect When silicon in situ etching is not used, very high Cl/Si ratios up to 30 are needed at 1600 °C to obtain homoepitaxial growth. At a higher temperature this ratio can be reduced (Cl/Si = 20 at 1680 °C) while still

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obtaining a 100% 4H homoepitaxial layer free of 3C inclusions, thanks to the increased polytype stability. With such conditions and a C/Si of 1.5 we demonstrated the growth of a 100 µm thick 4H-SiC epilayer. The high quality of this layer can be easily inferred from the low temperature photoluminescence (LTPL) spectrum showed in Fig. 5. The near-band gap emission was the dominant luminescence and contains mainly intrinsic (freeexciton) related lines and from this spectrum a net carrier concentration in the low 1013 cm-3 was determined.

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Photon Wavelength (Å) Figure 5. Photoluminescence spectrum a 100 µm thick 4H-SiC epitaxial layer grown

Fig. 5: Photoluminescence spectrum a 100 µm thick 4H-SiC epitaxial layer grown at at 1680 °C with a growth rate of 25 µm/h. The insets show first the near band gap 1680 °C with a growth rate 25 µm/h.(asThe firstnitrogen the near band gap emission with free-exciton lines of as dominant p.e.insets I77) andshow then the bound exciton related lines Q to be negligible (intensity increased with a x100 scale emission with free-exciton lines as dominant (as p.e. I77) and then the nitrogen bound 0 compared to the lines rest ofQ thetospectrum). The measurement was done with at 2K awith a scale exciton related be negligible (intensity increased x100 0 244 nm excitation laser. In the extended spectrum weak luminescence from the D 1 is compared to the restasoffrom theTispectrum). The measurementbeing was due done at 2Kin with a also observed as well related lines, Ti incorporation to crack 244 excitation laser. In the extended spectrum weak luminescence from the D1 is the nm susceptor coating. also observed as well as from Ti related lines, Ti incorporation being due to crack in Cl/Si ratio influence the susceptor coating. Epitaxial growths performed without special surface preparation or any low C/Si ratio process, have put in evidence how an increased amount of chlorine reduces the formation of 3C inclusions formed on an epilayer. As

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shown in Fig. 6, higher amount of HCl added to SiH4 and C2H4 reduces 3C inclusions, and even the use of a chlorinated precursor, such as CH 3SiCl3 (MTS), added with HCl can give 100% 4H-SiC homopolytypic growth [31]. This trend has been confirmed in several growth conditions on on-axis substrates, and it is explained by the change in gas-phase chemistry due to the presence of chlorine. Thermodynamic and kinetic calculations demonstrated that higher amount of chlorine lead to an increased formation of SiCl 2, which is the key silicon precursor formed in the gas phase to contribute to the growth. As discussed above, the main advantage of chloride-based CVD is the feasibility of achieving higher growth rates. Combining this process with the silicon-rich in situ surface preparation, a growth rate up to 100 µm/h was obtained [29]. a) Cl/Si=0

b) Cl/Si=5

c) Cl/Si=10

d) Cl/Si=6

Fig.6: 20 μm thick epitaxial layers at 77K illuminated by UV-light. Growth at 1600 Figure 6. 20 μm thick epitaxial layers at 77 K illuminated by UV-light. Growth at C with C/Si = 1 and a) Cl/Si=0; b) Cl/Si=5; c) Cl/Si=10; using SiH4+C2H4+HCl and 1600 0C with C/Si = 1 and a) Cl/Si=0; b) Cl/Si=5; c) Cl/Si=10; using SiH 4+C2H4+HCl d) MTS precursor withwith HCl HCl addition and Cl/Si=6. 3C-SiC inclusions appear appear as dark as and d) MTS precursor addition and Cl/Si=6. 3C-SiC inclusions 2 spots on the TheThe sample have have a areaanofarea about x 2020mm dark spots on samples. the samples. samples of 20 about x 20 mm2.

C/Si ratio effect As it happens for the epitaxial growth on off-axis substrates, the C/Si ratio is a determining parameter for the epitaxial growth since it affects directly the growth mode, and therefore the doping incorporation. Its required value to get an on-axis homoepitaxial layer depends on the other growth conditions but, as a rule of thumb, generally silicon rich conditions are usually preferred for the growth on on-axis substrates, since the 3C-SiC polytype is favoured by high carbon partial pressure. When higher growth rates are desired, the C/Si ratio should be generally kept below 1, unless chlorinated precursors such as MTS are used. The background doping is affected by this ratio as explained by the site-

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competition epitaxy theory, according to which higher C/Si ratios reduce n-type dopants incorporation [32].

The choice between various precursors The various chlorinated precursors can have a very different gas-phase chemistry, which has been demonstrated both from an experimental and theoretical (simulations) [18] point of view. For off-axis epitaxial growth MTS was found to be the most efficient precursor. Similar behaviour has been demonstrated for epilayers grown on on-axis substrates while keeping a total control of the polytype. As mentioned above, a growth rate of 100 µm/h has been demonstrated for the growth on 4H-SiC (0001) substrates, using MTS as precursor. The other parameters were: in situ etching with SiH4, T = 1600 °C, C/Si = 1, Cl/Si = 3, Si/H2 = 0.66%. The same result could not be achieved when using SiH4 + C2H4 + HCl.

Growth rate influence As a final example of the great potential of chloride-based CVD on onaxis SiC substrates, it is worth mentioning the outstanding results obtained in a vertical hot-wall CVD reactor using such a process [33] as an example of process tuning for high growth rates. Selecting as precursors either SiH 4 + C2H4 + HCl or SiHCl3 + C2H4 + HCl, the chloride-based process has made possible to grow up to 1 mm thick epilayer on 4H or 6H on-axis substrates with growth rate up to 350 µm/h at temperature of 1850 °C. At such high growth rates polytype stability gets more challenging; high Cl/Si ratio (5 – 10) and low C/Si ratio (0.3 – 0.5) were employed in this process, but difficulties with etching effect and 3C inclusion were eventually solved. In fact the amount of 3C inclusions increases with higher growth rates, but keeping a low C/Si ratio and increasing the Cl/Si proportionally helped to avoid them. Yet etching effect occurs at Cl/Si ratio of 10 or higher, therefore at moderate Cl/Si of 7, the use of a chlorinated precursor such as SiHCl 3 was the key to get growth rate at 350 µm/h.

Hetero-epitaxy on nominally on-axis substrates The growth of structures consisting of different SiC polytypes is a challenge for new applications such as resonant tunneling, but remains to be experimentally explored. The growth of 3C on on-axis grown 4H epitaxial layers could give device benefits with respect to MOSFETs (superior inversion channel mobility and reliability). In addition two-dimensional


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electron gas (2DEG) was predicted [34] to be formed at the hetero-junction 4H/3C or 6H/3C SiC due to abrupt change in spontaneous polarization between the cubic and the hexagonal SiC. However this challenge needs to resolve the problem with high defect level resulting from the heteropolytypical growth, such as twin-boundaries and, the growth of such structures demands different nucleation conditions for each of the polytype forming the structure. 3C layers can be grown on the most common SiC hexagonal-polytype substrates, which has been demonstrated by vaporliquid-solid (VLS) [35], sublimation epitaxy [36] and chemical-vapordeposition (CVD) [14, 15]. However, those studies have used mainly nominally on-axis 6H-SiC as substrate. The use of the 4H polytype seems thus to be an additional challenge. We will here describe the recent work using 6H as substrate and the chloride based chemistry as growth technique and then the standard chemistry using 4H Si-face on-axis substrate.

Hetero-epitaxy using 6H as substrate with chloride based CVD One of the main potential of chloride-based CVD is to prevent silicon nucleation in the gas phase which can occur either at high precursor concentration, or at low growth temperatures (below 1400 °C) [37]. This has been proved to be beneficial also for the growth of good quality 3C-SiC on hexagonal SiC substrates [38]. As discussed above, 3C-SiC is more thermodynamically stable at lower temperature (below 1500 °C), therefore it can be grown at temperatures lower than those used for 4H and 6H-SiC. In order to get 100% 3C-SiC on hexagonal SiC substrates, on-axis material is preferred, in order to favor islands growth. Chloride-based CVD has been tested mainly on 6H-SiC (0001) [39]. In our group we have found an optimal temperature window to grow 3C on 6H (0001) which is between 1300 and 1400 °C [38]. A higher temperature makes very likely the formation of 6H, while lower temperatures lead to lower crystal quality. Different surface preparations have indicated the importance of using carbon rich conditions, as already done when growing 3C on silicon substrates in the so-called carbonization process. Using other gases for the surface preparation, such as silane or pure hydrogen, brings more chance to get 6H, while HCl seems to be more favorable to 3C. Growths with different C/Si ratios and Cl/Si ratios have indicated that silicon rich conditions are ideal to get higher quality 3C. Cl/Si ratios between 3 and 6 were optimal for such process; higher values were detrimental from a growth rate and quality point of view. C/Si ratios from 0.6 to 0.9 were more suited to the process, because higher carbon inputs gave rise to defects, while lower carbon amounts gave rise to very high background doping levels. A final

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improvement to the process, necessary to favor single domain 3C to be formed, instead of the very common double-position-boundaries (DPB), was to add some nitrogen in the gas mixture, since it seems to stabilize one domain. 3C-SiC epitaxial layers almost completely single domain were grown at a rate of 10 µm/h using: C2H4 flow during temperature ramp up; T = 1365°C; C/Si = 0.75; Cl/Si = 6; and a small nitrogen flow. Small addition of nitrogen during the growth was proposed to help to stabilize the 3C-SiC polytype even when the growth conditions were not favoring the formation of 3C [40]. The material grown in this way was characterized optically and electrically. Electron back scattering diffraction (EBSD) was used to evaluate the presence of DPBs, indicating that the layers grown at the best conditions were 90% made of a single domain, as illustrated in Fig. 7. b)

a)

3C-2

3C-1 100 μm

50 μm

Fig.7: a) Optical microspcope image and b) EBSD images of a 3C epilayer grown Figure 7. a) Optical microspcope image and b) EBSD image of a 3C epilayer grown on-axis6H-SiC 6H-SiCat at 1365 . 3C-1 indicte the domains withpossible two ononon-axis 1365 °C °C . 3C-1 and and 3C-23C-2 indicte the domains with two possible orientations titled with 60°. orientations titled with 60°.

Hetero-epitaxial growth on 4H substrate by standard chemistry The substrates used here were n-type doped nominally on-axis 4H-SiC materials. In order to get lower net doping concentration, Si-face of the substrates was chosen for the growth. Standard chemistry (SiH 4 and C3H8), was used at a pressure of 200 mbar. Important growth parameters, such as temperature, C/Si ratio, starting-up condition, were varied to investigate their influence on the 3C formation. The growth temperature is one of the most important parameters that influenced the obtained epilayers’ morphology. After testing between 1200 °C and 1500 °C, 1350 °C was found to be the most suitable temperature for

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growing single domain 3C-SiC epilayer. When the temperature was lower than 1325 °C, the epilayer surface was carbonized and it appeared as dark brown. Polycrystalline surface was observed, when 1375 °C or even higher temperature was used. C/Si ratio equals 1 seems to be the best condition at 1350 °C. Silicon droplets or even clusters appear at C/Si ratio higher than 1.1 and below 1400 °C. Polycrystalline material appears when C/Si is less than 0.9. C-rich surface preparation was found to favor the growth of 3C layers. Two ways of starting-up conditions were shown to be useful to effectively reduce DPBs. One is to do an optimal time of in-situ etching right after reaching the growth temperature. The other method is to flow certain amount of C3H8 from room temperature to the growth temperature before introducing any Si precursors. The amount of C3H8 used during temperature ramp-up should be comparable with the flow used during growth. If the flow is not enough, the DPBs problem could not be solved. But too much of C 3H8 flow will cause even higher density of DPBs and also apparition of other surface defects probably carbon related. This is similar to the first method, which will lead to bad morphology for both too short and too long etching time. The growth rate varied from 2 to 6 µm/h, which was mainly governed by the SiH4 flow. Layers with thicknesses from a few micrometers up to 50 µm were grown. The sample with the best obtained results (see fig. 8) was grown on a 2x2 cm2 substrate at 1350 °C, 200 mbar with C/Si = 1 and 5 min in-situ etching with C ambient before growth and a small addition of nitrogen gas (N/C = 0.4 %). The stripes shown in this picture could be stacking faults [41].

50 µm

Figure 8. Opticalmicroscopy microscopy images at 400x magnification of 3C-SiC epilayers Fig. 8: Optical images at 400x magnification deposited at 1350 °C on (0001) 4H-SiC substrates with C/Si = 1, N/C4H= 0.004, Si/H2= of 3C-SiC epilayers deposited at 1350 °C on (0001) 0.015 % with 7 ml/min propane in-situ etching for 5 min. The epilayer thickness is SiC12 substrates with C/Si is=0.94 1, nm N/C 0.004, μm. The surface roughness in a=10x10 µm2 Si/H area. 2= 0.015 % with 7 ml/min propane in-situ etching for 5 min. The epilayer thickness is 12 μm. The surface roughness is 0.94 nm in a 10x10 µm2 area.

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This feature becomes more pronounced when the epilayer is thicker. EBSD technique confirmed that the whole layer was single domain 3C-SiC. The net doping concentration measured by Hg probe CV was 5x10 16 cm-3 at room temperature which was confirmed by LTPL. For most samples, the near-band gap emission was detected. No donor-acceptor pair recombination was observed, but weak D1 related luminescence was detected [42]. The RMS roughness examined by AFM was 3 to 8 nm at 50x50 µm 2 for most of the samples.

Device related issues As the main goal of this work is to obtain high quality layers suitable for device fabrication, first tests have been conducted for both homo-epitaxial and hetero-epitaxial material.

Homo-epitaxy material as device material A first complete device structure including a low doped n-type 30 µm thick active layer and a heavy p-type layer was grown without interruptions, and simple PiN diodes were processed, which showed stable behavior without bipolar degradation and stacking fault formation [43]. However no reverse characteristics were presented and the forward voltage drop was relatively high. More recently 600V PiN diodes were fabricated using on-axis material, the active layer being only 10 µm thick. [44]. Those diodes also showed stable forward characteristics without stacking fault generation and were compared with diodes done with the same device process but using offaxis material; stacking fault generation was rapidly observed as well as an important forward voltage drift [45]. However as the epitaxial growth mechanism on on-axis 4H SiC substrate includes both spiral growth and step growth mode, high roughness of the grown surface is observed on a very large scan with both the standard and the chloride based chemistry approaches. An example is given in Fig.9 where steps as high as almost 2 µm are observed for a 17 µm thick epilayers grown with the Cl based process. Similar results are obtained when using the standard chemistry process and on 100 µm thick epilayers steps as high as 7 µm have been measured. This will affect both the mesa thickness control and the PiN junction planarity during the processing of devices. This is the main reason why high mesas with a height of 8 µm were needed. Higher surface state density is suggested to decrease the resulted break down voltage [44]. Additional steps for the realization of the epilayer structures are thus needed; planarization of the active layer prior to the re-growth of the p+/p++ layers. If the latter (regrowth)

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Epitaxial growth on on-axis substrates 4000 2000 0

Height (Å)

-2000 -4000 -6000 -8000 -10000 -12000 -14000 0

200

400

600

800

1000

Horizontal length (µm)

Fig. 9:Figure Roughness of a 20ofµm thick growngrown on on-axis substrate andand measured 9. Roughness a 20 µmepilayer thick epilayer on on-axis substrate a surface profiler, (Dektak a view obtained with profiler. this with ameasured surface with profiler, (Dektak 6M). The 6M). insetThe is ainset viewis obtained with this profiler.

can be easily demonstrated as it was for off-axis material [46] and the first step (planarization) involving polishing and surface preparation is still a drawback. To resolve this problem the spiral growth should be avoid and very low off angle substrate would be the more appropriate substrate where only step growth mode will dominate the growth mechanism, as recently demonstrated [47].

Hetero-epitaxy material as device material Epilayers grown with the chloride based chemistry have been used for the fabrication of single Schottky diode. The epilayers were doped in the mid 1015 cm-3 range, very low leakage current of 1.5x10 -8 A/cm2 at a reverse voltage of -2V was measured on such layers. Deep level transient spectroscopy (DLTS) analysis showed higher quality material compared to 3C layers grown on silicon substrates, which instead showed a number of peaks related to deep level defects [48]. It should be noted that the epilayer thickness should be high enough, typically more than 10 µm, to reduce the DPB density. This could limit the interest of 3C as material for device application. High DPB density is equivalent to high probability to locate a device on grain boundary which leads to high leakage current and non-ideal”

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Schottky behavior [41]. In addition the defect density, mainly the stacking fault density should be reduced. Comparative studies using 3C epilayers grown with different techniques have proved that the epilayers grown with the chloride based chemistry have an order of magnitude less defect density than material grown with other techniques [49].

Conclusions Homo-epitaxy of 4H-SiC on nominally on-axis substrate is demonstrated using chemical vapor deposition with both the standard and the chloride based chemistry. The standard chemistry which was first applied, has rapidly shown the importance of the in-situ preparation and starting condition of the growth. This has been confirmed by the chloride based chemistry which in addition allowed higher growth rate. However due to high roughness of the grown layer, material with vicinal small angle (0.3 – 1°) should be tested for bipolar application. Hetero-epitaxy of single domain 3C on 4H-SiC on-axis substrate is also possible; the growth parameters window is however smaller when using standard chemistry compared to chloride-based CVD. To obtain single domain without double-position-boundaries thick enough layer is required, however more efforts are needed to decrease the stacking fault density and demonstrate the use of this hetero material in device application.

Acknowledgments The Swedish Research Council (VR 2009-3383) and the Swedish Energy Agency (project 32917-1) are gratefully acknowledged for financial support.

References 1. 2. 3. 4.

5. 6. 7. 8. 9.

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6. 4H-SiC epitaxial growth and defect characterization T. Kimoto, G. Feng, K. Danno, T. Hiyoshi and J. Suda Department of Electronic Science and Engineering, Kyoto University A1-301Katsura, Nishikyo, Kyoto 615-8510, Japan

Abstract. In the last decade, remarkable improvement in the material quality and understanding of defect behaviors in SiC have been made. In this paper, fast epitaxial growth and defect characterization of 4H-SiC are described. The growth rate was increased to 85 m/h by reducing growth pressure in a conventional SiH4-C3H8-H2 chemistry without morphology degradation. The net donor concentration of unintentionally doped epilayers is 5 1013 cm-3 or less. After micropipe elimination of SiC wafers, reduction of threading dislocations and basal-plane dislocations is essential to improve the performance and reliability of SiC power devices. These dislocations can be nondestructively detected by photoluminescence mapping at room temperature. In fast epitaxial growth (> 50 m/h), three types of in-grown stacking faults, (4,4), (5,3), and (6,2) structures, have been revealed in epilayers with a density of 0.5-5 cm-2. The Z1/2 center, which is located at 0.65 eV below the conduction band edge, was identified as the dominant lifetime killer in 4H-SiC. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1 1011 cm-3) by two-step annealing, thermal oxidation at 11501300oC followed by Ar annealing at 1550oC. The carrier lifetime was improved from 0.68 s (as-grown) to 9.5 s by the two-step annealing, and further increased to 13 s after surface passivation. Correspondence/Reprint request: Dr. T. Kimoto, Department of Electronic Science and Engineering, Kyoto University, A1-301Katsura, Nishikyo, Kyoto 615-8510, Japan. E-mail: [email protected]

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Introduction Power semiconductor devices have attracted increasing attention as key components in a variety of power conversion units. Realization of highperformance power devices will lead to enormous energy saving, conservation of fossil fuels and less environmental pollution. Because of the mature technology of Si power devices currently employed in most applications, it is now difficult to achieve innovative breakthroughs in this field. Newly emerging semiconductors such as silicon carbide (SiC) are attractive for advanced power devices, owing to their superior physical properties [1-4]. It should be noted that SiC is an exceptional wide bandgap semiconductor, doping concentration of which can be controlled in the wide range, more than five orders of magnitude, for both n-type (N or P doping) and p-type (Al doping). The figure-of-merit for power devices is given by EB3 (Baliga’s figure of merit) [5], where is the dielectric constant, the mobility, and EB the breakdown field. The figure-of-merit of SiC exceeds 500 when the value is normalized by that of Si, indicating much potential of SiC for power device applications. Owing to remarkable improvement of SiC wafer quality and progress in device technology, high-voltage SiC Schottky barrier diodes (SBDs) and field-effect transistors (FETs), which significantly outperform Si counterparts, have been demonstrated [6-8]. SiC SBDs have been on the market since 2001, and production of 600-1700 V SiC FETs has started in recent years. SiC power devices will become key components to realize significant reduction of power dissipation in a variety of power converters/inverters in the future. Through recent progress in SiC growth technology, four-inch 4H-SiC wafers with a reduced density of extended defects and free of micropipes are now commercially available. Epitaxial growth of high-quality SiC with uniform thickness and doping concentration is an essential technology for developing any kinds of SiC devices [9-15]. Although fundamental technology of 4H-SiC homoepitaxy on off-axis SiC(0001) substrates has been almost established, there still exist several important challenges in 4H-SiC homoepitaxy. Such challenges include homoepitaxy on nearly on-axis substrates [16-18], epitaxial growth on the C face [19-20], fast and thick epitaxy [21-25], and so on. Fast and thick epitaxial growth of SiC is especially important for developing very high-voltage SiC bipolar devices such as PiN diodes, thyristors, and IGBTs (Insulated Gate Bipolar Transistors). These SiC bipolar devices are promising for ultrahigh-voltage (> 10 kV) power devices, which can be employed for electric power infrastructures such as HVDC (High-

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Voltage DC) transmission and BTB (Back-to-Back) frequency converters. For these applications, however, very thick (> 100 m) and high-purity crystals with low defect density and long carrier lifetimes are required even with SiC. Table 1 shows the thickness and doping concentration of SiC voltage-blocking layers required for several typical voltage ratings, which was calculated from doping-dependent critical electric field strength [26]. Note that a non-punchthrough structure was assumed in this table, while a thinner epilayer with lower doping concentration is employed in a punchthrough structure. For example, about 100 m-thick epilayers with a background doping concentration of a low 10 14 cm-3 and a long carrier lifetime over 5 s are required for producing 10 kV SiC bipolar devices. In this paper, recent results on fast epitaxial growth of 4H-SiC and defect characterization obtained in the authors’ group are reviewed. Table 1. Thickness and doping concentration of SiC voltage-blocking layers required for several typical voltage ratings. Voltage-Blocking Region (SiC) Rated Voltage Thickness ( m)

Doping (cm-3)

1.2 kV

9.6

1.4x1016

1.7 kV

14

9.6x1015

3.3 kV

29

4.3x1015

4.5 kV

41

2.9x1015

10 kV

95

1.2x1015

20 kV

210

4.9x1014

Fast epitaxial growth of 4H-SiC Homoepitaxial growth was carried out on commercially available 8 o off-axis 4H-SiC(0001) Si-face substrates by using a custom-made horizontal hot-wall chemical vapor deposition (CVD) reactor in a SiH4 - C3H8 - H2 system [27]. In-situ H2 etching was carried out at 1650oC for 30 min, prior to epitaxial growth. The pressure during H2 etching was 4.6 kPa. The typical growth temperature and growth pressure were 1650 oC and 4.6 kPa,

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respectively. The SiH4 flow rate was changed in the range from 1 to 30 sccm. The flow rate of H2 carrier gas was fixed at 10 slm. The surface morphology of substrates and epilayers was observed using a Nomarski microscope and atomic force microscopy (AFM). The BPD density was investigated by etching epilayers in molten potassium hydroxide (KOH) at 500 oC for 5 min. The doping concentration of epilayers was determined by capacitance-voltage (C-V) measurement on a Ni/Schottky structure with a probe frequency of 1 MHz. Typical diameter of the Schottky contacts was 1.0-1.5 mm. The photoluminescence (PL) spectra were acquired at 4 K and 300 K with a HeCd laser ( = 325 nm) as an excitation source. Fig. 1 shows the SiH4-flow-rate dependence of the growth rate at a moderate C/Si ratio (C/Si = 1.2) in source gases. The growth rate was independent of the C/Si ratio in the moderate range from 1.0 to 1.3. The growth rate increased almost in proportion to the SiH4 flow rate, and it reached 85 m/h at a SiH4 flow rate of 30 sccm. Fig. 2 depicts Nomarski micrographs for 100 m-thick epilayers grown at 85 m/h at growth pressure of (a) 10.6 kPa and (b) 4.6 kPa. A very rough surface with island-like morphology is obtained when growth was performed at a pressure of 10.6 kPa, probably due to pronounced homogeneous nucleation(Si condensation). In contrast, at lower growth pressure of 4.6 kPa, the surface morphology was markedly improved, because the Si condensation is reduced at low pressure. The roughness defined by root mean square (rms) was as low as 0.18 nm in a

Growth Rate ( m/h)

100 C/Si = 1.2 80 60 40 20 0

0

5 10 15 20 25 30 35 SiH4 Flow Rate (sccm)

Figure 1. SiH4-flow-rate dependence of the growth rate at amoderate C/Si ratio (C/Si = 1.2) in homoepitaxial growth of 4H-SiC(0001). The growth temperature and pressure were 1650oC and 4.6 kPa, respectively.


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10 10 m2 scan and 0.21 nm in a 20 20 m2 scan in AFM measurements. On 4o off-axis 4H-SiC(0001), the surface morphology was worse than on 8 o off-axis substrates, when the growth rate was higher than 25-30 m/h. As the both SiH4 and C3H8 flow rates increased under moderate or high C/Si ratio conditions, the doping concentration significantly decreased at a given C/Si ratio. It has been reported that, under C-rich condition, the absolute amount of excess carbon increases as the total source gas flow rate (SiH4 and C3H8) increases while keeping a constant C/Si ratio of inlet source gases, which results in the increase of effective C/Si ratio on the growing surface [28,29]. This may lead to suppression of nitrogen incorporation at high SiH4 and C3H8 flow rates, due to the increase of effective C/Si ratio (site competition effect [30]). Fig. 3 shows the C/Si ratio dependence of the doping

Net Donor Concentration (cm-3)

Figure 2. Nomarski micrographs for 100 m-thick 4H-SiC epilayers grown with a growth rate of 85 m/h at growth pressure of (a) 10.6 kPa and (b) 4.6 kPa. 1016 4H-SiC(0001), undoped 15

10

1014 1013 1012 0.6 0.8 1.0 1.2 1.4 1.6 1.8

C/Si Ratio Figure 3. C/Si ratio dependence of the doping concentration for unintentionally doped 4H-SiC(0001) epilayers grown at 50 m/h.

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concentration for unintentionally doped epilayers grown at 50 m/h. As expected from the site competition effect [30], the net donor concentration decreased considerably with increasing the C/Si ratio. The typical background concentration was 5 1013 cm-3 at the C/Si ratio of 1.2, where very smooth surface can be obtained as shown in Fig.2 (b). Although an even lower net donor concentration below 1 1013 cm-3 can be attained at a C/Si ratio of 1.5, the surface exhibited macrostep bunching with a rms roughnes of 1.5-2.2 nm. Further increase in the C/Si ratio resulted in the increase of surface roughness and flip to the p-type conductivity. Fig. 4 represents the PL spectra at 4 K and 300 K for a 160 m-thick epilayer grown at 80 m/h without intentional doping. This epilayer is lightly doped n-type with a net donor concentration of 6 1013 cm-3, as determined by C-V measurement. In the PL spectra, free exciton peaks labeled by the I series are exclusively dominant. Although the Q0 peak that originates from excitons bound to neutral nitrogen donors was also observed, it is very small compared with free-exciton peaks, which suggests high purity of the epilayer [31]. The PL intensity of impurity-related peaks such as B, Ti, Al was also very small, at least 200 times smaller than that of free exciton peaks. In general, the L1 peak (2.901 eV), attributed to the DI center [32,33], is often observed in fast epitaxial growth of 4H-SiC. The DI center is thought to be an intrinsic defect complex, which is observed in both as-grown and irradiated SiC. It should be noted that the L1 peak was hardly observed even at high growth rate of 80 m/h (at least, 1000 times smaller than free exciton peaks) in this study.

Figure 4. Photoluminescence spectra at 4 K and 300 K for a 160 m-thick 4H-SiC epilayer grown at 80 m/h without intentional doping.


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Characterization of defects in SiC epilayers Dislocations Since the micropipe density in SiC wafers has been reduced down to well below 0.1 cm-2(almost eliminated), normal dislocations and epi-induced defects such as carrot defects are one of main issues in SiC epilayers. Most dislocations in 4H-SiC homoepitaxial layers originate from dislocations in 4H-SiC substrates. Major dislocations in SiC substrates include threading screw dislocations (TSD), threading edge dislocations (TED), and basalplane dislocations (BPD), though these dislocations form a complex network in the substrates [34]. The typical TSD, TED, and BPD densities in the commercial substrates are 500, 3000-5000, and 1000-5000 cm-2, respectively. Fig. 5 represents the schematic illustration of dislocations in 4H-SiC epilayers grown on off-axis {0001} by CVD [35-39]. Almost all the TSDs in the substrate are replicated in the epilayer, but some TSDs are converted to Frank partials [35]. A TSD in the substrate can work as the nucleation site of a carrot defect, which usually consists of basal-plane and prismatic-plane faults [35,40]. A BPD is another detrimental defect especially for SiC bipolar devices [41,42] and the reliability of thermal oxides [43]. Although most BPDs in the substrate are converted to TEDs within a few m of the initial epilayers, some

Figure 5. Schematic illustration of dislocation propagation in 4H-SiC epilayers grown on off-axis {0001} by chemical vapor deposition.

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Conversion Ratio of BPDs (%)

BPDs of a screw character propagate in the basal planes of the epilayer. Conversion from BPDs to TEDs has been enhanced by several ways such as molten KOH etching [44] or H2 etching [45] prior to epitaxial growth, interruption during growth [46], and the utilization of a low off-angle [45]. Fig. 6 shows the conversion ratio from BPDs in the substrates to TEDs in 4HSiC epilayers as a function of growth rate [25]. Here, the growth temperature, pressure, and C/Si ratio were fixed, while the gas flow rates and growth period were varied to obtain SiC epilayers with similar thickness at different growth rate. The increase in growth rate is effective for enhancement of the conversion ratio. By fast epitaxial growth (> 25 m/h) on CMP (Chemical Mechanically Polished) substrates, a high conversion ratio over 99% is achieved. It has been suggested that the conversion of BPDs into TEDs is driven by the image force, which is enhanced when the distance between the dislocation and the crystal surface becomes small. Thus, the superior flatness of CMP substrates may be effective to promote the dislocation conversion. The authors also investigated the influence of C/Si ratio on the BPD-TED conversion and confirmed that the C/Si ratio dependence of the conversion ratio was very small in the C/Si ratio range from 1.0 to 2.0. It has been suggested that the BPD-TED conversion is enhanced when two partial dislocations, which are formed through dissociation of an initial BPD, meet

100

95

CMP as-received substrate

90

T = 1650 oC C/Si ratio = 1.2-1.5

85

8o off-axis (0001)

80

0

10

20

30

40

50

60

Growth Rate ( m/h) Figure 6. Conversion ratio from basal-plane dislocations to threading edge dislocations during SiC epitaxial growth as a function of growth rate. The growth temperature was 1650oC, and the thickness of epitaxial layers are about 22-25 m. Both as-received and chemical-mechanically-polished substrates were employed.


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and are combined into one perfect BPD [47]. A similar phenomenon may be enhanced in fast epitaxial growth, though the exact mechanism is not clear at present. A minimum BPD density and maximum conversion ratio obtained in this study were 8 cm-2 and 99.8 %, respectively. PL mapping or imaging techniques enables easy and non-destructive detection of dislocations in SiC [48-51]. Fig.7(a) shows the image of micro PL intensity mapping at 390 nm (near band-edge emission) at room temperature obtained from a 72 m-thick n-type 4H-SiC epilayer intentionally doped to 1 1015 cm-3. Three circular areas with reduced PL intensity in contrast to the matrix can be observed, indicating locations of non-radiative recombination centers. Among these three circular areas, two of them show a larger size than the other one. Fig. 7(b) represents the optical microscopy image of the sample surface (same location) after molten KOH etching at 480oC for 10 min. Three threading dislocations are revealed by characteristic etch pits. In these figures, there is a one-to-one correlation between the circular areas with reduced PL intensity and threading dislocations. It should also be noted that a TSD exhibits a larger and darker circular area in micro PL intensity mapping than a TED. The authors monitored more than 200 dislocations by micro PL mapping and etch pits, and obtained a similar result. This result suggests that TSDs have a more pronounced impact on the non-radiative recombination activity than TEDs [51]. Detection of BPDs is easy, because long dark lines along the offdirection can be observed in micro PL mapping, and in many cases, a BPD is dissociated into two partial dislocations and a Shockley-type stacking fault is formed between them during PL measurement, as reported in ref. 50. Anyway,

Figure 7. (a) Micro PL intensity mapping at 390 nm (near band-edge emission) at room temperature obtained from a 72 m-thick n-type 4H-SiC epilayer intentionally doped to 1 1015 cm-3. (b) Optical microscopy image of the sample surface (same location) after molten KOH etching at 480oC for 10 min.

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individual dislocation types (TSD, TED, and BPD) can be easily identified by a non-destructive micro PL mapping technique.

In-grown stacking faults The authors’group suggested that epi-induced stacking faults (in-grown SFs) and morphological defects which contain SFs (e.g. carrot defect) cause severe decrease in blocking voltage of SiC devices [52,53]. It should be noted that most of in-grown SFs are invisible in optical microscopy. For detection of the SFs, PLmapping/imaging is a powerful method [54,55]. In this study, thick 4H-SiC epilayers grown by hot-wall CVD at a high growth rate of 50-85 m/h have been characterized by PL mapping at room temperature. Fig. 8 shows the micro PL spectra acquired from several areas with and without in-grown SFsin a 4H-SiC epilayer at room temperature. From the 4H-SiC matrix without SFs, only one peak located at 390 nm is observed. From the SF regions, however, distinct PL peaks at 460 nm, 480 nm, and 500 nm were observed in addition to the weak band edge (free exciton) peak at 390 nm.

Figure 8. Micro PL spectra acquired from several areas with and without in-grown SFs (IGSF-1, IGSF-2, IGSF-3) in a 4H-SiC epilayer at room temperature. IGSF-1, IGSF-2, IGSF-3 are in-grown SFs which exhibit a PL peak at about 460 nm, 480 nm, and 500 nm, respectively.


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Thus, the PL intensity mapping at a wavelength specific to each SF gives the profiling (location, shape, and density) of in-grown SFs. Fig. 9 shows the high-resolution TEM (Transmission Electron Microscopy) and micro PL images taken from the major in-grown SFs which exhibit PL peaks at (a) 460 nm, (b) 480 nm, and (c) 500 nm, respectively. The stacking sequence has been determined as the (4,4), (5,3), and (6,2) types in the Zhdanov’s notation. The one-to-one correlation has been established between the PL peak and the stacking sequence. The shape of SFs which show PL peaks at 460 nm and 480 nm is a right-angled triangle with a pointed apex at the upstream side of step flow. On the other hand, the shape of SF which shows 500 nm emission is isosceles triangular. Since the length of all these SFs agrees with the projected length of the basal plane in the epitaxial layers, it can be speculated that these SFs are generated at the initial stage of epitaxial growth. However, exact mechanism of SF generation is still not clear at present. Optimization of in-situ H2 etching condition and starting epitaxial growth at lower growth rate are effective to reduce the density of these SFs. The total density of

(a) (b) (c)

Figure 9. High-resolution TEM images taken from the major in-grown SFs in 4H-SiC epilayers grown at 72 m/h and the corresponding PL intensity mapping images at room temperature. (a) (4,4), (b) (5,3), (c) (6,2) structures.

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SFs is typically 0.5-5 cm-2 for epilayers grown at 50 m/h, and it tends to increase when the growth rate is increased. Elimination of these in-grown SFs is an important remaining issue in fast epitaxy of SiC.

Deep levels Another type of important defects in epilayers is a point defect, which creates a deep level in a bandgap. The authors and other groups have investigated the major deep levels observed in as-grown n- and p-type epilayers and their thermal stability [56-59]. Deep level transient spectroscopy (DLTS) measurements were performed on SiC Schottky structure in the temperature range from 100 K to 760 K. The Schottky metal employed was Ni for n-type and Ti for p-type SiC. Fig.10 illustrates the energy levels of major deep levels observed in as-grown n-type and p-type 4H-SiC epilayers. Among them, the Z1/2 (EC – 0.65 eV) [56] and EH6/7 (EC – 1.55 eV) [57] centers are the dominant and thermally stable defects commonly observed with a highest concentration ((0.2-3) 1013 cm-3) in all the as-grown epilayers. In the lower half of the bandgap, the HK2 (EV + 0.84 eV), HK3 (EV + 1.24 eV), and HK4 (EV + 1.44 eV) [59] are dominant deep levels, though the HS2 center (EV + 0.4 eV) becomes dominant in irradiated Conduction Band

Ec

0.0

3.0

EC - ET (eV)

RD1/2 1.0

Detected in p-type

UT1 EH6/7

2.0

HK4 (P1)

2.0

HK3

ET - EV (eV)

Z1/2

1.0

HK2 3.0

Detected in n-type

HS2 Ev

Valence Band

Figure 10. Energy levels of major deep levels observed in as-grown n-type and p-type 4H-SiC epilayers.


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and annealed SiC [60]. When the samples were annealed at high temperature in the range from 1300oC to 1700oC, both the Z1/2 and EH6/7 centers are very stable but hole traps (HK2, HK3, and HK4) are almost annealed out at 14501550oC [59]. It should be noted that the Z1/2 and EH6/7 centers are generated with a high concentration (1014 - 1015 cm-3) by ion implantation [61] and/or dry etching [62]. Thus, the Z1/2 and EH6/7 centers are very important deep levels in fabrication of SiC devices. Storasta et al. and the authors have reported that the concentrations of both the Z1/2 and EH6/7 centers increased by irradiation of low-energy (116-200 keV) electrons, by which only carbon atoms are displaced [58,63]. Although the microscopic structure of these defect centers are still unknown, the involvement of a carbon vacancy has been suggested. The following experimental facts have been found: 1) Both centers are generated via low-energy electron irradiation, by which only carbon atoms are displaced, and no thermal treatment after the irradiation is required to form the defect centers [58,63]. 2) The concentrations of the defect centers are almost in proportion to the electron fluence, and the defect concentration can exceed that of any impurities in SiC epilayers, indicating exclusion of impurity involvement [63]. 3) The extremely high thermal stability suggests exclusion of carboninterstitial-related defects. 4) In as-grown epilayers, the concentrations of both defects significantly increase when the epilayer is grown under Si-rich condition, and decrease under C-rich condition [64]. 5) The elimination process of these defects described below is consistent with the hypothesis that both defects are carbon-vacancy-related. 6) In as-grown, electron-irradiated, and annealed n-type 4H-SiC, the EH6/7 concentration is close to the Z1/2 concentration for almost all the samples in a very wide range of defect concentration (10 11~1015 cm-3). Therefore, the Z1/2 and EH6/7 centers may be attributed to different charge states of the same point defect, or at least, may contain a same intrinsic defect, most likely carbon vacancy [58]. In recent years, the Z1/2 center has been identified as a major carrierlifetime killer in n-type 4H-SiC, as described in the next subsection [65,66]. Thus, it is very important to control the concentration of Z1/2 center for obtaining an optimal carrier lifetime in fabrication of SiC bipolar devices. One effective way to reduce the Z1/2 concentration is the increased C/Si ratio during CVD growth or by decreasing growth temperature [67]. However,

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DLTS Signal (fF)

10 8

Z1/2 as-grown

6 4 2

EH6/7 after oxidation (1300oC, 5h)

0 100 200 300 400 500 600 700

Temperature (K)

(a)

Z1/2 Concentration (cm -3)

these growth parameters should be carefully optimized, because the good morphology and low density of extended defects must be maintained. Storasta et al. reported that the Z1/2 center can be eliminated by C+ implantation and subsequent annealing at 1600-1800oC [68,69]. They speculated that C interstitials generated by implantation may diffuse and recombine with C vacancies, which is most likely an origin of the Z1/2 center. The authors discovered that both the Z1/2 and EH6/7 centers can be completely eliminated (< 1×1011 cm-3) by thermal oxidation [70,71]. Fig.11(a) depicts the DLTS spectra taken from an n-type 4H-SiC epilayer before and after thermal oxidation at 1300oC for 5 h. The Z1/2 and EH6/7 centers are dominant with a trap concentration of 3×1012 cm-3 in the as-grown epilayer, but both the DLTS peaks disappeared after the oxidation. The depth profiles of the Z1/2 concentration before and after oxidation are shown in Fig.11(b). The Z1/2 center is eliminated in the 9 μm-, 21 μm-, and 47 μmdeep regions from the surface after oxidation for 10 min, 1 h, and 5 h, respectively. In thermal oxidation of SiC, Hijikata et al. reported that a Siand-C emission model can well simulate the experimental oxidation rate of SiC [72]. Therefore, the authors suggest that the C interstitials emitted from the SiO2/SiC interface may diffuse into the bulk region of the epilayer during oxidation, and the C vacancies (likely related to the Z1/2 and EH6/7 centers) annihilate via recombination with the C interstitials diffused from the interface. In the DLTS spectrum from the p-type epilayer after oxidation, a large DLTS peak emerged at 355 K (not shown) [71]. From the energy level (EV + 0.78eV), this trap can be ascribed to the HK0 center [59]. The HK0 concentration is approximately 1×1013 cm-3 at a depth of 1.2-1.5 μm. The HK0 1013

1012

as-grown 5h

10 min 1h

1011 Detection Limit

0

10 20 30 40 50 Depth From Surface (μm)

(b)

Figure 11. (a) DLTS spectra of an n-type 4H-SiC epilayer before and after thermal oxidation at 1300oC for 5 h. (b) Depth profiles of the Z1/2 concentration before and after oxidation at 1300oC for 10 min, 1 h, and 5 h, respectively.


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center can be completely reduced by the subsequent annealing at 1550 oC for 30 min in Ar [59]. Thus, most of major deep levels in 4H-SiC can be reduced to below the detection limit (1 1011 cm-3) by the two-step thermal treatment, namely thermal oxidation followed by high-temperature (1550oC) annealing in Ar [71]. Note that the thermal oxides were removed before Ar annealing.

Carrier lifetimes A carrier lifetime is an important physical property, which determines the performance of bipolar devices, and fundamental study has been performed on carrier lifetimes in SiC [73]. In order to elucidate the quantitative correlation between the carrier lifetime and the concentrations of deep levels, lifetime mapping by -PCD (microwave-detected photoconductance decay) and the deep-level concentration mapping by DLTS measurements have been performed for a number of samples, and these properties on exactly the same locations were compared. For several samples, two-step thermal treatment, namely thermal oxidation at 1300oC for 5 h followed by Ar annealing at 1550oC for 30 min was performed in order to eliminate the Z 1/2 (and EH6/7) center [70,71]. In -PCD measurements, an YLF-third harmonic generation laser ( = 349 nm) was employed. The photon density during the excitation was (1-2) 1014 cm-2. Fig.12 depicts the inverse of the carrier lifetime vs. the concentration of the Z1/2 center measured for 50 m-thick n-type 4H-SiC epilayers. The data denoted by closed circles are the same as those presented in a previous report [74]. The open triangles indicate the data obtained in latest experiments where the C/Si ratio was changed. By increasing the C/Si ratio from 0.8 to 1.5 during CVD, the Z1/2 concentration was reduced from 6.2×1013 cm-3 to 1.5×1012 cm-3. The open squares denote the data obtained for the samples in which the Z1/2 center was eliminated by the two-step thermal treatment. When the Z1/2 concentration is higher than (1-2)×1013 cm-3, the inverse of the carrier lifetime is proportional to the Z1/2 concentration, indicating the lifetime is governed by the Shockley-Read-Hall (SRH) recombination via the Z1/2 center. However, the correlation between the lifetime and the Z1/2 concentration is not clear when the Z1/2 concentration is in the 1011~1012 cm-3 range. Based on this result, there must exist, at least, two different recombination processes; the SRH recombination and the other recombination. Thus, the carrier lifetime ( ) is given by the following equation: 1/ = 1/

SRH

+ 1/

other,

(1)

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107

0.1

106

1

105

10

104 11 10

1012

1013

1014

Carrier Lifetime ( s)

1 / (s-1)

50 m-thick epilayers

100

Z1/2 Concentration (cm -3) Figure 12. Inverse of the carrier lifetime vs. the concentration of the Z 1/2 center measured for 50 m-thick n-type 4H-SiC epilayers. The data denoted by closed circles are the same as those presented in a previous report [74]. The open triangles indicate the data obtained when the C/Si ratio was changed. The open squares denote the data obtained for the samples in which the Z1/2 center was eliminated by the twostep thermal treatment.

where SRH is the SRH lifetime governed by recombination centers, and other is the carrier lifetime governed by other recombination processes. Here, the inverse of SRH should be proportional to the concentration of recombination centers (1/ SRH = aNZ1/2, a: constant, NZ1/2: the concentration of the Z1/2 center), while other can be assumed to be independent of the Z1/2 concentration. By using this model expressed by Eq. (1), the experimental data were fitted, where the other and a are the fitting parameters. The fitted result is shown by two broken lines for 1/ SRH and 1/ other, respectively. Since the Z1/2 concentration can be increased by low-energy electron irradiation, it is rather easy to obtain the shortened carrier lifetimes with good uniformity (lifetime control) by utilizing the irradiation technique [74]. In order to clarify the influences of the surface recombination and recombination in the substrate on carrier lifetimes, numerical simulation based on a diffusion equation has been performed, detail of which is described elsewhere [75]. In the simulation, a two-layer model, namely an epilayer on a substrate, was considered, and the distribution (depth profile) of excess carrier concentration was calculated as a function of time, taking account of bulk recombination and surface recombination. By integrating the excess carrier concentration for each time step, the decay curve and the

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corresponding effective lifetime were calculated. The effective lifetimes obtained from the simulated decay curves are plotted as a function of the bulk lifetime of the epilayers in Fig.13. In this simulation, the epilayer thickness was also varied as a parameter, while the surface recombination velocity was fixed to be 1000 cm/s. As shown in Fig.13, when the epilayer thickness is 50 m and the bulk lifetime of an epilayer is shorter than 0.5 s, the effective lifetime is nearly equal to the bulk lifetime of an epilayer (The effective lifetime is only 4-20% shorter). However, the effective lifetime shows saturation at a value of 1.8 s for 50 m-thick epilayers when the bulk lifetime exceeds 30 s. At a 10 s bulk lifetime, for example, the effective lifetime is only 1.5 s, indicating almost detrimental underestimation. When the bulk lifetime is long, e.g. 10 s, the effective lifetime increases with increasing the epilayer thickness, and reaches 8.5 s for an epilayer thickness of 300 m. If an extremely long bulk lifetime of 100 s is achieved, an even thicker epilayer with a low surface recombination velocity is required for accurate evaluation of carrier lifetimes. On the other hand, it is very hard to obtain accurate bulk lifetimes for 10-30 m-thick epilayers, as shown in Fig.13. These results clearly indicate the impacts of carrier recombination in the substrates on the lifetime measurements. SRV = 1000 cm/s

102

Effective Lifetime ( s)

eff eff =

= 0.8

epi

Wepi = 300 m epi

Wepi = 200 m

101

Wepi = 100 m

Wepi = 50 m

100

Wepi = 30 m

Wepi = 10 m

10-1 10

-1

10

0

1

10

102

Bulk Lifetime of Epilayer ( s) Figure 13. Effective lifetimes obtained from the simulated decay curves as a function of the bulk lifetime of 4H-SiC epilayers. The experimental relationship between the measured lifetime and the bulk lifetime obtained from the data in Fig.12 (epilayer thickness Wepi = 50 m) is also plotted. Regarding the experimental data, the same symbols as in Fig.12 are used.

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If the bulk lifetimes of present n-type 4H-SiC epilayers are dominated by a Shockley-Read-Hall (SRH) recombination via the Z1/2 center, a simple relationship between the bulk lifetime ( epi SRH) and the Z1/2 concentration (NZ) can be established based on the results in Fig.12 (broken line) as follows: epi

[ s] = 2×1013 / NZ [cm-3].

(2)

Note that this equation is valid when the Auger recombination and recombination at extended defects are less important, but it does depend neither on the epilayer thickness nor on the surface recombination velocity. The factor 2×1013 depends on the excitation intensity (injection level) and temperature. Using this equation, the bulk lifetimes in epilayers were estimated from the Z1/2 concentration. Thus, the experimental relationship between the measured lifetime and the bulk lifetime was obtained from the data shown in Fig.12. This relationship is plotted in Fig.13, considering that the measured lifetime corresponds to the effective lifetime in the simulation. Regarding the experimental data, the same symbols as in Fig.12 are used. It is natural that the effective lifetime is nearly equal to the bulk lifetime when the bulk lifetime is short, less than 1 s, because the lifetime is indeed limited by the Z1/2 center in this region. The measured lifetimes tend to saturate at about 2 s when the bulk lifetime is very long, being in good agreement with the result simulated for 50 m-thick epilayers, as shown in Fig.13. Thus, the other recombination paths, which limit the measured lifetimes in 4H-SiC epilayers with low Z1/2 concentrations as indicated by a dotted line in Fig.12, may be mainly the surface recombination and fast recombination in the substrate. Since it is revealed that the recombination in a substrate greatly affects the lifetime measurements, epilayers with different thicknesses were prepared to experimentally investigate the influence of substrate recombination. N-type 4H-SiC epilayers with a thickness of 50, 98, 122 and 148 m were grown on highly-doped substrates. The donor concentration of the epilayers was (0.9-1)×1015 cm-3. After the lifetime measurements on as-grown materials by a -PCD method, two-step thermal treatment, thermal oxidation at 1300oC for 5 h followed by Ar annealing at 1550 oC for 30 min was performed in order to eliminate the Z1/2 (and EH6/7) center. After this defect reduction process, the lifetime measurements were repeated. Fig.14 shows the -PCD decay curves at room temperature obtained from a 148 m-thick epilayer before (as-grown) and after the two-step thermal treatment [75]. For the as-grown epilayer, the measured lifetime is 0.69 s, while the lifetime is remarkably improved to 9.5 s after the thermal treatment owing to significant reduction of the Z1/2 center.

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-PCD Signal (a.u.)

N0 = 1x1014 cm-2

4H-SiC epilayer

103

after oxidation & Ar annealing

102 as-grown

101

0

5

10 Time ( s)

15

20

Figure 14. -PCD decay curves at room temperature obtained from a 148 m-thick SiC epilayer before (as-grown) and after the two-step thermal treatment.

The dependence of measured lifetimes on the epilayer thickness is presented in Fig.15, where the lifetimes before and after the two-step thermal treatment are plotted by closed and open circles. In the figure, the simulated dependence of the lifetime on the epilayer thickness is also shown by dashed lines, for various bulk lifetimes of epilayers. In the simulation, the surface recombination velocity (SRV) was assumed to be 1000 cm/s. For as-grown epilayers, the measured lifetimes were almost independent of the epilayer thickness in the investigated range, and showed good agreement with the result simulated for a bulk lifetime of 0.8 s. In the as-grown epilayers, SRH recombination via the Z1/2 center is dominant, and the impact of carrier recombination in substrates is less important. In contrast, the measured lifetimes exhibit significant increase with increasing the epilayer thickness for samples with greatly reduced Z1/2 concentration, suggesting that the dominant recombination path is changed from the SRH recombination to the recombination in the substrates for high-quality epilayers. Although it is difficult to estimate the real bulk lifetime in the epilayers after the two-step thermal treatment due to the lack of experimental SRV values, the bulk lifetime may be about 30 s or even longer, as seen from Fig. 15. The carrier lifetime was further improved to 13.1 s by surface passivation with a nitrided oxide [76].

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n-type 4H-SiC epilayers

Carrier Lifetime ( s)

10 8

epi

= 50 s epi

= 30 s

epi

= 10 s

epi

=5 s

epi

= 0.8 s

: as-grown : oxidation + Ar annealing

6 4 2 0 0

50 100 150 Epilayer Thickness ( m)

200

Figure 15. Dependence of measured lifetimes on the SiC epilayer thickness. The lifetimes before and after the two-step thermal treatment are plotted by closed and open circles, respectively. The simulated dependence of the lifetime on the epilayer thickness is also shown by dashed lines, for various bulk lifetimes of epilayers.

Summary Through reduction of homogenous nucleation of Si clusters by lowpressure (4.6 kPa) chemical vapor deposition, the growth rate of 4H-SiC homoepitaxy was increased to 85 m/h while keeping very good morphology. The net donor concentration of unintentionally doped epilayers is 5 1013 cm-3 or less. In photoluminescence measurements at 4 K, free exciton peaks were dominant from lightly-doped thick epilayers, and impurity- or defect-related luminescence peaks were hardly observed. The extended defects and deep levels generated in 4H-SiC epilayers were reviewed. Threading and basal plane dislocations can be nondestructively detected by photoluminescence mapping at room temperature. Conversion of basal plane dislocations to threading edge dislocations can be enhanced by several techniques such as appropriate surface etching prior to CVD growth and fast epitaxy. In fast epitaxial growth (> 50 m/h), three types of in-grown SFs, (4,4), (5,3), and (6,2) structures, have been revealed in epilayers with a density of 0.5-5 cm-2. One-to-one correlation between three types of major ingrown SFs and PL spectra was established. All the major deep levels present in as-grown n- and p-type 4H-SiC epilayers were summarized. The Z1/2 center, origin of which may be a carbon vacancy, was identified as the


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dominant lifetime killer in 4H-SiC. All the major deep levels could be eliminated (< 1 1011 cm-3) by thermal oxidation followed by Ar annealing at 1550oC. Recombination paths of excess carriers in SiC epilayers are discussed. In experimental study on a 148 m-thick n-type SiC epilayer, the carrier lifetime was improved from 0.69 s to 9.5 s by reducing the Z1/2 center via two-step thermal treatment. The real bulk lifetime may be about 30 s or even longer, as judged from comparison with simulated results.

Acknowledgements This work was supported by a Grant-in-Aid for Scientific Research (21226008) and the Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program) from the Japan Society for the Promotion of Science.

References 1. 2. 3. 4. 5. 6. 7. 8.

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7. 3C-SiC epitaxial growth on large area silicon: Thin films Andrea Severino

Epitaxial Technology Center srl, 16a strada – Pantano D’Arci, Blocco Torre Allegra 95121, Catania, Italy; CNR-IMM, VIII strada 5, 95121, Catania, Italy

Abstract. Cubic Silicon Carbide (3C-SiC) heteroepitaxy with Silicon (Si) substrates is desirable in order to sensibly reduce the manufacturing costs and increase the crystal area. Mismatches in lattice parameters and thermal expansion coefficients limits the development of such a technology, leading to formation of devicedegrading crystallographic defects and significant wafer bowing. In this chapter, a survey on chemical vapor deposition (CVD) of 3CSiC on Si substrates is presented since the nucleation of the buffer layer. A comparison of experimental data extracted from the available literature indicates that thin epitaxial 3C-SiC films of better quality are grown when slower growth rate processes are used. The improvement of the crystal quality is also commonly observed as the epitaxial layers grow in thickness. Notwithstanding the quality improvement of nowadays available 3C-SiC epitaxial layers, stacking faults (SFs) reduction is still an open issue as SFs linear density commonly tend to a saturation value of about 5 × 103 cm-1 in 50 m thick films. Chapter ends with considerations on another issue involved in the 3C-SiC/Si heteroepitaxy, i.e. the wafer bow. Correspondence/Reprint request: Dr. Andrea Severino, Epitaxial Technology Center srl, 16 o strada – Pantano d‟Arci, Blocco Torre Allegra, 95121, CNR-IMM, VIII strada 5, 95121, Catania, Italy E-mail: [email protected]

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Introduction Many attractive mechanical and electrical properties make silicon carbide (SiC) a material of interest in both electronic devices and sensors for nowadays technology (sustainable energies, hybrid vehicles, low power loss inverters). Silicon carbide exists in nature in several crystalline structures, called polytypes, differentiated by the stacking sequence of the tetrahedrally bonded Si-C bilayers [1,2,3]. Thus, a large number of different atomic arrangements and symmetries can be obtained, from hexagonal to cubic and rhombohedral. The only possible cubic structure, 3C-SiC, is obtained when the bilayer stacking is of the kind ABCABC…, resulting in a pure zincblende structure. Different polytypes have widely ranging physical properties. For instance, 3C-SiC shows the highest electron mobility and saturation velocity, because of the reduced phonon scattering resulting from a higher symmetry, while its band gap energy is the lowest (2.3 eV) [4,5,6,7]. Furthermore, cubic silicon carbide (3C-SiC) is more stable at lower temperature with respect to other polytypes and, hence, it can be grown below 1500 °C [3]. This stability at lower temperature is both a limitation and

Figure 1. Snapshot of an 8 inch Si wafer after the growth of a 3 m thick single crystal 3C-SiC film. The growth has been conducted within a CVD reactor (ACIS M10), sited in ETC (Catania).

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an advantage for 3C-SiC development. The drawback arises from the reduced thermal budget required for its growth that limits the development for a reliable 3C-SiC bulk growth technology which would allow the realization of the seed for the subsequent homoepitaxial growth in order to obtain devicegrade 3C-SiC epilayers. The lack of such a substrate forces to grow 3C-SiC hetero-epitaxially on different substrates. Many attempts have been made in optimizing the heteroepitaxial growth of 3C-SiC on hexagonal polytypes (both 6H- and 4H-SiC) [8,9,10] but the manufacturing costs are too high and substrate sizes still limited. An important technological and scientific breakthrough would be growing high-quality 3C-SiC epilayers on a substrate with an area as large as possible, i.e. on silicon. This is the main reason why silicon is considered as the most interesting substrate and crystal seed for thin epitaxial films and/or subsequent bulk 3C-SiC growth. Furthermore, 3C-SiC growth on Si is allowed within chemical vapor deposition (CVD) reactors, which would ensure a very high purity of the resulting product. Motivations in developing a technology based on 3C-SiC heteroepitaxy mainly reside on the chance that such a system ensures in reducing the cost for production of a wide bandgap material. The scientific efforts devoted, in the last decades, in maturing the 4H-SiC technology, mainly concentrated in developing larger area seeds for substrates and high-purity electronic-grade epitaxy, still have to face some relevant drawback such as the cost for material production and the viability of reliable and efficient electronics devices, such as MOSFETs. If one wants to roughly compare the estimated costs for the production of SiC epitaxial layers for Schottky diode applications, a 6 m thick 3C-SiC epitaxial layer grown on a 8 inch Si substrate would have a cost of about 2 $/cm2 compared to an approximated cost of 20 $/cm2 for a 4H-SiC homoepitaxial layer. Thus, the reduction is about one order of magnitude! Of course, 4H-SiC crystals show a much higher purity and quality and 4H-SiC homoepitaxy is a more mature technology. Indeed, 3C-SiC crystals grown on Si present a lower material quality and large stress stored in the system, leading eventually to not processable bowed wafers, as a consequence of the poor compliance between the substrate and the epitaxy. By looking to table 1, where some of the most important semiconductor electrical properties of 3C, 4H and 6H silicon carbide polytypes at room temperature are given together with Si properties, shown here for the sake of comparison, it is reasonable the persistent interest of the research community, pushed by the power device industry, in developing 3C-SiC as the SiC polytype on which bet. Table 1 shows some interesting properties making 3C-SiC as good as 4H-SiC for field effect transistors based on Metal-Oxide-Semiconductor

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Table 1. Most relevant electrical properties of Si, 3C-SiC, 6H-SiC and 4H-SiC [6,7,11,12,13].

structure (MOSFETs). The main advantages, in terms of material properties, that 3C-SiC shows on hexagonal polytypes are large bulk and channel electron mobilities (electron channel mobility e up to 250 cmV-1s-1 has been experienced [14,15,16,17,18]), due to a higher symmetry within the crystal, and lower interface state density at 3C-SiC/SiO2 of at least one order of magnitude with respect to 4H-SiC and 6H-SiC, due to the narrower bandgap energy of 3C-SiC and the presence of such states within the conduction band of 3C-SiC [19,20,21,22,23]. It must be noted that the reduction of state density at SiC/SiO2 interface is crucial in MOS applications since interface states affect the channel mobility of the semiconductor and the threshold voltage of the device. On the other hand, the higher channel mobility and the breakdown voltage of 3C-SiC suggest low values of device on-state resistance (RON) thus reducing the conduction losses when a MOSFET is forward biased [24]. Moreover, a limited concentration of intrinsic carriers (about 11 order of magnitude lower than in Si), property correlated to the energy bandgap of 2.3 eV, contributes in lowering the leakage current in reverse bias, even in the low and medium power regimes. Finally, the high thermal conductivity, together with excellent mechanical properties, ensures a suitability of SiC-based sensors and devices at working temperatures above 250 °C, a requirement that must be fulfilled in some applications at very high power regimes and/or in extreme environments (hybrid vehicle engines, aerospace turbine engines) [25,26,27,28,29]. A strong demand for MOSFETs power devices falls within the generation of sustainable and renewable energies, as power devices in SiC


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are desirable as inverters and converters in photovoltaic applications and wind turbines, respectively. At current status, the technology based on 4HSiC homoepitaxy shows drawbacks in the costs as well as in the surface morphology of epitaxial layers, still limiting the development of marketable power MOSFETs. On the other hand, very encouraging advancements in 3C-SiC-based technology have been made by Acreo and HOYA Corporation that demonstrated the operation of a power MOSFET made of 3C-SiC with low on-state resistance, good electron mobility and blocking voltages up to 610 V [21,24,30]. However, to date there is some open issue for a complete development of high-performance devices based on heteroepitaxial 3C-SiC. Indeed, the quality of the material must be improved to allow the production and marketing of electronic devices. Efforts must be done to reduce the density of crystallographic defects in the 3C-SiC films. Defects are a consequence of the large mismatches in lattice parameters (19% at RT) and in thermal expansion coefficients (~23% at deposition temperatures and 8% at RT) between the two materials. In the next section, issues arising from the highly mismatched 3C-SiC/Si heteroepitaxial system will be introduced and discussed. In this chapter, the technological advancements in 3C-SiC heteroepitaxial growth on Si will be illustrated, with emphasis placed on the CVD process in its different stages during 3C-SiC growth. The initial stage of growth, the so-called Si surface carbonization, will be discussed. Generation and propagation of crystallographic defects, and their relationships with experimental parameters, in uniform micrometric 3C-SiC layers will be then reported. Stress evolution and wafer bowing will also be discussed thanks to several experimental observations, mainly conducted by means of Raman spectroscopy and wafer interferometric profilometry.

3C-SiC heteroepitaxy on Si substrates: A highly mismatched system Due to its stability at lower temperatures, cubic silicon carbide can be grown below the Si melting temperature (1410 °C) so that the growth of epitaxial 3C-SiC films on Si substrates is allowed. The higher stability at low temperatures, on the other hand, is a limiting issue for the development of 3C-SiC bulk growth since there is still not a suitable technology to grow a large scale 3C-SiC crystal seed for substrate realization. As a consequence, 3C-SiC epitaxial layers are always obtained on dissimilar substrates, that is on 4H-SiC and on Si wafers.

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There are at least a couple of good reasons to bet on the development of 3C-SiC heteroepitaxy with Si. First, both these materials show a cubic symmetry, which implies a relationship of epitaxy usually driven by the orientation of the substrate seed. Silicon substrate gives indeed the chance to grow single-crystal (001)-oriented 3C-SiC layers, which is an epitaxial orientation hindered in 3C-SiC heteroepitaxy with 4H-SiC, due to the hexagonal symmetry of the substrate stimulating a (111)-oriented epitaxial layer. Since the electron mobility is higher in the low-packing (001) oriented crystal, the choice of the epitaxy orientation results crucial in order to develop a material suitable for high-performance electronics devices. Another obvious advantage of using Si substrates is due to the larger area, up to 12 inch Si substrates are available, and reduced costs if compared to the 4H-SiC counterpart. When 3C-SiC films are grown on a Si substrate, two dissimilar materials are forced to stay together causing several implications in the resulting epitaxy. First, the bulk lattice parameters of 3C-SiC and Si are 4.3589 Å and 5.4311 Å, respectively, [7,31] leading to a large amount of strain generated at the hetero-interface due to a misfit a/a of about 19.7%. This contribution to the residual strain field is said to be the „intrinsic strain‟ and a high density of crystallographic defects close to the interface are generated in the 3C-SiC film in order to relieve the most of it. The lattice mismatch produces a misfit dislocation at every fifth SiC plane. The „magic‟, as defined by Long, [32] 5:4 SiC-to-Si lattice plane matching was reported by Ernst et al. [33] for selected, away-from-voids, regions of 3C-SiC thin layer. Li et al. [34] indicated that this 5:4 match is extended over the length of the entire layer when void-free film growth conditions are employed. Mendez et al. [35] detected, through cross-section transmission electron microscopy [TEM], misfit dislocations with a density that correspond to one dislocation on each four {111} Si planes (and, then, on each five {111} SiC planes). These dislocations, spaced about 1.61 nm each other, are mainly Lömer (90° type) dislocations, as observed in the filtered micrograph, that are much more efficient than 60° type for relaxing the strain produced by the 20% lattice mismatch. Misfit dislocations, however, are not able to completely relieve the residual strain generated and other mechanisms are then involved, such as grain misorientations and stacking fault generation. The interface between 3C-SiC and Si is the origin of a high density of planar and volume defects, such as microtwins, anti-phase boundaries and stacking faults in the epilayer and voids in Si underneath the hetero-interface. Most of these defects, considered killers for devices, however, reduce their density, and some are totally annihilated, when very thick (several tens of microns) 3C-SiC epitaxial films are realized. Furthermore, defect density and


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surface morphology strongly depend from the orientation of the Si substrate. The through-thickness variation in the defect density is nicely depicted in figure 2 where a cross-section TEM of a 6 μm epitaxial 3C-SiC film grown on an off-axis (111) Si substrate is reported. The lattice mismatch is only one component of the resulting strain, the second contribution being brought by the large mismatch in thermal expansion coefficients (TEC) between Si and SiC. This contribution, called „thermal strain‟, acts mainly during the cooling down from growth temperature to room temperature. Thermal expansion coefficients of Si and SiC at room temperature are 2.57 x 10-6 K-1 and 2.77 x 10-6 K-1, respectively, as tabulated by Slack et al. [37] so that the TEC mismatch is about 8% at RT. When the temperature is raised up to the growth temperature, which is tightly dependent

Figure 2. Cross-section TEM image showing a (111) 3C-SiC from the interface with the Si to the surface. The black contrast close to the interface is due to the large density of defects generated by the hetero-epitaxy. These defects become mainly stacking faults, shown as tilted lines or platelets, approaching the film surface [36].

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on the growth technique used and gaseous precursors involved, but often over 1000 °C, the difference in the TECs of SiC and Si increases, with the mismatch reaching percentages above 20%. The stress generated during the cooling down from growth temperature, due to these variations in the TECs, is of tensile nature, causing an upwards bending of the wafer and, often, the generation of cracks in the epitaxy and in the substrate. The bending, usually referred to „wafer bow‟, is dependent on the size of the crystal (wafer diameter or mesa size), thickness of the 3C-SiC epitaxy, thickness of the Si substrate, symmetry (orientation) of the epitaxial crystal and substrate. In figure 3, a snapshot of a 7 m thick 3C-SiC film grown a 6 inch off-axis (111) Si wafer shows the impressive bow reported in this sample. The wafer bow was calculated to be about 1 cm at the edge of the wafer. Different approaches have been attempted in order to improve the crystal quality of 3C-SiC films grown on Si by using compliant substrates. In fact, by acting on the structure and on the properties of the substrate, it is possible to achieve a better compliance in the heteroepitaxy. Several examples can be found in literature: good-quality 3C-SiC film grown on silicon-on insulator (SOI) was reported with the buried oxide layer effective in suppressing the growth of voids, as the SiO2 acts as a barrier against Si diffusion. In addition, stress in the SiC layer was reduced thanks to the softening of the oxide layer at the high growth temperatures and the use of a thin Si top layer also appeared essential as a seed for the growth of a high-quality SiC film, as reported by many authors. However, 3C-SiC growth on silicon on insulator (SOI) materials have demonstrated a limited success because of the poor stability of the oxide at high growth temperatures.

Figure 3. An example of extreme bowing in a 6 inch 3C-SiC/Si hetero-epitaxial wafer.


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An interesting way to remain compliant without using SiO 2 would be to use porous silicon (p-Si) [43,44]. Abe et al. [45] surveyed an appropriate material that can be epitaxially grown on Si, and whose lattice constant was suitable for 3C-SiC. Boron monophosphide (BP) possesses the lattice constant (0.454 nm) close to the 3C-SiC. However, a significant problem for the SiC growth using a BP film was that BP easily decomposes at a temperature greater than 900 °C without a phosphorus ambient. Irokawa et al. [46] reported that a Si substrate having cavities immediately beneath a surface layer can be used as a stress relaxation structure in 3C–SiC growth on a Si substrate, and pointed out that this structure improves the crystal quality of the films. Finally, an important outcome in the growth on compliant substrates was recently proposed by Nagasawa et al. [47] with the concept of undulant Si substrates found to be effective in the reduction and elimination of defects, such as twin boundaries (TBs) and anti-phase boundaries (APBs).

The growth process of 3C-SiC hetero-epitaxial films by Chemical Vapor Deposition The scientific and technological attraction on 3C-SiC dates from 1959, when Spitzer et al. [48] published the first report of 3C-SiC growth on a silicon wafer by heating the silicon with a gaseous hydrocarbon. This was the first milestone in the 3C-SiC heteroepitaxy on Si. The similarity in atomic structures and the large availability of excellent-quality Si substrates, even if counterbalanced by lattice and thermal mismatches between the two materials, stimulated the first pioneering researches in the sixties. However, the interest on 3C-SiC was initially slowed down by the new perspective to realize high-quality α-SiC thanks to the sublimation method proposed by Tairov [49] in 1978. In the decade between 1970 and 1980, interesting works on the conversion of the Si surface into SiC, and the subsequent growth, were performed [50,51,52]. Usually the resulting quality was poor but it helped a lot in the study of the nucleation of a 3C-SiC layer on Si surface through the use of either ethylene (C2H4), acetylene (C2H2), propane (C3H8), or methane (CH4) as the C-containing gasses. Furthermore, other gaseous sources were experienced as well, with silane (SiH4) or chlorosilanes [53] and, occasionally, single-source precursor, as reported by Jacobson in 1971 [54], as precursors for thicker 3C-SiC films. The actual milestone in the 3C-SiC/Si heteroepitaxy goes back to 1982, when Nishino et al. [55] proposed a multi-step CVD process able to ensure an improvement in the crystal quality of the 3C-SiC epilayers. They demonstrated a method consisting of three different steps for the 3C-SiC

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growth: (i) an etching process with flowing HCl at 1100 °C was performed in order to prepare the Si substrate surface; (ii) a buffer layer growth, necessary to obtain good SiC crystal quality, was performed at 1360 °C for a short time under propane (C3H8) flow; (iii) the crystal growth with both silane and propane was carried out at 1330 °C under a flowing H 2 carrier gas. Under these conditions, a single-crystal 3C-SiC layer can be grown on the buffer layer, used as seed for the subsequent SiC growth. The so-called „buffer layer method‟ used by Nishino stimulated again the race towards the ideal material for electronic applications of 3C-SiC that was started in the fifties. After 1982, several universities and R&D departments of semiconductor industries tried to improve the scientific knowledge and to develop and optimize an industrial growth process. The improvements obtained so far are due to the efforts devoted by researchers in following many different paths in the labyrinth of the 3C-SiC chemical vapor deposition. Available reactors for growing SiC on Si are complicated and a wide range of parameters are involved in a growth process, such as temperature, gaseous precursor composition, pressure, gaseous partial pressures and so on. In literature, a huge number of published works is devoted to the growth of SiC on Si, not only by CVD but also by sputtering or molecular beam epitaxy (MBE). In the last decades, a strong development of CVD reactors brought to the enlargement of the reaction chamber allowing, nowadays, the epitaxial growth on Si wafers with a diameter of 200 mm (8 inches). An example of such a reactor is the ACIS M10, built by LPE and sited at the Epitaxial Technology Center in Catania [56].

Gaseous precursor composition Amongst many variables, the composition of the gaseous precursors is crucial in determining which will be the experimental conditions of several parameters inside the CVD reaction chamber in order to achieve good quality 3C-SiC films. This is of course related to the different behavior of reactants in their dissociation from gaseous phase molecules to solid phase adatoms that will arrive, migrate and bond with the dangling bonds available at substrate surface steps or terraces. An overview of possible reactions can be found in literature [57,58,59]. Thus, changes in gaseous precursor chemistries will determine significant differences in the growth temperature range, in the gas partial pressures during the growth and in the cracking efficiency of reactant species in the gaseous phase. The temperature of gasses determines the rate of production of the various radicals. For instance, in the silanepropane system, a widely used chemistry for SiC CVD epitaxy, silane dissociates at a lower temperature than propane. This means that, as the


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chamber is heated up to growth temperature, the effective C/Si ratio changes so that the real amount of adatoms to form SiC film is unknown. As a consequence, due to the higher thermal stability of CH species compared to the SiH ones [60], the growth process requires a higher amount of C-containing supply in the gas phase to obtain stoichiometric SiC. On the other hand, being Si the minority element in the gas phase participating to the reaction, a linear dependence of the growth rate on the Si-precursor gaseous flux is commonly observed. The dependence of the growth rate with the Si/H2 ratio is reported in figure 4. From this plot, the linear dependence is clearly evidenced. Moreover, a strong dependency of both parameters with the total pressure can also be observed [61]. In details, the higher the reactor pressure the steeper the experimental slope. The higher growth rate at lower Si/H 2 ratio for pressure regime above 200 Torr (eventually at atmospheric pressure) is related to the lower gas velocity and to the longer time that adatoms need to reach the solid surface. When the pressure is reduced, the gas velocity increases and more Si (higher Si/H2 ratio) is required to maintain the same growth rate. The effect of the gas phase composition on the growth mechanism of 3CSiC on Si by atmospheric-pressure CVD (APCVD) using the silane-propane system has been studied by Chassagne et al. [62]. They have correlated the

Figure 4. Dependence of the growth rate with the Si/H2 ratio. This dependence is strongly influenced by the total pressure within the reaction chamber. Growth temperatures used are similar.

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resulting surface morphology with the partial pressure of carbon above the growing surface, demonstrating the existence of an equilibrium partial pressure of the C-precursor, referred to C/Si ratio, which ensures a mirrorlike morphology. In details, low values of C/Si (2) resulted in high defect density with homogenous nucleation while a mirror-like surface was observed for intermediate C/Si ratio [62,63]. However, the silane-propane system is affected by homogeneous gas phase nucleation, where solid/liquid particulates (usually of Si) are formed in the gas phase. This phenomenon causes the depletion of the gas phase precursor available for the deposition and the worsening of the surface quality, due to particulates impinging on the deposition surface. To remove the homogeneous gas phase nucleation, the use of chlorinated silicon precursors, or simply the addition of HCl, was suggested [64,65,66]. Nagasawa et al. [67] reported about the reaction paths observed by changing the operating conditions to grow 3C-SiC epitaxy. In particular, they used the “H2 intermittent flow” method with an alternating supply of dichlorosilane (SiH2Cl2) and acetylene (C2H2) as source gases. They suggested that the SiCl2 intermediate specie was formed from the thermal decomposition of SiH 2Cl2. SiCl2 was adsorbed on the surface and subsequently reduced into Si atoms by hydrogen. Si atoms on the surface quickly combine with the adsorbed C2H2 molecules and resulted in silicon carbide layer formation. SiC growth rates with the alternating supply of source gases were predominantly determined by the amount of SiCl2 incorporated into the substrate surface. Using this growth technique, they produced the first good-quality 3C-SiC film on a (001) Si wafer with a diameter of 6 inches [68]. Gao et al. [65] reported about the growth of good quality 3C-SiC layers grown on Si using SiH4-C2H4-HClH2 at a growth temperature of 1000 °C. They found an improvement in SiC crystal quality when HCl was used and two explanations were proposed. HCl eliminates gas phase Si nucleation, which interferes with epitaxy forming droplets, and allows to the adsorbed species a longer time to find the appropriate positions in the crystal lattice by reducing the growth rate. Hong et al. [69] studied the effect of various precursors on film composition in a CVD reaction system using Si2H6 and C2H2 to synthesize SiC films at low temperatures. In their study, it was suggested that SiC growth and its composition is ascribed to several intermediate species, SiH2 and HC≡CSiH3, which participate to the SiC growth with a different weight due to their probability of sticking on the substrate surface. Alkylsilane compounds have also been proposed as single source precursors for the growth of 3C-SiC films on Si within metal-organic CVD (MOCVD) working at lower growth temperature. In fact, single source


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precursors, containing directly bonded Si and C atoms, have the advantage of a simpler chemical reaction, do not require an elevated thermal budget to ensure the cracking efficiency of gasses, are considered a more efficient source than silane-propane to form Si-C bonds at the growth surface, even at lower temperatures, and they are safer to handle. For instance, silacyclobutane (c-C3H6SiH2, SCB) molecules, which have a four-member ring structure containing Si atoms bonded to C atoms, have been investigated by Yuan et al. [70] for thin film growth of SiC. Other single source precursors used in low temperature 3C-SiC heteroepitaxy are methylsilane (CH3SiH3), methyltrichlorosilane (CH3SiCl3, MTS), tetramethylsilane ({CH3}4Si, TMS), diethylsilane ({C2H5}2SiH2, DES), tripropylsilane ({C3H7}3SiH, TPS), dimethyldichlorosilane ({CH3}2SiCl2, DMDS), hexamethyldisilaneI ({CH3}6Si2, HMDS) [71,72,73,74,75,76,77,78,79]. Ferro et al. [79] reported on a comparative evaluation of hexamethyldisilane (HMDS) and silane–propane precursor systems, showing that HMDS needs a small addition of propane to deposit heteroepitaxial layers of 3C–SiC on Si with superior crystalline properties. Due to the higher intrinsic stability of HDMS, the growth temperature could not be reduced significantly without losing control on the crystal quality. However, higher growth rates (7 m/h) have been achieved with the HDMS-propane system at 1350 °C against 3 m/h for silane-propane system. Nevertheless, an intrinsic drawback of single source precursors is given by the operational restrictions on other parameters. In such a system, C- and Si-based gaseous precursors come out from an unique source, so their ratio (C/Si) is predetermined for the entire deposition process. This means that, in order to optimize the growth process conditions, the grower cannot modify the C/Si ratio and it is necessary to introduce an alternative Si-based source or a C-containing precursor to change properly the C/Si ratio, complicating further the reactions inside the chamber.

Growth temperature influence A lower temperature regime for 3C-SiC growth is highly desirable to reduce the strain generated by the mismatch in thermal expansion coefficients of SiC and Si and, consequently, the defects thereby generated. Furthermore, a reduced growth temperature should also result in a reduction of the wafer bow, as it seems mainly correlated to the thermal stress generated during the cooling down from growth temperature to room temperature as evidenced by Zielinski et al. [80]. As pointed out above, growth temperatures as low as 900 °C have been attempted for 3C-SiC/Si heteroepitaxy, mainly by using single source precursors. Single crystal 3C-SiC films on (111) Si substrates have been obtained at growth temperatures as low as 800 °C on pre-carbonized

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surfaces with propane. Steckl et al. [71] successfully investigated the growth of 3C-SiC on (001) Si at temperatures at 900°C using SCB at a growth rate of 4-5 m/h. Hurtos et al. [81] successfully deposited SiC on bare (001) Si in a hot-wall quartz reactor at temperatures below 1200°C using tetramethylsilane (TMS) as a single precursor reporting good quality 3C-SiC films grown at 1170 °C on a pre-carbonized Si surface by MBE. The dislocation density, for a half micron thick 3C-SiC film, was found to be about 1011 cm-2, the same order of magnitude to the density obtained by Golecki et al. [73] using SCB at 750 °C. It is also possible to find nanocristalline 3C-SiC growth using the reaction of (001) Si with SiCl4–CH4-Ar-H2 gas mixture in a plasma-enhanced CVD (PE-CVD) [82]. Cheng et al. [83] reported on the growth of nanodevice-grade nanocristalline 3C-SiC in a temperature range of 400-550 °C using PE-CVD. Bittencourt et al. [84] reported about a buffer layer formation with this reaction system and they reported good-quality 3C-SiC films for temperatures higher than 850°C while SiC material grown at lower temperatures was polycrystalline. Kordina et al. [85] reported on growth experiments conducted in a temperature range between 900 °C and 1300 °C using the silane-propane system. In their work, they inferred that a lower gas flow gave a higher cracking efficiency. An efficient heating of the gas phase is accomplished by the hot-wall design of the reactor, proposed by Kordina in 1997 [86]. The resulting 3C-SiC films contained defects consisting of stacking faults and microtwins on {111} planes, with the best quality material obtained at 1250 °C. Defect density generally decreased with increasing film thickness. At low temperature (1000-1100 °C) the surface mobility, surface reactions and gas phase decomposition of the propane are lower which resulted in a correspondingly higher formation rate of planar defects. At even lower growth temperature (as low as 900 °C) the columnar growth of SiC was accentuated. The highest growth temperature (1300 °C) led, on the other hand, to a worsening of the interface sharpness with a high density of large voids density in the Si. When the two-step CVD process is performed, the temperature for the initial stage of SiC growth should be lower than the growth temperature for thermodynamic reasons, as well described by Pirouz et al. [87] for a general epitaxial growth system, particularly on Si substrates. The nucleation of SiC forming nuclei has its driving force in the minimization of the free energy, which depends mainly on the volume free energy of condensation, on the interfacial energies involved and on the size of forming nuclei. Moreover, the nucleation rate depends from the process temperature. At very low temperatures, the adatoms do not have sufficient energy to move around on the substrate or to orient themselves appropriately. Hence, at these temperatures, amorphous or polycrystalline deposition occurs. Additionally,


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the precursor gases are not decomposed leading also to a low nucleation density. The formation of stable nuclei during heteroepitaxial growth requires a high volume free energy of condensation and can thus be enhanced by either large undercooling or high supersaturation, conditions that are fulfilled within a certain range of process temperature. At intermediate growth temperatures, a high nucleation rate is obtained and the growth rate is still relatively low. In addition, in this range of temperatures, the interfacial energy is such that parallel epitaxy between nuclei and substrate is highly stimulated and well-oriented 3C-SiC buffer layers are generated. At the highest temperatures, the nucleation rate decreases and a low density of nuclei are obtained due to a lowering in the volume free energy and in the interfacial energy between film and substrate. Furthermore, the low interfacial energy results in a high density of non-epitaxially oriented nuclei, which would lead to polycrystalline film growth. Intermediate initial temperatures are thus favoured to obtain single crystals during the initial stage of growth. After the initial stage, the growth is homoepitaxial and it is favourable then to switch to a higher growth temperature, where the nucleation rate is lower but the overall growth rate is higher. This description applies to the growth of 3C-SiC on Si since it is basically a nucleation growth process.

Reactor pressure influence Together with temperature, another important factor is the pressure regime within the reaction chamber. Nishino‟s first report [55] on 3C-SiC growth on Si was conducted by using an atmospheric pressure (AP) regime. A 3C-SiC film was grown on a sputtered polycrystalline 3C-SiC layer. The authors postulated that this layer, being polycrystalline, accommodated the strain between the silicon substrate and the SiC overlayer. The authors stated that, by following this 2-step APCVD recipe, good-quality 3C-SiC films could be grown on Si. Following such a recipe, in 1995, Zorman et al. [88] reported about epitaxial 3C-SiC films grown on 4 inch (001) Si wafers by APCVD and they found the films to be uniformly single crystalline across the wafers. This was the first large area growth reported in the literature since 3C-SiC/Si heteroepitaxy by 2-step CVD process was introduced. Hernandez et al. [63] presented a study of 3C-SiC growth on (111) Si substrates under AP conditions in a temperature range from 1150 °C to 1350 °C. They found an activation energy of 0.26 eV, a typical value for a mass transport mechanism for the growth controlled by the gas diffusion of the reactants through the thick boundary layer over the surface, as expected when atmospheric pressure is used. Compared to the AP process, low-pressure

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CVD (LPCVD) have been proposed for some inherent advantage in using a reduced pressure regime, i.e. a much higher gas purity within the reaction chamber and a larger area uniformity. This is related to the surface-controlled kinetic taking place over the hosting surface as a consequence of a sensible change in the gas velocity, much faster in a reduced pressure regime, and in the thermal boundary layer thickness when the reactor pressure (or the partial pressure of gasses) is reduced. As matter of facts, a much higher thickness uniformity at low working pressure is ensured since the deposition is not limited by the diffusion of the precursors through the boundary layer, being it very thin, and the gas velocities are very high. These two factors allow a much uniform distribution of reactants all over the substrate surface. The difference in growth kinetics results in a different nucleation rate of SiC on the Si surface with a higher density of SiC nuclei when LPCVD is conducted. As reported in some previous works [89,90,91], the pressure regime influences the 3C-SiC growth mode with three dimensional island growth stimulated by the secondary nucleation observed in APCVD. On the other hand, LPCVD growth results in well-faceted squared 3C-SiC islands, with an overall improvement of the crystal quality, and a higher lateral growth rate of islands. Morphologies of thin 3C-SiC films grown under LP and AP conditions are shown in figure 5 [91]. If, on one hand, 3D island growth with dendritic features are clearly recognizable in (a), well-faceted islands with some tall hillock-like feature (etch pits) is observed in (b). The reduction of etch pits in LPCVD has been explained with several mechanisms but there is still some controversy about this subject [92,93].

Figure 5. Three dimensional AFM analysis on thin 3C-SiC buffer layer grown under AP (a) and LP (b) conditions, respectively. 3D island growth with dendritic features is clearly recognizable in (a) while well-faceted islands with some tall hillock-like feature are observed in (b) [91].


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Finally, Yun et al. [94,95] showed evidences of the improved crystal quality of a 2.4 m thick 3C-SiC epilayers when the reactor pressure is reduced from 80 to 30 Torr. They observed a strong reduction in both stacking faults and micro-twins while Ishida et al. [90] observed a much higher elimination rate of anti-phase boundaries (APBs) in LPCVD growth process. Nowadays, low pressure CVD is an established technique to grow good quality 3C-SiC films while APCVD is scarcely used.

The initial stage of growth: 3C-SiC buffer layer on Si The aim of this section is to provide an introduction to the 3C-SiC buffer layer formation on Si substrate surfaces. Since before Nishino et al. introduced the 2-step growth method for the 3C-SiC heteroepitaxy on Si by CVD, a relevant interest was placed on the effect of a hydrocarbon gas on a Si surface at high temperatures. Different models and experimental observations were proposed in the seventies, with the evidence that a thin 3CSiC layer was formed on a Si surface by the conversion of Si into SiC. A milestone for the understanding of the mechanisms involved in the conversion of the Si into random or epitaxial SiC was presented by Mogab and Leamy in 1974 [96]. In their work, they proposed one of the first empirical models of Si conversion in a 3C-SiC thin layer, trying to explain the formation of voids at the interface. Basically, they found that the partial pressure of the hydrocarbon gas (acetylene, C2H2) was a critical parameter to determine the dependence of SiC film thickness and surface morphology on the reaction time at a reaction temperature ranging from 950 °C to 1100 °C. In their model, the initial reaction results in the formation of isolated SiC nuclei on the Si surface. When the partial pressure of C2H2 is sufficiently low, most of these nuclei follow the substrate orientation, and i.e. they are epitaxial. Nuclei grow laterally more than vertically, with the Si reactant being supplied from adjacent unreacted regions on the surface. At the onset of the reaction, the area fraction of unreacted Si greatly exceeds that of SiC and C2H2 molecules are adsorbed mainly on the unreacted Si surface. The lateral growth of epitaxial SiC nuclei leads to eventual coalescence of adjacent SiC islands. During this growth process, the SiC surface area increases at expense of the unreacted Si. Consequently, adsorption of C2H2 molecules occurs now to a greater extent on SiC rather than on Si. Since diffusion of Si through the epitaxial SiC layer is quite low (the diffusion coefficient of Si in SiC has been found in the range D Si=10-16÷10-10 cm2s-1 depending on the process temperature as reported in a work by Cimalla et al. [97]), the main source of Si for further growth is provided by few unreacted regions remained, which show up as porous defective regions leading to

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pitting of the substrate. The densities of such regions are directly correlated to the density and size of the initial SiC nuclei, as they will be formed at the border of coalesced SiC islands. In the regime of low partial pressure of C2H2, film growth is uniform and the growth rate of SiC constant since the rate at which Si can be supplied to the gas-solid interface, by diffusion through the porous regions, exceeds the rate at which C is supplied from the gaseous phase. Clearly, the size and density of initial nuclei, and thus the density of pits in the substrate, will vary with the temperature and with the hydrocarbon partial pressure. In the regime of high partial pressure of C 2H2, the growth sequence is assumed to be similar to that described above except that the many initial SiC nuclei are randomly oriented, their density is much higher and their size smaller, in accordance with the nucleation theory. Thus, when coalescence begins, the occluded unreacted regions are much smaller in size. In addition, in this pressure regime, the rate at which C is supplied by decomposition and adsorption of C2H2 molecules exceeds the rate at which Si is supplied by diffusion. Growth is then no longer uniform but tends to occur preferentially around the porous defects (the Si sources), leading to hillock formation. The main result of the work presented by Mogab and Leamy is definitely the influence of the precursor partial pressure on the nucleation and growth of very thin 3C-SiC layers. However, they did not report about voids formation underneath the SiC/Si interface but rather of porous region providing for Si suppliers during the reaction process. Even though single crystal 3C-SiC films have been obtained by the 2-step CVD technique, the SiC/Si interface remains a plague due to the formation of voids in the Si substrate. Voids are usually hollow inverted pyramids, with the shape depending from the orientation of the substrate, lying just beneath the interface. Their presence poses a severe problem in several applications based on 3C-SiC heteroepitaxy such as heterojunction bipolar transistors or heterojunction solar cells with 3C-SiC emitter layer as these devices require an excellent interface morphology. It has been shown in 1995 by Li and Steckl [98], and more recently by others [99,100], that voidfree SiC/Si interfaces could be formed under given growth condition, with the hydrocarbon partial pressure (propane in their case) and process temperature again as determining factors. They proposed a slightly different model from that described by Mogab and Leamy twenty years before. In details, 3C-SiC thin film growth by carbonization of Si surface starts with (i) the formation of SiC nuclei following the nucleation theory with density and size of nuclei depending on C3H8 partial pressure and process temperature; (ii) SiC nuclei grow and Si trench formation surrounding individual SiC islands are generated, with the growth of islands being nearly twodimensional for highly oversaturated C3H8 conditions or three-dimensional


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for under-saturated C3H8 conditions; (iii) occurrence of voids in Si is observed due to the continuous demand of Si to form SiC and to the lateral growth of SiC islands decreasing the unreacted Si area on the surface; (iv) voids are sealed if a continuous 3C-SiC film is formed with no detection of porous or polycrystalline aggregates as suggested by Mogab and Leamy. Other models, supported by experimental data and simulations, have also been proposed by Ferro et al. [101] and Kitabatake [102]. Interested readers are stimulated to consider them as well. In many works, voids have been detected as peculiar features affecting 3C-SiC thin films under different deposition conditions. In a work published in 2007 [103], author‟s group has correlated void density and size with the process temperature and reaction time for 3C-SiC buffer layer formation on differently oriented Si substrates. A statistical study of voids at the interface has been conducted as a function of the process temperature for the buffer layer formation. First, the temperature strongly influences the surface and interface morphology and the film thickness with the observation of an incomplete film formation and occurrence of cavities in the substrate if the temperature is too low. In figure 6, there are reported cross-section transmission electron microscopy (XTEM) images of two thin 3C-SiC films grown at 1020 °C (a) and 1120 °C (b), respectively. Channels and cavities deep into the substrate are easily observable at 1020 °C. The film is irregular on the surface, presenting some valleys at the interface and SiC traces in the

Figure 6. Cross sectional TEM analysis of (001) 3C-SiC thin layers carbonized at 1020°C (a) and 1120°C (b). Lower temperature process results in channel and deep void formation. In (a) the insert shows a double diffraction in a deep channel [103].

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channels as well. Raising up the process temperature to 1120 °C a flat interface is detected with an uniform 3C-SiC film grown on the Si substrate. As a consequence of the influence of temperature on the interface morphology, void densities and average dimensions are greatly affected by this parameter, as shown in figure 7 for thin 3C-SiC films grown on (001) Si. Average dimensions and void densities are inversely correlated due to nucleation of voids occurring during the buffer layer growth. By using the process parameters described in reference [103], it has been found that a temperature of 1120 °C gives the lower void area on total area ratio together with smoother 3C-SiC film surface. Void shape is, as expected, strictly related to the orientation of the silicon substrate used for the growth. In a diamond cubic crystal structure such as for Si, the atomic lattice packing density and the available bonds in the crystallographic plane strongly affect both the removal or the addition of the atoms on the surface. Voids on the silicon surface during the growth of a 3CSiC layer could be seen as an etching process of atoms from the substrate contributing to the formation of the growing 3C-SiC layer. The (111) oriented Si surface shows the highest atomic packing density, which is less for the (001) Si surface and is even less dense for the (110) Si surface. Since etch and deposition rates depend on this density, one would expect a faster process in the direction than in the other directions. This assumption is confirmed by figure 8, in which the thicknesses of 3C-SiC films grown at 1120 °C are reported as a function of reaction time and the highest growth rate corresponds to the (110) surface. The trend found here predicts a squared

Figure 7. Void statistics vs process temperature for the carbonization of (001) Si. (a) Void average dimension and density with process temperature. The arrows relate the experimental data with the appropriate axes. (b) Fraction of area occupied by voids with process temperature. Here the line is only a guide for the eyes [103].


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Figure 8. Linear dependence of the squared 3C-SiC buffer layer thickness with the reaction time for three different substrate orientations.

dependence of the thickness versus the process time, suggesting that the reaction is limited by the diffusion of one of the species (atoms of Si in 3C-SiC buffer layer) involved in the growth. The growth rates of 3C-SiC thin films are 0.67 ± 0.09 nm/min, 0.19 ± 0.01 nm/min, 1.85 ± 0.08 nm/min for (001), (111) and (110) Si substrates, respectively. 3C-SiC thin films with a thickness of about 8 nm have been then studied by plan view TEM resulting in another empirical model for 3C-SiC buffer layer formation, different from previous ones for the presence of large singlecrystal 3C-SiC platens forming the uniform film. The definition of 3C-SiC platens comes from the coalescence of different 3C-SiC islands laterally growing on the Si surface. The interior part of each platen consists of pure single crystal material which is affected by local misorientations, effective in relieving part of the stress generated by the heteroepitaxy. At the border of platens, where coalescence between islands occurred and the unreacted Si surface lasted for longer time, a tilt of the crystals was observed due to an underlying rougher interface as a consequence of a stronger Si out-diffusion on such zones. Once platens coalesced together, the lack of Si availability leads to stop the 3C-SiC growth process and, eventually, appearance of hillocks and carbon tubes and particles, due to an excess of carbon supply, occurs. A model of 3C-SiC buffer layer based on growth of different platens,

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as observed in PVTEM reported in figure 9, is described in figure 10. Hence, the grower should work at the optimum C-precursor partial pressure at the reaction temperature used and be able in reducing the Si out-diffusion for the substrate surface in order to produce a flat, uniform and void-free 3C-SiC buffer layers as a seed for subsequent growth of thicker 3C-SiC films. The introduction of a small amount of Si gaseous precursors during the „carbonization step‟ has been successful to suppress Si out-diffusion, to

Figure 9. (a) PVTEM analysis in bright field of 3C-SiC buffer layer with voids underneath the interface. (b) PVTEM in dark field showing platens with bent borders [103].

Figure 10. Model explaining thin 3C-SiC layer formation during carbonization of a silicon surface, based on the experimental evidence obtained through TEM and SEM analysis [103].


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eliminate voids from the hetero-interface and to obtain smooth and continuous film morphology [104].

The second stage of growth: Thick 3C-SiC films on SiC buffer layer The growth of epitaxial 3C-SiC films on Si substrates is affected by large mismatches in lattice parameters and thermal expansion coefficients, as reported above in this chapter. If a growth process is performed after the buffer layer formation, 3C-SiC films will be characterized by a very high density of defects in the first 2 or 3 microns from the interface. Crystallographic defects detected during 3C-SiC growth can be volume defects, such as microtwins (MTs), anti-phase boundaries (APBs) and protrusions, planar defects (stacking faults) and line defects (several kinds of dislocations). Some of these defects, such as MTs, have seen to vanish by growing very thick films while, in general, extended defects reduce their density but do not disappear. The reduction of these defects with the film thickness follows a selfannihilation mechanism so that most of them, such as SFs and MTs, propagate along opposite crystallographic directions and they are stimulated to meet one another in the film [90,105,106,107]. Some of these defects are also generated during the film growth, due to local strain fields or mistakes in the arrangement sequence during the deposition so that defects such as stacking faults reduce their density but they tend to a saturated value without vanishing. Hence, the defect density in SiC decreases when the 3C-SiC thickness increases. No matter which defect is considered, its density is tremendously high when thin 3C-SiC films are formed or, in other words, when the interface with Si substrate is close by. Misfit dislocation and stacking faults are the two most important paths for stress relief on such a highly mismatched heteroepitaxy. It has been observed that the best matching at the SiC/Si interface is of 5 crystalline cells of 3C-SiC with 4 crystalline cells of Si, resulting in a generation of an array of misfit dislocations spaced about 1.6 nm from one another [32,34,35]. Misfit dislocations act to relieve a large part of the stress generated at the hetero-interface. Stacking faults, whose density in nanometric thin films is higher than 109 cm-2 [106], decrease in density by increasing the film thickness but they still are present after 250 μm of growth with a density of about 5 × 103 cm-1 (density per unit length) [106], with devastating consequences on 3C-SiC based devices performances due to their experienced high electrical activity [108,109]. As observed by Song et al.

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[109] by means of scanning spreading resistance microscopy, higher electrical activity of crystallographic defects in n-type 3C-SiC can be due to accumulation of nitrogen at defects so that the current will preferentially flow through them. This observation further supports the experimental results of Nagasawa et al., that an increase of one order of magnitude in the SF linear density corresponds to an increase in the leakage current density of about three orders of magnitude at V R=600 V [30,110].

Crystal quality of 3C-SiC films The improvement of the crystal quality in thicker 3C-SiC film growth is confirmed by data reported in figure 11, where trends of the full widths at half maximum (FWHM) of (200) 3C-SiC rocking curves from different groups [111,112,113] are reported as a function of the film thickness. Several aspects of 3C-SiC heteroepitaxy, as the film microstructure, the average residual stress and the surface morphology, are tightly linked to the Si substrate orientation. In figure 12, cross-section TEM analysis of about 250 nm thick 3C-SiC films grown under the same experimental conditions on

Figure 11. The trend of FWHMs of (200) 3C-SiC rocking curves shows a reduction when the thickness of 3C-SiC films is increased as a consequence of the improved film quality.


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Figure 12. Cross-section TEM of 3C-SiC films (about 250 nm thick) grown on (a) (001) Si, (b) (110) Si and (c) (111) Si. In the insets, selected area diffraction patterns are reported [114].

different Si orientations are shown [114]. As it can be clearly observed, the surface morphology strongly changes from one orientation to another. This difference is mainly due to the available bond configurations on different Si surfaces, leading the different nucleation and subsequent growth rate of the buffer layer. Moreover, the different symmetry of the crystal affects the defect generation rate and the defect propagation into the 3C-SiC crystal. For instance, the average roughness brought by microtwins generation affects to a less extent a (111)-oriented 3C-SiC crystal, being one direction sensible to crystal twinning (running along the four {111} planes) parallel to the growth direction, thus generating double positioning boundaries (DPBs) [38,115,116]. Diametrically opposite is the case of 3C-SiC growth on (110) Si where a variation in the growth direction has been observed from the to the due to the generation of second order microtwins after about half a micron of 3C-SiC growth, leading to an extremely rough film surface [117].

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Figure 13. Cross-section TEM in dark field showing double-positioning boundaries (DPBs) (a) and standard microtwins (b). Selected area electron diffraction (SAED) patterns placing small apertures on the defects are shown in the insets [38].

In order to grow high quality 3C-SiC films suitable for device fabrication several issues arising from the growth process must first be taken into account. There are, indeed, so many variables within the deposition chamber in the reactor to be considered that their influence on the crystal quality of resulting resulting 3C-SiC films must be settled. Besides the substrate orientation and its influence on the film morphology and defects, an important parameter to be considered is the growth rate. The growth rate is proportional to the Si/H2 ratio, being Si the limiting specie in the gas phase participating to the reaction, as shown in figure 4. It was observed in previous works that the crystal quality increases when lower growth rates are used [118]. Sun et al. reported about a growth process consisting of two growth stages after the initial nucleation of SiC on Si using a C/Si=60. Stage I was performed at a lower growth rate (2.1 m/h) with a Si/H2 ratio of about 0.007% to grow a 10 m thick 3C-SiC film followed by stage II, at a growth rate of 6.2 m/h (Si/H2=0.03%). This approach was effective for growing very thick films (up to 150 m) but the increase of the growth rate brought no benefits in reducing the defect density and protrusions in very thick 3C-SiC films. The average quality of 3C-SiC films thus have a very strong correlation on both the growth rate and the final thickness as reported in figure 14 where FWHMs of (200) 3C-SiC rocking curves are reported as a function of the growth rate used. By looking at this plot, it is clear that an increase of the final 3C-SiC film thickness reduces the FWHM, i.e. improves the film quality, while an increase in the growth rate for a fixed film thickness always


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Figure 14. The trend of FWHMs of (200) 3C-SiC rocking curves as a function of the 3C-SiC growth rate. An increase of the final 3C-SiC film thickness reduces the FWHM, i.e. improves the film quality, while an increase in the growth rate for a fixed film thickness always results in a worsening of the quality with a broader FWHM.

results in a worsening of the quality with a broader FWHM. Experimental data are extracted from literature [65,79,119,120,121,122,123]. Lower growth rates were seen to be effective in reducing the densities of several kinds of crystallographic defects, for instance microtwins. In (001) 3C–SiC heteroepitaxy, microtwin density decreases when a slower growth rate process is performed, with a reduction ratio of 0.16, 0.2, and 0.28 for 2 m/ h, 5 m/h, and 10 m/h, respectively. The density of microtwins as a function of the growth rate, displayed in figure 15, was obtained by x-ray diffraction using in-plane and out-of-plane configuration and the difference between the two configurations consisted mainly on different sampled volumes [119]. This observation confirmed the improvement in the crystal quality brought by a reduced growth rate process. Same conclusions found by Yun et al. [94] where they observed an increase of MT density with the flux ratio of Si to H. Other studies have found a relationship between MT density with the total reactor pressure as well as a dependency from the relative flux ratio of C to Si on the deposition surface [68,90,91,94,95,124]. MTs are, however, considered „vanishing defects‟ as their density approaches to zero when thick 3C-SiC films are grown. The trend of MT density as a function of the 3C-SiC film thickness is reported in figure 16. This plot gives only an indication of the trend followed by MT density increasing the film thickness since the experimental conditions reported by authors were different and, sometimes,

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Figure 15. Micro-twin density vs. growth rate (or Si/H2 ratio) obtained by two different XRD analysis configurations [119].

Figure 16. MT density as a function of the film thickness. MT density tends to value below 1% after few microns of 3C-SiC growth [91,94,116,119,124].


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not comparable. However, data here reported are consistent one another as the MT density for films thicker than 3.5 m was always below 1%. In a characterization work from Polychroniadis et al. [106], performed on very thick 3C-SiC samples from HOYA, authors reported about the complete annihilation of MT after only 2 m of growth.

Device-killing defects: Anti-phase boundaries and stacking faults The primary residual defects in thick layers are antiphase boundaries (APBs) and stacking faults (SFs). APBs in 3C-SiC are the interfaces between two domains that correspond to each other through the exchange of Si and C atoms and it inevitably consists of Si–Si or C–C bonds along the {111} planes. Conversely, a SF in 3C-SiC can be regarded as hexagonal sites inserted along the {111} plane, to minimize the number of dangling bonds at the SiC/Si interface. These defects may be at least one reason of the disappointing performance reported for prototype devices fabricated from 3C-SiC. Anti-phase domains tend to expand at extent of the neighbour domains when the 3C-SiC film thickness increases and, thus, APBs decrease in density [107]. The change in surface morphology due to the reduced density of APBs is well represented by scanning electron microscopies reported in figure 17 where two 3C-SiC film surfaces of different thickness are displayed.

Figure 17. Scanning electron microscopies on 0.15 m and 10 m thick 3C-SiC films, displayed on the left and right, respectively. The two surfaces show a different morphology with a drastic change in the size of domains. 3C-SiC films were grown at USF, Tampa.

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Pirouz et al. [125] reported about the appearance of irregular boundaries in (001) 3C-SiC in 1986. Shibahara proposed a model for boundary formation with the assumption that the first grown layer by carbonization is a carbon layer [126]. In the case of heteroepitaxial growth of polar crystals on non-polar ones, if the first grown layer consists of one kind of atom, antiphase boundaries are reported to be due to the height of surface steps of a substrate. Steps with mono-atomic layer height generate anti-phase boundaries, whereas steps with bi-atomic layer height do not. So, if the height of the surface steps of a Si substrate can be controlled, growth of cubic SiC free of anti-phase boundaries is expected [68]. APD annihilation phenomena have been experimentally observed and annihilation mechanisms have been proposed by several authors. Two models have been presented based on the planes along which APBs propagate. One is {111} plane model [174], i.e., APBs propagate along direction and annihilate at the cross point of two APBs [127]. The other is {011} plane model, i.e., APBs propagate along the direction and annihilate at the cross point as in the case of the {111} model [128]. Both these models have been developed for gallium arsenide (GaAs) epilayers. Although the two models are incompatible with each other, experimental evidences supporting both of them have been reported [68,129]. A very interesting experimental study on APBs reduction has been published by Ishida et al. [89,90] where they linked the APB elimination rate with the secondary nucleation rate of 3C-SiC islands. However, the growth of 3C-SiC films on on-axis (001) Si substrates has never resulted in APB-free surface even after several tens of microns. Indeed, two adjacent domains tend to enlarge laterally on two orthogonal directions (i.e. [110] and [-110]) due to the 90° rotation around the growth direction. Breaking this symmetry, for instance by using slightly misoriented substrates, APB-free films can be produced. This requirement pushed Nagasawa et al. to develop the concept of undulant Si substrates as a template for high-quality APB-free 3C-SiC films [47,107]. While APBs can be eliminated quite easily by growing on mis-oriented Si substrates [130,131], stacking faults remain a troublesome issue in order to realize electronic devices with reliable performances. As said above, the large lattice mismatch between Si and 3C-SiC (about 20%) introduces an array of misfit dislocations, one every five {111} planes in 3C-SiC, to minimize the number of dangling bond at the SiC/Si interface and to allow the relaxation of the strain. This network of dislocation is associated with a network of stacking faults, running parallel to the {111} planes in 3C-SiC, arising close to the interface and propagating in the epitaxial film. In (001) 3C-SiC, the symmetry of {111} planes allows to terminate those SFs running along opposite planes. This results in a reduction of SF density as the thickness of


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the epitaxial film increases. However, as it was pointed out recently by Nagasawa et al. [107] for a (001) 3C-SiC film, the reduction trend shows a saturation behaviour since SFs running along the {-111} or {1-11} planes, those exposing the Si-face onto the surface, are seen to expand due to kinetic competition at the (001) surface, while the SFs exposing the C-face onto the surface tend to disappear with a effective annihilation rate. Moreover, Siterminating SFs cannot be eliminated by using mis-oriented nor undulant substrates. Stacking fault reduction in very thick 3C-SiC crystals will be discussed more thoroughly in the next chapter. The trend of stacking fault linear density (per unit length) as a function of the film thickness is displayed in figure 18, where several literature works have been considered. Experimental data reported in figure 18 show a decaying exponential trend of SF density as the 3C-SiC film thickness increases for all the considered works. In the same plot, together with experimental data from different groups [106,116,132,133,134,135], there are also reported values calculated by performing Monte-Carlo simulations calibrated on the SF density as measured after KOH etching of thick freestanding 3C-SiC wafers and microscopy inspection [110,136]. Values obtained with simulations are higher than those measured by experimental

Figure 18. SF density per unit length as a function of 3C-SiC thickness. By using conventional Si substrates, SF density tends to saturation values of about few thousands at cm-1 while this value can be decreased by using compliant substrate (i.e. undulant Si, inverted Si pyramids).

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technique so that an underestimation of SF density seems to be a common feature, regardless the analysis technique used. The reduction rate of SFs due to their self-annihilation is roughly inversely proportional to their density. This statement is further supported by Polychroniadis et al., [106] where a detailed study on the propagation of SFs using transmission electron microscopy in cross section is presented. They showed that the average length of propagating SFs was of the order of about 0.5 m in the first 3 microns of film growth, where the SF density is very high (4 × 104 cm-1), while SFs as long as 26 m were observed after 20 m of film growth (with a SF density reduced to 5 × 103 cm-1). In other words, the annihilation rate of SFs is high where a very dense network of SFs is detected and the mutual closure mechanism is stimulated. As the SF density decreases, SFs are much farther each other so that their annihilation rate falls and their density tends to a saturation value. Furthermore, for relatively thin (