351-354, Dec. 1976. ... alous behavior often observed in MOS capacitors with silicide/polysilicon ... T IS WELL KNOWN that MOS capacitance-voltage curves.
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[3] K. Lehovecand R. Zuleeg,“Voltage-currentcharacteristics of GaAs J-FET’s in the hot electron range,” Solid-state Electron., V O ~ . 13, pp. 1415-1426,1970. [4] K. Yamaguchi and H. Kodera, "Two-dimensional numeric dandysis ofstabilitycriteria ofGaAsFET’s,” IEEE Trans. Electron Devices, voL ED-23, no. 12, pp. 1283-1290, Dec. 1976. [5] B. Himsworth,“Atwo-dimensionalanalysisofgalliumarsenide junction field effecttransistorwithlongandshort channels,” Solid-State Electron., vol. 15, pp. 1353-1361, 1972. in the [6] R. Engelmannand C. Liechti,“Gunn-domainformation saturated current region of GaAsMESFET’s,” in ZEDM Tech. D i g , pp. 351-354, Dec. 1976. [7] L. 0. Chua and Y. W. Sing, “A nonlinear lumped circuit model for Gunn diode,” Int. J. Circuit Theory and Applications, vol. 6, pp, 375-408, Dec. 1978. [8] B. L. Gelmont and M. S. Shur, “Analytical theory of stable dom d n in high doped Gunn diodes,” Electron. Lett., vol. 6, no, 12, pp. 385-397, 1970.
IEEE Trans. [9] M. S. Shur, “Analytical model of GaAs MESFET,” Electron Devices, vol. ED-25, no. 6, pp. 6 12-618, June 1978. [ 101 H. Willing, “A technique for predicting, large-signal performance IEEE Trans. MicrowaveTheoryTech., ofaGaAsMESFET,” vol. MTT-26, no. 12, pp. 1017-1022, Dec. 1978. [ 111 M. S. Shur,“Small-signalnonlinearcircuit modelof GaAs MESFET,”Solid-State Electron,, vol. 22, pp. 723-728, 1979. [ 121 A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967. [ 131 C.A. Liechti,“Microwavefield-effecttransistor,” ZEEE Trans. voL MTT-24,no. 6 , pp.279-299, MicrowaveTheoryTech., June 1976. [14] R. H. Engelmann and C. A. Liechti, “Bias dependence of GaAs IEEE lYans. ElectronDevices, andInPMESFETparameters,’’ vol. ED-24, no. 11, pp. 1288-1296, Nov. 1977. [ 151 L. 0. Chua and P. M. Lin, Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques. Englewood Cliff, NJ: PrenticsHall, 1975.
Influence of a Resistive Sublayer at the PolysiIicon/SiIicon Dioxide interface on MOS Properties
Abstract-We suggest that a thin (< 100 A) resistive sublayer of polyThe situation may be quite different when thedoping profile silicon near the oxide interface can have a pronounced effect on the in a polysilicon gate is nonuniform. In particular, one mayhave MOS capacitance-voltage characteristics. On the depletion side of the a very thin (- 100 but resistive sublayer of polysilicon imC-Vcurve, thelower effective work-function difference leads to a higher mediately adjacent to the gate oxide. The existence of such a thresholdi forstrong inversion.On theaccumulation side, the MOS layer can be brought about by the very presence of the poly/ capacitance is loweredduetotheaddedthickness of thedepletion sublayer. oxide boundary which serves as a natural stop for thediffusion With the help of the sublayer model, we attempt to explain the anom- of certain deep-level impurities, such as Cu and Fe. Moreover, alous behavioroften observed inMOS capacitors with silicide/polysilicon in the vicinity of the interface, a greater percentage of donor gates. The sublayer depletion activates traps due to the heavy impurities impurities is inactive compared to that in the bulk of polysili(Cu, Fe, and Ta) at the interface, a considerable amount ofwhich were con which also contributes t o enhanced resistivity. observed in these samples byAuger spectroscopy.
a)
I.INTRODUCTION T IS WELL KNOWN that MOS capacitance-voltage curves and MOSFET thresholds are sensitive to the presence of various states in oxide and at thesilicon-oxide interface [ 1] . One is usually concerned with the state of the Si/Si02 interface or with charged states within the gate oxide but rarely with those on the outer interface of the oxides. Of course, neglecting the latter is well justified when the layer immediately over the oxide is a ]metal or highly doped polysilicon.
I
Manuslxipt received June 12, 1982;revised January 31, 1983. The authors are withBell Laboratories, Murray Hill, NJ 07974.
The presence of this resistive sublayer would produce little effect on suchcharacteristics as sheet resistivity of the polysilicon. On the other hand, it shouldmanifestitself through a degradation of MOS C-V characteristics. Qualitatively, for npoly gate and p-subtrate, the effectis twofold. First, the slope of C-V curves becomes less steep and threshold voltage of nchannel devices is shifted to higher voltages. Secondly,the MOS capacitance in the flat-band to weak-accumulation region of the C-V curve is lower due to the finite thickness of the resistive sublayer. The latter effect is unobservable on the depletion side of the curve and disappears in strong accumulation. The purpose of this paper is to suggest a possible explanation to theunusual behavior often observed in MOS devices containing a silicide-polysilicon gate structure with the metal silicide
0018-9383/83/0700-0833$01.00 0 1983 IEEE
1EZ.E TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-30, NO. 7, J U L Y 1 9 8 3
well as a washed out threshold point. The unwelcome changes were clearly introduced during the sintering. An additional high-temperature anneal produced no improvement in the characteristics. Although the C-V characteristics shown in Fig. 1 [curves (a) and ( b ) ] can undoubtedly be explained in a conventional way, assuming interface traps and fixed oxidecharges at the Si/SiOz interface, suchan explanation would necessarily involve a number of ad hoc assumptions. In particular, one would have to postulate a special combination of interface trapsand fixed oxide charges in order to explain the observed intersection of 0.41 SILICIDE I curves (a) and (b). Moreover, sucha peculiar combination POLY would appear unlikely to result from a short 900°C sintering GATE OXIDE step. We were, therefore, led to consider an alternative explap-SILICON nation, based on the idea that it was the state of the outer SUBSTRATE interface, viz., Si02/poly, rather than that of the inner oxide interface, that was responsible for the degradation of the C-V characteristics. -4 -2 0 2 To confirm this hypothesis, we took some of the samples GATE VOLTAGE ( V I which exhibited the after-sintering characteristic [Fig. 1 , curve Fig. 1. C-V characteristics of MOS capacitor with silicide gates; ' h ) be( b ) ] and etched thesilicide away. After this step, the measured fore sintering; ( b )after 30-min sintering at 900°C; ( c ) after subsc cluent curves were still identical to curve (b). However, after 15 min phosphorus diffusion (15 min,900°C) with silicide layer remov,:tl. of phosphorus diffusion at 9OO0C, the MOS characteristics produced by sputteriqand sintering. They consistently c.x.hib- returned to theiroriginal undistorted shape, [Fig. 1, curve (c)] . ited degraded C-V characteristics after high-temperatur : sin- In our view, this experiment gives a conclusive evidence of the tering. We believe that our model, which postulates'the 'exis- importance of the outer interface since a brief diffusion step tence of a resistive sublayer at poly-SiOz interface, can acl:',.)unt could not possibly affect the inner interface. Furthermore, we for all essential features of the observed behavior. Fro] i:, the carried out another experiment which also resulted in a comobserved C-V curves we make anestimate of the reqtlired plete rehabilitation of the degraded capacitors. This time we thickness of the resistive layer to be of order 60 8,w h ~ is h did not remove the silicide. After high-temperature sintering, the silicide gates were implanted with arsenic (60 kV with 7 X notunreasonable.Furthermore,our model is indirectl)supported by Auger data [ 4 ]which showed a large concentration 10"-cm-* dose). After the implantation, devices were covered of heavy impurities at the poly/Si02 interface. It is pro oable by CVD oxide (1200 8 thick) and annealed at 9OO0C for 1 h. Next, windows to the silicide gates were patterned and etched that these impurities (Cu andFe) segregate attheintt,rface through the oxide, and then theC-V characteristics were taken during the sintering step. again. This time we found the original ideal curves shown in Fig. 1, curve (a). It should be emphasized that a similar treat11. EXPERIMENTAL ment not preceded by implantation of As into the silicide proThermal oxide 4000 ,f thick i was grown on Wacker p.i.ype duced no change in the degraded C-V characteristics. Our (100) oriented wafers. The wafers were implantedth~clugh explanation of this effect will be discussed in Section IV. the oxide with boron to achieve a carrier concentration o ? 4 X 111. THE MODEL 1O'6cm-3 at the Si/Si02 interface.The oxide was subsequ :.ntly etched away and a 250-8-thickgate oxide was grown. A 3 0 1 ~ Our model assumes that during the high-temperature sintersilicon layer of thickness 3500 8 was then deposited andd zlped ing, heavy impurities (e.g., Cu or Fe), which are present in the with phosphorus by diffusion from PBr, source. Tantalulrl sil- silicide or polysilicon, diffuse in polysilicon towards the oxide icide layer (2500 8)was cosputtered on polysilicon SUI f;ace. and sink at the interface,giving rise to a high density of surface The structure was then patterned and reactive ion etched SID as traps of acceptor type. On the other hand, the dopant concento form MOS capacitors with poly/silicide upper electrodts. tration in polysilicon during high-temperature sintering is Afterpatterning,the samples were sinteredat 900"(.: for decreaseddue to diffusion of phosphorus into silicides. The 30 min in Ar atmosphere to form a stablelow-resistivity ":'Siz compensation effect of the surface traps brings aboutthe [2]. It was noticed that after the high-temperature sintt ring, formation of a highly resistive layer in polysilicon. C-V characteristics underwent a drastic change. Next, we consider the band diagram of the gate structure, A typicalresult is shown in Fig. 1 . Before sintering, the Esi'lape Fig. 2 . At equilibrium, V, = 0, the silicon layer under the oxof the curve (a) is similar to thatusually obtained with the Iply- ide is in depletion (Fig. 2(a)). The broken lines correspond to silicon gate (without silicide). After sintering, the C-V (,l~rve the presence of a depletedsublayer of polysilicon and solid lines ( b ) behaves in a manner similar to that usually attributc.(I to show the case of a uniformly andheavily doped polysilicon. the presence of a large number of interfacetraps [ 3 ] . This Consider now how our model explains the essential features characteristic behavior includes a degraded and uneven do,,:: as of the observed C-V characteristics. First, we note that the
INFLUENCE LURYI: LIFSHITZ AND
OF RESISTIVE SUBLAYER ON
1
DEPLETION vG = O
ACCUMULATION
vG
