Microelectronic Engineering 86 (2009) 1957–1960
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Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Silicon nanowire NVM with high-k gate dielectric stack Xiaoxiao Zhu a,b, D. Gu c,d, Qiliang Li a,b,*, D.E. Ioannou a,*, H. Baumgart c,d, J.S. Suehle b, C.A. Richter b a
Department of Electrical and Computer Engineering, George Mason University, 4400 University Drive, MSN 1G5, Fairfax, VA 22030, USA CMOS and Novel Devices Group, Semiconductor Electron Division, National Institute of Standards and Technology (NIST), Gaithersburg, MD 20899, USA Department of Electrical Engineering, Old Dominion University, Norfolk, VA 23529, USA d Thomas Jefferson Laboratory, Applied Research Center, Newport News, VA 23606, USA b c
a r t i c l e
i n f o
Article history: Received 3 March 2009 Received in revised form 11 March 2009 Accepted 12 March 2009 Available online 19 March 2009 Keywords: SiNW NVM Flash memory Silicon nanowire
a b s t r a c t Three flash memory cell structures with silicon nanowire channels and high-k dielectric stacks were fabricated with a ‘‘self-aligning” process and their characteristics are reported and compared in this paper: a Metal/SiO2/HfO2/SiO2/Si (MOHOS) cell with a SiO2 blocking layer and two Metal/Al2O3/HfO2/SiO2/Si (MAHOS) cells with Al2O3, all with HfO2 as the charge trapping layer. Compared to (control) planar cells, all three operate at higher speeds, attributed to the enhanced electric field across the tunneling oxide surrounding the channel. The MAHOS cells (Al2O3 blocking layer) outperform the MOHOS cells (SiO2 blocking layer) and both have large memory window, fast operation speed, good endurance and retention. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction
2. Experimental
Due to difficulties associated with scaling conventional floating gate, flash non-volatile memory (NVM) cells, SONOS and MANOS NVM cells, where charge trapping layers replace the conducting (poly-silicon) floating gate, have received increasing attention and are considered as a solution for flash memory beyond the 32-nm technology node [1,2]. The situation can be further improved by designing cells incorporating three dimensional channels such as silicon ‘‘fins” and nanowires [2,3]. We present here and compare new results on Metal/SiO2/HfO2/SiO2/Si (MOHOS) and Metal/Al2O3/HfO2/SiO2/Si (MAHOS) memory cells with Si nanowire (SiNW) channels, where the high-k dielectric HfO2 is employed as the charge trapping layer. Compared to (control) planar cells, the SiNW NVM can operate at higher speeds, which is attributed to the enhanced electric field at the interface between SiNW and surrounding tunneling oxide [2–5]. We find that the MAHOS cells (Al2O3 blocking layer) perform better than the MOHOS cells (SiO2 blocking layer) and both are characterized by large memory window, fast operation speed, good endurance and retention.
SiNWs were integrated into devices by using the self-aligning approach recently developed in our lab [6,7]. A schematic of the source/drain self-aligning process is shown in Fig. 1: (i) intrinsic SiNWs were grown at 440 °C by chemical vapor deposition (CVD) from predefined and patterned Au catalyst on a 100 nm thick thermal oxide covering the p-type silicon wafer; (ii) The SiNW surface was dry-oxidized at 700 °C for 30 min to form a 3.5 nm tunneling oxide; (iii) Al Schottky contact source/drain electrodes were patterned on SiNWs by using photolithography. After source/drain formation, a layer of HfO2 was deposited on the wafer by Atomic Layer Deposition (ALD) at 250 °C, followed by the blocking oxide (sputtered SiO2 or ALD Al2O3) deposition. Finally, top Al gate electrodes were deposited by electron beam evaporation and patterned by lift-off on the blocking oxide. Three different structures (H1, H2 and H3) with different blocking oxide layers were fabricated (see Table 1). The SiNW diameter is 20 nm and the gate length is 5 lm. A schematic of the cell cross-section is shown in Fig. 2, where it is seen that the top gate stack almost completely surrounds the SiNW channel. 3. Results and discussion
* Corresponding authors. Address: Department of Electrical and Computer Engineering, George Mason University, 4400 University Drive, MSN 1G5, Fairfax, VA 22030, USA. Tel.: +1 703 993 1596 (Q. Li); tel.: +1 703 993 1580; fax: +1 703 993 1601 (D.E. Ioannou). E-mail addresses:
[email protected] (Q. Li),
[email protected] (D.E. Ioannou). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.095
Fig. 3a–c show the current–voltage (IDS–VGS) characteristics of the Programmed and Erased (P/E at ±10 V) states of cells H1, H2 and H3, respectively, where it is seeing that the memory windows are 2, 3.5 and 3.4 V for cells H1, H2 and H3, respectively. Although the thickness of the HfO2 charge trapping layer is about the same in
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a
a
101 Device H1 VDS = -0.1V
10-1
-IDS [µA]
Au catalyst on SiO2 /Si
b
10-3
10-5
Program
10-7
Growth of SiNWs with LPCVD
Erase
c
10
-9
-6
-4
-2
0
2
4
6
VG [V] Aligning metal contacts
b
Device H2 VDS = -0.1 V
Fig. 1. Illustration of the basic steps of the self-aligning process: (a) Au catalyst (5 11 lm) is patterned on SiO2/Si substrate; (b) SiNWs are grown from Au catalyst by LPCVD; (c) metal pads are aligned with Au catalyst to form (source and drain) contacts with the SiNWs.
10
-IDS [µA]
Table 1 Three cell structures with different gate stacks. Device
Charge trapping layer
Blocking oxide
H1 H2 H3
25 nm of HfO2 by ALD 20 nm of HfO2 by ALD 20 nm of HfO2 by ALD
50 nm of SiO2 by Sputtering 40 nm of Al2O3 by ALD 20 nm of Al2O3 by ALD
101
-1
10-3
(b) 10-5
10-7
Program Erase
10
-9
-6
-4
-2
0
2
4
6
2
4
6
VG [V]
c
101 Device H3 VDS = -0.1 V
-IDS [µA]
10-1
Fig. 2. Schematic of the cross-section of a typical SiNW NVM cell. The top gate dielectric stack almost completely surrounds the SiNW channel.
all three cells (thus expecting roughly same effective areal trap densities), it is noted from these results that the memory windows of H2 and H3 cells are much improved compared to H1. To ascertain the reason for this improvement, numerical simulations were carried out by using the Synopsis TCAD Sentaurus device simulator [8] to obtain the electric filed and electrostatic potential profiles through each cell at VGS = 10 V, as shown in Fig. 4. It is seen from Fig. 4a that, consistent with their improved characteristics, the use of Al2O3 blocking layers in cells H2 and H3 results in about two (H2) to two and a half (H3) times higher electric field across the tunneling oxide compared to using SiO2 blocking layer (H1): the field strength in the order H3 > H2 > H1, leading to the observed higher trapped charge densities in cells H2 and H3, and ultimately larger memory windows. Programming and erasing characteristics at several applied voltage values are shown in Fig. 5a–c. It is seen from these results that the cell speed becomes progressively faster from cell H1 to H2
10-3
10-5 Program 10-7
10-9 -6
Erase
-4
-2
0
VG [V] Fig. 3. Drain current vs. top gate voltage curves, for Programmed and Erased states, of devices: (a) H1, (b) H2 and (c) H3. For ±10 V P/E operation, the memory windows are 2, 3.5 and 3.4 V for cells H1, H2 and H3.
to H3, reaching values faster than a microsecond for cells H3. This speed improvement is also consistent with the electric filed profiles shown in Fig. 4a: higher tunneling oxide electric field results in higher injection current and thus faster charging (i.e. faster Program) of the charge trapping HfO2 layer. Similarly, the corresponding field profiles (not shown) under Erase conditions explain the faster Erase observed going from cell H1 to H2 to H3. The endurance characteristics of the cells are shown in Fig. 6, where the Program and Erase pulses are +8 V for 1 ms and 8 V for 10 ms,
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a
b H3 HfO2 / Al2O3: 20 / 20 nm
10
Electrostatic Potential [V]
Electric Field (MV/cm)
15
H2 HfO2 / Al2O3: 20 / 40 nm 10
H1 HfO2 / SiO2: 25 / 50 nm 5
8 6 4 2
H1 HfO2 / SiO2: 25 / 50 nm H2 HfO2 / Al2O3: 20 / 40 nm
0 0 0
H3 HfO2 / Al2O3: 20 / 20 nm
SiNW
SiNW 40
20
60
-2
80
0
40
20
[nm]
60
80
[nm]
Fig. 4. Numerically simulated: (a) electric field intensity and (b) electrostatic potential distribution through the gate stack of cells H1, H2, and H3 at a gate bias of VG = 10 V.
a
b
5 +8 / -8 V
3 +6/-6V
+12 / -12 V
+8/-8V
2
+14 / -14 V
+10/-10V
3
VTH [V]
VTH [V]
+10 / -10 V
4
1 Solid: Program Open: Erase
2
Solid: Program
0
Open: Erase 1
-1
HfO2/SiO2: 25 / 50 nm
0
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0 -7 10
0
HfO2/Al2O3: 20 / 40 nm -6
10
-5
10
Time [s]
c
-3
10
-2
10
-1
10
0
10
Time [s]
4 +8 / -8 V +10 / -10 V
3
(c)
+12 / -12 V +14 / -14 V
2
VTH [V]
-4
10
1
0 Solid: Program -1
HfO2/Al2O3: 20 / 20 nm
Open: Erase -7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
Time [s] Fig. 5. Programming and erasing characteristics of cells: (a) H1, (b) H2 and (c) H3.
respectively. All cells show excellent endurance up to the tested range of 104 cycles. It is also seeing that although a moderate upward shift of the threshold voltage (Vth) of each cell for both Programmed and Erased states develops with accumulating P/E cycles, the cells maintain the same memory window (no noticeable degradation) after 104 P/E cycles. This upward shift of Vth may be due to
accumulation of ‘‘residual” electrons trapped in deep traps in the HfO2 layer. Fig. 7 shows the retention characteristics at room temperature, from which the 10-year retention threshold voltages (estimated by linear extrapolation) show a trapped charge loss of 50%, 11% and 9.1% for H1, H2, and H3, respectively. The observed large charge loss of cell H1 most likely arises from the poor
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4. Conclusions 3
Charge trapping NVM cells with SiNW channels, HfO2 trapping and Al2O3 blocking oxide layers have been fabricated with a fully CMOS compatible, self-aligning process. The resulting devices show a large memory window, faster program speed compared to planar devices, reasonable endurance and excellent retention capability, outperforming on all counts similar cells using SiO2 blocking layer. Fast cell writing speed is achieved by engineering the dielectric stacks for higher internal electric field across the tunneling oxide during the P/E process. The performance and reliability of SiNW based NVM cells with high-k gate dielectric stack therefore make them attractive for future non-volatile memory applications.
H1 H2
VTH [V]
2
H3 1
0 Solid: Program +8 V, 1 ms -1 100
Open: Erase -8 V, 10 ms 101
102
103
104
P/E Cycles Acknowledgments Fig. 6. Endurance properties of devices H1, H2 and H3.
The contribution of the National Institute of Standards and Technology is not subject to US copyright. The authors acknowledge the support of the NIST Office of Microelectronics Programs and NIST Semiconductor Electronics Division. The authors would also like to thank the NIST Center for Nanoscale Science and Technology’s Nanofab Facility for device fabrication support.
3.0 2.5 Solid: Program Open: Erase
2.0
VTH [V]
Charge loss: 1.5
References
H1 50% H2 11%
1.0
H3 9.1% 0.5 0.0 -0.5 0 10
10 years 2
10
4
10
6
10
8
10
Time [s] Fig. 7. Retention capability of cells H1, H2 and H3 at room temperature.
quality of the sputtered SiO2 as the blocking oxide, whereas the superior charge retention of cells H2 and H3 results from the high quality of the ALD deposited Al2O3 blocking layer.
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