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Single-Carrier Phase-Disposition PWM Implementation for Multilevel Flying Capacitor Converters Amer M. Y. M. Ghias, Member, IEEE, Josep Pou, Senior Member, IEEE, Gabriel J. Capella, Vassilios G. Agelidis, Senior Member, IEEE, Ricardo P. Aguilera, Member, IEEE, and Thierry Meynard, Member, IEEE

Abstract—This letter proposes a new implementation of phasedisposition pulse-width modulation (PD-PWM) for multilevel flying capacitor (FC) converters using a single triangular carrier. The proposed implementation is much simpler than conventional PD-PWM techniques based on multiple trapezoidal shaped carriers, generates the same results as far as natural capacitor voltage balance is concerned and offers better quality line-to-line voltages when compared to phase-shifted PWM. The proposed algorithm is based on re-shaping the reference signal to fit within the range of a single carrier and assigning each crossing of the reference signal with the carrier to a particular pair of switches at any time. The proposed algorithm is suitable for digital implementation taking maximum benefit from the PWM units available in the processor. Simulation and experimental results are presented from the five-level FC Converter to verify the proposed PD-PWM implementation. Index Terms—Multilevel converter; Flying capacitor converter; Natural Voltage control; Pulse-width modulation

I. I NTRODUCTION

M

ULTILEVEL converters have attracted significant interest for medium/high power applications [1]–[3]. Among various multilevel converter topologies [4], the flying capacitor (FC) converter [5] offers some advantages over the neutral-point-clamped (NPC) converter [6], such as that capacitor voltage balance can be achieved without producing low frequency voltage ripples in the FCs, even in converters with a large number of levels. Phase-shifted pulse-width modulation (PS-PWM) is a common technique applied to FC converters. PS-PWM provides natural capacitor voltage balance but the quality of line-to-line voltages is not the best. On the other hand, phase-disposition PWM (PD-PWM) produces better line-to-line voltages than This work was supported by the University of New South Wales, Australia Energy Research Institute, and the School of Electrical engineering and Telecommunications. A. M. Y. M. Ghias, J. Pou, V. G. Agelidis, and R. P. Aguilera are with Australian Energy Research Institute & School of Electrical Engineering and Telecommunications, The University of New South Wales, Sydney, NSW 2052, Australia (email: [email protected]; [email protected]; [email protected]; [email protected]). G.J.Capella is with the Department of Electronic Engineering, Technical University of Catalonia, Terrassa 08222, Spain ([email protected]). T. Meynard is with the Laboratoire d’Electrotechnique et d’Electronique Industrielle (LEEI), Institut National Polytechnique de Toulouse, Toulouse 31000, France, and also with Cirtem SA, Toulouse 31047, France ([email protected]).

PS-PWM, but it cannot be applied straightforward to the FC converter. Some solutions are based on modifying the shapes of the carriers to produce PD-PWM [7], [8]. However, each cell requires different carriers, which complicates its practical implementation, especially for FC converters with a large number of levels. The technique was simplified in [9], and the number of carriers was reduced from (n − 1)2 to (n − 1), which is the standard number of carriers used in PD-PWM. The main drawback is that it requires a lot of digital signal power processing. The property of natural capacitor voltage balance in FC converters can be boosted by the addition of RLC filters connected to the output of the converter [10]–[12]. Closedloop voltage balancing methods have also been reported in the technical literature [13]–[19]. This letter proposes a new implementation of PD-PWM for the FC converter. Unlike in [7]–[10], the proposed PDPWM implementation uses a single triangular carrier for the modulation. Tables or masks containing digital information are used to process the PWM pulses. It is very simple to apply and can be easily programmed in a digital processor requiring only a single PWM unit. The technique can be extended to FC converters with any number of levels. The letter is organized as follows. Section II describes the operating principle of a FC converter and the PD-PWM technique. Section III introduces the proposed PD-PWM implementation. Section IV presents simulation and experimental results obtained from a three-phase five-level FC converter. Finally, the conclusions are summarized in Section V. II. FC C ONVERTER AND PD-PWM A. Fundamentals Fig. 1 shows a phase-leg of an n-level FC converter, which integrates n-2 FCs. The subscript x is used for the phase identification x = {a, b, c}. The switch pairs in each phase-leg sx1 − s¯x1 , sx2 − s¯x2 ,..., and sxn−1 − s¯xn−1 operate in a complementary manner. During normal operation, the mean voltage values of the FCs, Cx1 , Cx2 ,..., and Cxn−2 , should be maintained at Vdc /(n − 1), 2Vdc /(n − 1),..., and (n − 2)Vdc /(n − 1), respectively, where Vdc is the dc-bus voltage. Consequently, the voltage across each switch is only 1/(n − 1) of the dc-bus voltage. Each converter phase-leg can generate n − 1 output voltage levels, i.e. 0, Vdc /(n − 1),

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Singl Band 1 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2427201, IEEE Transactions on Power Electronics

va0 vb0 vc0

2

1 1 0 0 1 0 1 0 1

Resulting PD Arrangement Cell 1 Carrier

Vdc

sxn1 Cdc

n2 Vdc n 1

iCxn2 Cxn 2

iCx 2

2Vdc Cx 2 n 1

sx 2

iCx1

Cell 2 Carrier Cell 3 Carrier Cell 4 Carrier

sx1

Band 4

ix

Vdc Cx1 n 1

vxref

vx

Band 3 Band 2

0

sxn1

sx 2

Band 1

sx1

Sing

Fig. 1. Phase-leg of a five-level FC Converter.

1 1 0 0 1 0 1 0 0

Cell 1

2Vdc /(n − 1),..., (n − 2)/(n − 1)Vdc , and Vdc , with respect to the dc negative rail “0”.

Cell 2

B. PD-PWM

Cell 3

In standard PD-PWM, n-1 carriers of the same amplitude, frequency, and phase are arranged in a level shifted manner that occupy the linear modulation range. The reference signal is compared with the carriers to define the voltage levels that have to be generated at the output. This technique is spectrally superior to other carrier layouts because it produces large harmonic concentration at some specific frequencies that cancel in the line-to-line voltages, hence reducing their total harmonic distortion (THD) [10], [20]. However, when PDPWM is applied to the FC converter, and each carrier should not be associated to a specific cell, otherwise capacitor voltage balance cannot be achieved. This is because the reference signal crosses a single carrier at any sampling period and hence only the cell associated to that carrier will switch. As a consequence, the FC voltages will keep on increasing or decreasing depending on the the direction of the output current ix , thus deviating from their reference values. In PS-PWM, natural capacitor voltage balance is achieved when the consecutive carriers are phase shifted by 2π/(n−1). Based on this idea, a carrier rotation technique was proposed using PD-PWM [7], [8]. This rotation implies that each specific carrier defines switching transitions to different converter cells. A similar rotation effect is achieved by re-shaping the carriers. Fig. 2 shows the carriers arrangement for a five-level FC converter. Different sets of carriers are required to achieve natural capacitor voltage balance. As it can be deduced from Fig. 2, this implementation of PD-PWM is complex, specially for converters with a high number of levels.

Cell 4 (a)

2 0 0 0 1 0 1 1 0

Singl Carrier 1

2 CellCarrier 1 Carrier

Carrier 3

Carrier4

Band 4 vxref

Band 4 Band 3 Band 3 Band 2 Band 21 Band Band 1

(b)

Fig. 2. PD-PWM in a five-level FC converter: (a) association of carrier Resulting PD Arrangement segments to FC cells and final cell pulses, and (b) standard PD-PWM Cell 1 Carrier Cell 2 Carrier Cell(Cell 3 Carrier implementation using trapezoidal carriers 1). Cell 4 Carrier v

1

xref

Cell 1 4 Band

0 1

is compared with the triangular carrier (only oneCell carrier). 2 3 Band 0 Look-up tables and some digital processing are needed to 1 define the states of all the switches, including those that have Cell 3 2 Band to0 switch during a particular sampling period. 1 The value that has to be added to the reference signal Cell 4 1 v0offsetx depends on the band bx within it is located Band (bx = {1, 2, . . . , n − 1}). In the general case of an n-level FC converter: voffsetx = (

III. P ROPOSED PD-PWM I MPLEMENTATION The PD-PWM method proposed in [7], [8] requires (n−1)2 carriers with different shapes and phase dispositions. Its implementation is complex and unpractical, especially for FC converters with a high number of levels. The proposed PDPWM implementation is based on the same concept but it is radically simplified because a single triangular carrier is used instead. To achieve this, the reference signal vxref needs to be level-shifted and re-scaled. The band where the reference signal is located (Fig. 2(b)) needs to be determined in order to know the adjustments required. The modified reference signal

2 1 0 0 1 0 1 0 1

n − 2bx + 1 Cell 1 2 )(n − bx ) − 1 = . (1) n−1 n−1 Cell 2

When this offset is added to the reference signal, the operating Cell 3 range is within the interval [0, 2/(n−1)]. In order to normalize this range into [0, 1], the signal needs to be multiplied by (n − 1)/2, as follows: Cell 4 0 vxref = (vxref + vof f set )

Carrier 1

Carrier 2

Carrier 3

n−1 . 2

Sing

(2)

Carrier4

vxref Fig. 3(a) shows an example of reference signal with the Band 4 corresponding bands in the case of a five-level FC converter. Band 3 Band 2 Band 1

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1 2 1 0 vxref0 0 0 0 1 1Sin 0 1 0 0 0 1 02 0 1 01 0 0 Single 0 0 1 1 0 0 1 2 1 1 1 00 0 0 10 1 0 1 0 0Sin 0 0 0 0 1 2 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0

1 1 0 0 1 0 0 0 0

2 0 0 0 1 1 0 0 0

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Band Band Reference, Reference, bbx

Reference ReferenceSignal, Signal, vvxref

x

xref

v 0xref = 3 + 2vxref − bx .

bbx=4 =4

11

x

From (1) and (2) considering n = 5, reshaping the reference signal is done using the following equation: (3)

bx=3 b =3 x

b =2 bx =2

0 0

Modulation is performed by comparing the rescaled reference signal with the triangular carrier (Fig. 3(b)) producing the -1 so-called raw PWM. The raw PWM needs to be processed to bbx=1 -1 =1 x define the state of each FC converter cell. Digital processing 0 0.01 0.02 0 0.01 0.02 is performed using masks that are allocated in look-up tables. Time (s) Time (s) The amount of intervals considered in the masks depends on (a) the number of levels of the FC converter by the relationship Rescaled Reference Signal, v'xref Triangular Carrier 2(n − 1). Therefore, in this example where n = 5, the number Rescaled Reference Signal, v'xref Triangular Carrier of intervals is eight. The masks are designed to decide whether 1 1 the control signal of a converter cell is ‘1’, ‘0’, or a transition ‘1’-‘0’ or ‘0’-‘1’ defined by the raw PWM. The masks are obtained from the information provided in Fig. 2 [7], [8]. Fig. 4(a) shows an example for Band 3. In this example, the output signal that defines the state of Cell 1 (sx1 ) is ‘0’ during 0 the Intervals 2 and 3, and ‘1’ during the Intervals 5-8. In the 00 0.01 0.02 Interval 1, there is a transition ‘1’-’0’, and in the Interval 4, 0 0.01 0.02 Time (s) Time (s) the transition is in the opposite direction, i.e. ‘0’-’1’. Such (b) transitions are defined by the crossing of the reference signal Fig. 3. Single carrier PWM implementation: (a) reference signal and band with the triangular carrier, i.e. by the raw PWM. signal, and (b) modified reference signal and triangular carrier. Fig. 4 shows a possible implementation for the digital processing. The information included in the masks is designed 1 2 3 4 5 6 7 8 Counter Single Carrier Waveform according to this digital implementation. Coming back to the Band 3 Dedicated example in Fig. 3, when the counter indicates Intervals 1 or 4, 1 for 2 3 4 5 6 7 8 Counter Single CarrierCarrier vxref Waveform Cell 1 (sx1) the raw PWM should be applied to Cell 1. To achieve this, the 1 Band 3 Raw Dedicated information provided by the Mask A is ‘1’ (Mask A1 signal) Carrier for 0 vxref PWM and it leads the raw PWM to the output of the AND gate Cell 1 (sx1) 1 1 Raw sx1 associated to Cell 1 (Fig. 4(b)). During those intervals, the PWM 0 0 Mask B should provide a ‘0’ (Mask B1 signal) to let the raw 1Switching PWM 0 0 PWM 1 1 1 1 PWM reach the output sx1 through the OR gate. When the sx1 Transition ON ON 0 counter indicates Intervals 2 or 3, the Mask A1 signal is ‘0’, for Cell 1 imposing the output of the AND gate to be ‘0’ and therefore Switching PWM ‘-’ Do Not Care (sx1) 0 0 PWM 1 1 1 1 Transition Mask preventing the raw PWM to go to the next stage. The final ON A1 ON 1 0 0 1 for Cell 1 output for Cell 1 is defined by the state of mask B (signal Mask B1 0 0 0 0 1 1 1 1 ‘-’ Do Not Care (sx1) Mask B1), which is ‘0’ in this case. Similarly, the output sx1 1 0 0 1 Mask A1 is imposed to be ‘1’ by the signal Mask B1 during the Intervals Mask B1 0 0 0 0 1 1 1 1 5-8. Using this simple two-signal masks, the state of each cell is defined. Fig. 5 shows the block diagram for the proposed (a) implementation. Table I shows the masks for all the cells and Mask B1 bands in the case of a five-level FC converter. Raw PWM sx1 OR AND The generation of the masking codes is done off-line and, Mask A1 given a specific n−level FC converter, the masks are always Mask B1 Mask B2 the same. The mask pointer needs to be synchronized with sx2 OR Raw PWM sx1 OR AND AND the carrier signal and it increases whenever the slope of the Mask A1 Mask A2 carrier changes. The number of the interval is odd/even when Mask B2 Mask B3 sx3 OR sx2 the carrier signal has a positive/negative slope, respectively. OR AND AND Mask A2 Mask A3 Table II shows the comparison of the proposed PD-PWM implementation with the methods presented in [7]–[10]. Mask B4 Mask B3 sx4 OR s OR x3 AND x

Mask A3

Mask A4 AND

(b) Mask B4 sx4analysis of intervals and Fig. 4. Generation of PWM signals usingOR masks: (a) (b) proposed digital AND processing circuitry. Mask A4

IV. S IMULATIONS AND E XPERIMENTAL R ESULTS Simulations and Experimental tests are performed on a low power grid-connected five-level FC converter. The proposed PD-PWM implementation has been programmed in a DSPACE

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1

2

3 4 5 6 7

8 Counter

Resulting PD Arrangement

1 1 issue 0 0 of 0 this 0 0journal, 0 Maskbut A1 has not been fully edited. Content may change prior to final publication. Citation information: DOI Cell article 1 1 been 0 0 accepted 1 0 0 0for0 publication Mask A1 This has in a future Cell 1 Cell 1 Cell 2 Carrier Cell 3 Carrier Cell 4 Carrier 0 10.1109/TPEL.2015.2427201, 0 1 1 1 1 1 1 Mask B1 vxref 0 0 0 0 1 1 1 1 Mask B1 IEEE Transactions on Power Electronics

Cell 1 Carrier

Cell 2

0 1 0 1 0 0

Cell 3 Cell 4

Band 4

0 1 0 1 1 0

1 0 0 1 0 1

0 0 0 1 0 1

0 0 1 0 0 1

1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 Band 1 0 0

Detector Single Carrier Waveform

Band 3

r4

vxref

Band 4

Band 2

Band 3

Band 4 Band Band 12 Band 3 Band 1 Band 2 Band 1 Cell 1

Band 1

Band 1

Band 1 Band 2

Carrier 2

1 0 0 Carrier 3 0 1 1 33 44 55 66 77 00000 1 00 001 00 10110 0 10 100 10 11 10 00 00 00 00000 0 10 100 10 00101 1 11 101 00 10 10 00 00 10 00000 0 00 010 11 10110 1 10 101 00

0 0 0 0 Band Carrier4 Band 41 1 1 1vxref1 88 Counter CounterBand 4 00 Mask 0 A1 0 0 1 Mask A1 Cell Cell 11 1 Mask 10 Mask 1 B1 1Band 13 B1 00 Mask Mask A2 A2 Cell 2 Cell 110 Mask 1 0 Band042 Mask B2 B2Band 2 0 Mask A3 00 Mask 0 A3 1 Cell 1 Cell 333 10 Mask B3 Band Mask B3Band 1 010 Mask 0 A4 1 1 Mask A4 Cell Cell 244 0 Mask B4 10 Mask 1 B4 0Band 0

Single Carrier Waveform

Band 1

Cell 1 Single Carrier Waveform Band 3

1 2 3 4 5 6 7 8 CounterCell 2 Resulting Cell 1 1 0PD0Arrangement 1 0 0 0 0 Mask A1 Cell 31 Cell 1 Carrier Cell 20Carrier CarrierB1Cell 0 0Cell 0 3 1Carrier 1 1 Cell 1 4Mask vxref8 1 2 3 4 5 6 7 Cell 2 0 0 1 0 0 1 0 0 Mask A2 Cell 42 Band Cell 1 1 11 00 0 0 0 01 1 0 1 Mask 0 B2 0Cell 04 Cell 3 0 0 0 0 1 0 0 1 Mask A3 Cell 0 0 0 0 1 1 1Band 133 1 1 1 1 0 0 0 0 Mask B3 CellCell2 4 0 0 1 0 00 01 00 1 0 0 Mask A4 1 0Band 0 Cell 24 0 0 1 1 1 1 0 0 Mask B4

Cell 3

4

vxref Band 4

Cell 4

Band 3

Band 1 vxref

Band 4 Cell 1

Carrier 1

Band Cell 3 2 Cell 3

Band 2 Cell 4

Band 1

1

0 1

Cell 1

0 1

0Cell 1

2

0

Cell 3

Cell 4

0 1 0 1 0 1

1 0 0 1 0 1

1 0 0 0 1 1 0 1 1 1 0 0 0 Mask 0 0 1Signals 1 1

0 1 0 1 1 0

0 1 0 1 1 0

Mask A2 Cell 2 Mask B2 Mask A3 Cell 3 Mask B3 Mask A4 Cell 4 Mask B4

Code Single Carrier WaveformDigital Sequencer Signal Raw Band 3 PWM Processing 1 2 3 4 5 6 7 8 Counter Comparator

Mask A Cell 1 Mask B 1 2 3 4 5 6 7 Mask A 1 0 0Cell 0 02 1 0 Mask 0 B 0 0 0 0 0 1 0 0 1 0 0 0 0 Mask A 0Band0 0 0 1 1 0Cell 3 Mask 0 B 1 0 Detector 0 1 0 0 0 0 1 1 0 0 0 Mask A 1 0 0 1 vxref0 0 0Modulation Cell 4 v' Signal Rescaler Mask 0 B 0 0 0 1 1 0

4

sx1 sx2 sx3 sx4

TABLE III PARAMETERS OF G RID -C ONNECTED FC C ONVERTER

Cell 1

Cell 2 Cell 3 Cell 4

Band 2

8 0 1 1 0 0 0 0 xref 0

Counter Mask A1 Cell 1 Mask B1 Mask A2 Cell 2 Mask Mask B2 Signals Code sx1 Mask A3 Sequencer Digital sx2 Cell 3 Signal Raw Mask B3 sx3 PWM Processing Mask A4 Comparator sx4 Cell 4 Mask B4 CH2:vdc

Circuit Parameter RMS Grid Voltage, E Dc-Bus Voltage Source, Vdc Dc-Bus Capacitor, Cdc Flying Capacitors, C1 , C2 , C3 Grid Inductance, L Carrier Frequency, fs Fundamental Frequency, f Balance booster inductance, Lb Balance booster capacitance, Cb Balance booster resistor, Rb

CH3:vCa1

Value 60 V 110V 2 mF 220 µF 6 mH 4.1 kHz 50 Hz 1mH 1.5µF 68Ω

CH4:vCa2 CH5:vCa3

Single SingleCarrier CarrierWaveform Waveform Band Band 14 11 23 2 Band 11 01 00 00 Counter 00 10 01 A 01 Mask 00 00 Mask B 01 01 00 A 00 Mask 01 01

33 44 55 66 00 00 00 00 01 01 01 01 11 01 00 00 00 00 01 01 00Cell 10 111 01 01 01 00 00 00 00 00 10 01Cell 01 012 01

77 00 01 00 01 00 01 11 00

88 10 01 00 01 00 01 01 00

Counter Counter Mask Mask A1 A1 Cell 11 Cell Mask Mask B1 B1 Mask A2 A2 Mask Cell 22 Cell Mask B2 B2 Mask Mask A3 A3 Mask Cell 33 Cell Mask B3 B3 Mask Mask A4 Mask A4 Cell 44 Cell Mask B4 B4 Mask

1 1 0 0 0 0 1 1 Mask B Band 1 Single Carrier Waveform 0 0 0 0 1 0 0 1 Mask A Band 2 Cell 3 Band 3 1 1 1 1 0 0 0 0 Mask B 1 2 controller 3 4 5 6 7 with 8 Counter 1006 integrated DS board. The 1 2 5203 3 4 5 FPGA 6 7 8 Counter 0 A11Cell 01 Mask1 A0 0 1 0 0 0 0 Mask A1 1 0 0 0 10 00 100 0 0 Mask parameters of the converter in table III. Cell 1are given Cell 4 Cell 1 0 0 0 0 00 01 011 1 1 Mask 0 B 0 0 0 1 1 1 1 Mask B1 1 B1 0 proposed 0 Mask The performance of the PD-PWM implementation

CH1:vab

CH6:va

Single Carrier Waveform

0

Band 2

0 1 0 1 0 1

2 3 4 Modulation 5 6 7 8 Counter v'xref 1 0 0 0Signal 0 1 Rescaler 0 0 Mask A1 Cell 1 1 0 0 1 0 0 0 0 Mask A1 Cell 1 0 0 0 0 0 0 1 1 Mask B1 0 0 0 0 1 1 1 1 Mask B1 Cell Mask 2 0 0 1 0 0 0 0 1 Mask A2 0 0 1 0 0 1 0 0 Mask A2 Band Carrier Cell 2 Signals Fig.1 5.1 Single Diagram of the proposed PD-PWM implementation. Waveform Code 0Detector 0 0 0 0 0 Mask B2 1 1 0 sx1 0 0 0 1 1 Mask B2 Sequencer Digital Cell 3 0 1 0 0 1 0 0 0 Mask A3 0 0 0 sx2 0 1 0 0 1 Mask A3 Signal CellRaw 3 0 0 Modulation 1 1 0 0 0 0 Mask B3 PWM Band 1I 41 1 sx3 1 0 0 0 0 Mask B3 Processing TABLE vxref 0 0 Signal 0 1Rescaler 0 0 v'1xref 0 Comparator Mask A4 Cell 4 0 1 FC 0 sx4 0 C0ONVERTER 0 1 0 Mask A4 4 -L EVEL M ASKS U SED IN ACell F IVE 0 10 02 0 31 14 0 50 Mask 0 0 1 1 1 1 0 0 Mask B4 6 B4 7 8 Counter Single Carrier Waveform Single Carrier Waveform Single Carrier Waveform

vxref1

1 0 vxrefCell 2 11 22 11 010 Band 43 rrier 00 100 vCell xref 00 01 Band Cell 4 Cell 4 1 Carrier 10 010 Band 3 00 100 Band 3 10 10 00 000 Band 2 Band 2 10 110 Carrier 1

Mask A2 Band Cell4 2 Mask B2 Mask A3 Band Cell3 3 Mask B3 Mask A4 Band Cell2 4 Mask B4

0

1 0 0 0 0

1 Mask A2Cell 2 Cell 2

0 0 1 0 0 1 0 0 Mask A2

Cell 2 Mask B2 1 Single 0 0 under 0Carrier 0 0 a0Waveform 1 1 0 0 on 0 0a 1 grid-connected 1 Mask B2 is 1tested closed-loop operation 0 1 0 0 1 0 0 0 Mask A3Cell 3 0 0 0 0 1 0 0 1 Mask A3 3 FC0 converter, as shown inCellFig. 6. An RLC voltage balancing Cell 3 0 1 1 0 0 0 0 Mask B3 Band1 21 1 1 0 0 0 0 Mask B3 0 0 0 is 1 connected 0 0 1 0 Maskto 4 converter booster the output [7]–[9]. The dcA4Cell 0 1 0 0 0 0 1 0 Mask A4 Cell 4 Cell 4 0 0 0 1 1 0 0 Mask B4 0 0 source 1 1 1 with 1 0 0 VMask = bus0 1voltage voltage dc B4 110V. 2 3is4provided 5 6 7by 8dc Counter Single Carrier Waveform Single Carrier Waveform Traditional current 1 0 Carrier 0 decoupled 0 0Carrier4 1 0id -i0q Mask A control loops are used Carrier 2 3 Band 2 Band 1 Cell 1 v[21]. for the grid connection The FCs xref 0 0 0 0 0 0 1 1 Mask B are charged using the 1 2 3 4 5 6 7 8 Counter Band 4 1 2 3 4 5 6 7 8 Counter precharging method proposed in [22]. The line-to-line voltage 0 0 00 01 000 01 Mask 0 A10 1 Mask 1 A 0 0 0 0 1 0 0 Mask A1 Cell 1 Cell 2(v 1 11 ,Mask Cell 1 FC voltages vab10 , 00dc-bus voltage vdc and vCa , and B1 2 0 B 0 0 0 0 0 Ca 1 0 10 00 000 00 Mask 0 B10Band0 3 Mask 0 1 0 0 0maintains 0 1 Mask A2the FC vCa Fig. Mask A2 6(a). The0 converter 0 3 1 ) 1are 0 shown 0 0 0 0in Cell 2 Cell 10 Mask 0 B20 Band 022 Mask 1 A 1∗ 0 0 0 0 0 0 Mask ∗ B2 0 0 0 0 10at00 the 00 0 reference voltages values (V = 27.5V, VC2 = 55V, Cell 3 C1 A3 0 1 0 0 1 0 0 0 Mask 0∗ 0 0 0 01 11 01 0 0 0 Mask A3 B 03 Mask Cell 3 VC3 = 82.5V). At t0 =0 Cell 50ms, the changes 0 0reference 1 1 0 0 current 0 0 Mask B3 0 0 0 0 0 0 0 0 Mask B3 Band 1 ∗ ∗ 0 0 0 1 0 0 1 0 Mask A 0 0 0 1 0 0 1 0 Mask A4 0 0 i0 =3A Mask A4 As it can be observed, the proposed from Cell 4 d 0 0 1to1 i0d =5A. Cell 4 0 0 0Cell 0 14 1 0 0 Mask B4 0 0 0 0 00 00 00 0 1 0 Mask Mask B well 1 B40 0 performs PD-PWM implementation under closed-loop Single Carrier Waveform operation the voltages Cell 1 in the FCs remain unaffected Singleand Carrier Waveform Band 1 during this transient. Fig. 6(b) shows similar results obtained Cell 2

Band1 12

3 4 5 6 7 8 Counter 1 0 0 0 0 0 0 1 Mask A1 Cell 1 Cell 3 0 0 0 0 0 0 0 0 Mask B1 1 2 3 4 5 6 7 8TABLE Counter 0II 1 1 0 0 0 0 0 Mask A2 Cell 2 Cell 4 B2 C1OMPARISON ULTILEVEL 0 0MMask 0 0 0 OF0PD-PWM 0 0 I1MPLEMENTATIONS Mask0 A0 0 0 0 IN0 FC 0 0 0Cell 1 11 0 0 0 Mask A3 C ONVERTERS 0 0 0 0 0 0 0 0 Mask0 B0 0 0 0 0 0 0 Mask B3 Cell 3 0 0 1 Implementation 1 0 Mask A4 A0 0 of 0 PD-PWM 1 1 0 0 0Number 0 0 ofMask0Shape Cell 4 0 0 0Cell 0 02 0 0 0 Mask B4

B 0 Carriers 0 0 MaskCarriers 1 Triangular 0 0 0 2 Mask A Cell 3 (n − 1) Trapezoidal 0 0 0 Mask B n−1 Triangular 0 0 0 0 0 1 1 0 Mask A Cell 4 0 0 0 0 0 0 0 0 Mask B

Implementations 0 0 0 0 0 Proposed one 0 0 0 1 1 [7], [8], [10] 0 0 0 0 0 [9]

Difficulty Low High Medium

CH8: ib CH9: ic CH7: ia CH1:80V/div CH2:80V/div CH3:80V/div CH4:80V/div TB: 10ms/div CH5:80V/div CH6:30V/div CH7:4.0A/div CH8:4.0A/div CH9:4.0A/div (a) Simulation

CH2:vdc

CH3:vCa1

CH1:vab

CH4:vCa2 CH5:vCa3

CH6:va

CH7: ia CH8: ib CH9: ic CH1:80V/div CH2:80V/div CH3:80V/div CH4:80V/div TB: 10ms/div CH5:80V/div CH6:30V/div CH7:4.0A/div CH8:4.0A/div CH9:4.0A/div (b) Experimental Fig. 6. Closed-loop grid-connected FC converter operating with the proposed modulation technique. The dc-bus voltage is provided by dc voltage source with Vdc = 110V. The current reference changes from i∗d =3A to i∗d =5A at t=50ms. Top waveforms: line-to-line output voltage, dc-bus and FC voltages. Bottom waveforms: grid voltage and output currents. (a) Simulation and (b) experimental results.

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experimentally from the laboratory prototype. V. C ONCLUSION In this letter, a new implementation of PD-PWM for a FC converter using just a single carrier has been presented. The modulation signals have been properly level-shifted and rescaled to operate in the range of a single triangular carrier. The PWM pulses have been digitally processed to achieve the same effect as in the case of other complex implementations based on using several trapezoidal carriers. The proposed PDPWM implementation has been presented in a general way so that it could be applied to FC converters with any number of levels. It is easy to apply and very suitable to be processed in a digital processor. In this letter, the proposed PD-PWM implementation has been tested on a five-level FC converter together with an RLC voltage balancing booster and it has shown excellent results.

R EFERENCES [1] V. Yaramasu, B. Wu, and J. Chen, “Model-predictive control of gridtied four-level diode-clamped inverters for high-power wind energy conversion,” IEEE Trans. Power Electron., vol. 29, no. 6, pp. 2861-2873, Jun. 2014. [2] T. Freddy, N. A. Rahim, W. P. Hew, and H. S. Che, “Comparison and analysis of single-phase transformerless grid-connected PV inverters,” IEEE Trans. Power Electron., vol. 29, no. 10, pp. 5358-5369, Oct. 2014. [3] V. Yaramasu and B. Wu, “Predictive control of a three-level boost converter and an NPC inverter for high-power PMSG-based medium voltage wind energy conversion systems,” IEEE Trans. Power Electron., vol. 29, no. 10, pp. 5308-5322, Oct. 2014. [4] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Fraquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and industrial application of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553-2580, Jun. 2010. [5] T. A. Meynard and H. Foch, “Multi-level conversion: High voltage choppers and voltage-source inverters,” in Proc. IEEE PESC, 29 Jun.– 3 Jul. 1992, vol. 1, pp. 397–403. [6] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. IA–17, no. 5, pp. 518–523, Sep./Oct. 1981. [7] S. Lee, D. Kang, Y. Lee, and D. Hyun, “The carrier-based PWM method for voltage balance of flying capacitor multilevel converter,” in IEEE PESC, Jun. 2001, vol.1, pp. 126–131.

[8] D. W. Kang, B. K. Lee, J. H. Jeon, T. J. Kim, and D. S. Hyun, “A symmetric carrier technique of CRPWM for voltage balance method of flying-capacitor multilevel inverter,” IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 879–888, Jun. 2005. [9] A. Shukla, A. Ghosh, and A. Joshi, “Natural balancing of flying capacitor voltages in multicell inverter under PD carrier-based PWM,” IEEE Trans. Power Electron., vol. 26, no. 6, pp. 1682–1693, Jun. 2011. [10] B. P. Mcgrath and D. G. Holmes, “Enhanced voltage balancing of a flying capacitor multilevel converter using phase (PD) modulation,” IEEE Trans. Power Electron., vol. 26, no. 7, pp. 1933–1942, Jul. 2011. [11] B.P. Mcgrath and D. G. Holmes, “Analytical determination of the capacitor voltage balancing dynamics for three phase flying capacitor converters,” IEEE Trans. Ind. Appl., vol. 45, no. 4, pp. 1425–1433, Jul. 2009. [12] B.P. Mcgrath and D. G. Holmes, “Natural capacitor voltage balancing for a flying capacitor converter induction motor drive,” IEEE Trans. Power Electron., vol. 24, pp. 1554–1561, Jun. 2009. [13] S. Thielemans, A. Ruderman, B. Reznikov, and J. Melkebeek, “Improved natural balancing with modified phase-shifted PWM for single-leg fivelevel flying-capacitor converters,” IEEE Trans. Power Electron., vol. 27, no. 4, pp. 1658–1667, Apr. 2012. [14] G. Gateau, M. Fadel, P. Maussion, R. Bensaid, and T. A. Meynard, “Multicell converters: Active control and observation of flying capacitor voltages,” IEEE Trans. Ind. Electron., vol. 49, no.5, pp. 998–1008, Oct. 2002. [15] C. Feng, J. Liang, and V. G. Agelidis, “Modified phase-shifted PWM control for flying capacitor multilevel converters,” IEEE Trans. Power Electron., vol. 22, pp. 178–185, Jan. 2007. [16] S. Choi and M. Saeedifard, ”Capacitor voltage balancing of flying capacitor multilevel converters by space vector PWM,” IEEE Trans. Power Del., vol. 27, no. 3, pp. 1154–1161, Jul. 2012. [17] M. Khazraei, H. Sepahvand, K. A. Corzine, and M. Ferdowsi, “Active capacitor voltage balancing in single-phase flying-capacitor multilevel power converters,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 769– 778, Feb. 2012. [18] A. M. Y. M. Ghias, J. Pou, M. Ciobotaru, and V. G. Agelidis, “Voltage balancing method using phase-shifted PWM for the flying capacitor multilevel converter,” IEEE Trans. Power Electron., vol. 29, no. 9, pp. 4521-4531, Sep. 2014. [19] A. M. Y. M. Ghias, J. Pou, V. G. Agelidis, and M. Ciobotaru, “Optimal switching transition-based voltage balancing method for flying capacitor multilevel converters,” IEEE Trans. Power Electron., vol. 30, no. 4, pp. 1804-1817, Apr. 2015. [20] V. G. Agelidis and M. Calais, ”Application specific harmonic performance evaluation of multicarrier PWM techniques,” in Proc. IEEE PESC, 17–22 May 1998, vol. 1, pp. 172–178. [21] L. Chen, A. Amirahmadi, Q. Zhang, N. Kutkut, and I. Batarseh, “Design and implementation of three-phase two-stage grid-connected module integrated converter,” IEEE Trans. Power Electron., vol. 29, no. 8, pp. 3881-3892, Aug. 2014. [22] A. M. Y. M. Ghias, J. Pou, V. G. Agelidis, and M. Ciobotaru, “Initial capacitor charging in grid-connected flying capacitor multilevel converters,” IEEE Trans. Power Electron., vol. 29, no. 7, pp.3245-3249, Jul. 2014.

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Single-Carrier Phase-Disposition PWM Implementation for Multilevel Flying Capacitor Converters Amer M. Y. M. Ghias, Member, IEEE, Josep Pou, Senior Member, IEEE, Gabriel J. Capella, Vassilios G. Agelidis, Senior Member, IEEE, Ricardo P. Aguilera, Member, IEEE, and Thierry Meynard, Member, IEEE

Abstract—This letter proposes a new implementation of phasedisposition pulse-width modulation (PD-PWM) for multilevel flying capacitor (FC) converters using a single triangular carrier. The proposed implementation is much simpler than conventional PD-PWM techniques based on multiple trapezoidal shaped carriers, generates the same results as far as natural capacitor voltage balance is concerned and offers better quality line-to-line voltages when compared to phase-shifted PWM. The proposed algorithm is based on re-shaping the reference signal to fit within the range of a single carrier and assigning each crossing of the reference signal with the carrier to a particular pair of switches at any time. The proposed algorithm is suitable for digital implementation taking maximum benefit from the PWM units available in the processor. Simulation and experimental results are presented from the five-level FC Converter to verify the proposed PD-PWM implementation. Index Terms—Multilevel converter; Flying capacitor converter; Natural Voltage control; Pulse-width modulation

I. I NTRODUCTION

M

ULTILEVEL converters have attracted significant interest for medium/high power applications [1]–[3]. Among various multilevel converter topologies [4], the flying capacitor (FC) converter [5] offers some advantages over the neutral-point-clamped (NPC) converter [6], such as that capacitor voltage balance can be achieved without producing low frequency voltage ripples in the FCs, even in converters with a large number of levels. Phase-shifted pulse-width modulation (PS-PWM) is a common technique applied to FC converters. PS-PWM provides natural capacitor voltage balance but the quality of line-to-line voltages is not the best. On the other hand, phase-disposition PWM (PD-PWM) produces better line-to-line voltages than This work was supported by the University of New South Wales, Australia Energy Research Institute, and the School of Electrical engineering and Telecommunications. A. M. Y. M. Ghias, J. Pou, V. G. Agelidis, and R. P. Aguilera are with Australian Energy Research Institute & School of Electrical Engineering and Telecommunications, The University of New South Wales, Sydney, NSW 2052, Australia (email: [email protected]; [email protected]; [email protected]; [email protected]). G.J.Capella is with the Department of Electronic Engineering, Technical University of Catalonia, Terrassa 08222, Spain ([email protected]). T. Meynard is with the Laboratoire d’Electrotechnique et d’Electronique Industrielle (LEEI), Institut National Polytechnique de Toulouse, Toulouse 31000, France, and also with Cirtem SA, Toulouse 31047, France ([email protected]).

PS-PWM, but it cannot be applied straightforward to the FC converter. Some solutions are based on modifying the shapes of the carriers to produce PD-PWM [7], [8]. However, each cell requires different carriers, which complicates its practical implementation, especially for FC converters with a large number of levels. The technique was simplified in [9], and the number of carriers was reduced from (n − 1)2 to (n − 1), which is the standard number of carriers used in PD-PWM. The main drawback is that it requires a lot of digital signal power processing. The property of natural capacitor voltage balance in FC converters can be boosted by the addition of RLC filters connected to the output of the converter [10]–[12]. Closedloop voltage balancing methods have also been reported in the technical literature [13]–[19]. This letter proposes a new implementation of PD-PWM for the FC converter. Unlike in [7]–[10], the proposed PDPWM implementation uses a single triangular carrier for the modulation. Tables or masks containing digital information are used to process the PWM pulses. It is very simple to apply and can be easily programmed in a digital processor requiring only a single PWM unit. The technique can be extended to FC converters with any number of levels. The letter is organized as follows. Section II describes the operating principle of a FC converter and the PD-PWM technique. Section III introduces the proposed PD-PWM implementation. Section IV presents simulation and experimental results obtained from a three-phase five-level FC converter. Finally, the conclusions are summarized in Section V. II. FC C ONVERTER AND PD-PWM A. Fundamentals Fig. 1 shows a phase-leg of an n-level FC converter, which integrates n-2 FCs. The subscript x is used for the phase identification x = {a, b, c}. The switch pairs in each phase-leg sx1 − s¯x1 , sx2 − s¯x2 ,..., and sxn−1 − s¯xn−1 operate in a complementary manner. During normal operation, the mean voltage values of the FCs, Cx1 , Cx2 ,..., and Cxn−2 , should be maintained at Vdc /(n − 1), 2Vdc /(n − 1),..., and (n − 2)Vdc /(n − 1), respectively, where Vdc is the dc-bus voltage. Consequently, the voltage across each switch is only 1/(n − 1) of the dc-bus voltage. Each converter phase-leg can generate n − 1 output voltage levels, i.e. 0, Vdc /(n − 1),

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Singl Band 1 This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2427201, IEEE Transactions on Power Electronics

va0 vb0 vc0

2

1 1 0 0 1 0 1 0 1

Resulting PD Arrangement Cell 1 Carrier

Vdc

sxn1 Cdc

n2 Vdc n 1

iCxn2 Cxn 2

iCx 2

2Vdc Cx 2 n 1

sx 2

iCx1

Cell 2 Carrier Cell 3 Carrier Cell 4 Carrier

sx1

Band 4

ix

Vdc Cx1 n 1

vxref

vx

Band 3 Band 2

0

sxn1

sx 2

Band 1

sx1

Sing

Fig. 1. Phase-leg of a five-level FC Converter.

1 1 0 0 1 0 1 0 0

Cell 1

2Vdc /(n − 1),..., (n − 2)/(n − 1)Vdc , and Vdc , with respect to the dc negative rail “0”.

Cell 2

B. PD-PWM

Cell 3

In standard PD-PWM, n-1 carriers of the same amplitude, frequency, and phase are arranged in a level shifted manner that occupy the linear modulation range. The reference signal is compared with the carriers to define the voltage levels that have to be generated at the output. This technique is spectrally superior to other carrier layouts because it produces large harmonic concentration at some specific frequencies that cancel in the line-to-line voltages, hence reducing their total harmonic distortion (THD) [10], [20]. However, when PDPWM is applied to the FC converter, and each carrier should not be associated to a specific cell, otherwise capacitor voltage balance cannot be achieved. This is because the reference signal crosses a single carrier at any sampling period and hence only the cell associated to that carrier will switch. As a consequence, the FC voltages will keep on increasing or decreasing depending on the the direction of the output current ix , thus deviating from their reference values. In PS-PWM, natural capacitor voltage balance is achieved when the consecutive carriers are phase shifted by 2π/(n−1). Based on this idea, a carrier rotation technique was proposed using PD-PWM [7], [8]. This rotation implies that each specific carrier defines switching transitions to different converter cells. A similar rotation effect is achieved by re-shaping the carriers. Fig. 2 shows the carriers arrangement for a five-level FC converter. Different sets of carriers are required to achieve natural capacitor voltage balance. As it can be deduced from Fig. 2, this implementation of PD-PWM is complex, specially for converters with a high number of levels.

Cell 4 (a)

2 0 0 0 1 0 1 1 0

Singl Carrier 1

2 CellCarrier 1 Carrier

Carrier 3

Carrier4

Band 4 vxref

Band 4 Band 3 Band 3 Band 2 Band 21 Band Band 1

(b)

Fig. 2. PD-PWM in a five-level FC converter: (a) association of carrier Resulting PD Arrangement segments to FC cells and final cell pulses, and (b) standard PD-PWM Cell 1 Carrier Cell 2 Carrier Cell(Cell 3 Carrier implementation using trapezoidal carriers 1). Cell 4 Carrier v

1

xref

Cell 1 4 Band

0 1

is compared with the triangular carrier (only oneCell carrier). 2 3 Band 0 Look-up tables and some digital processing are needed to 1 define the states of all the switches, including those that have Cell 3 2 Band to0 switch during a particular sampling period. 1 The value that has to be added to the reference signal Cell 4 1 v0offsetx depends on the band bx within it is located Band (bx = {1, 2, . . . , n − 1}). In the general case of an n-level FC converter: voffsetx = (

III. P ROPOSED PD-PWM I MPLEMENTATION The PD-PWM method proposed in [7], [8] requires (n−1)2 carriers with different shapes and phase dispositions. Its implementation is complex and unpractical, especially for FC converters with a high number of levels. The proposed PDPWM implementation is based on the same concept but it is radically simplified because a single triangular carrier is used instead. To achieve this, the reference signal vxref needs to be level-shifted and re-scaled. The band where the reference signal is located (Fig. 2(b)) needs to be determined in order to know the adjustments required. The modified reference signal

2 1 0 0 1 0 1 0 1

n − 2bx + 1 Cell 1 2 )(n − bx ) − 1 = . (1) n−1 n−1 Cell 2

When this offset is added to the reference signal, the operating Cell 3 range is within the interval [0, 2/(n−1)]. In order to normalize this range into [0, 1], the signal needs to be multiplied by (n − 1)/2, as follows: Cell 4 0 vxref = (vxref + vof f set )

Carrier 1

Carrier 2

Carrier 3

n−1 . 2

Sing

(2)

Carrier4

vxref Fig. 3(a) shows an example of reference signal with the Band 4 corresponding bands in the case of a five-level FC converter. Band 3 Band 2 Band 1

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1 2 1 0 vxref0 0 0 0 1 1Sin 0 1 0 0 0 1 02 0 1 01 0 0 Single 0 0 1 1 0 0 1 2 1 1 1 00 0 0 10 1 0 1 0 0Sin 0 0 0 0 1 2 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0

1 1 0 0 1 0 0 0 0

2 0 0 0 1 1 0 0 0

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Band Band Reference, Reference, bbx

Reference ReferenceSignal, Signal, vvxref

x

xref

v 0xref = 3 + 2vxref − bx .

bbx=4 =4

11

x

From (1) and (2) considering n = 5, reshaping the reference signal is done using the following equation: (3)

bx=3 b =3 x

b =2 bx =2

0 0

Modulation is performed by comparing the rescaled reference signal with the triangular carrier (Fig. 3(b)) producing the -1 so-called raw PWM. The raw PWM needs to be processed to bbx=1 -1 =1 x define the state of each FC converter cell. Digital processing 0 0.01 0.02 0 0.01 0.02 is performed using masks that are allocated in look-up tables. Time (s) Time (s) The amount of intervals considered in the masks depends on (a) the number of levels of the FC converter by the relationship Rescaled Reference Signal, v'xref Triangular Carrier 2(n − 1). Therefore, in this example where n = 5, the number Rescaled Reference Signal, v'xref Triangular Carrier of intervals is eight. The masks are designed to decide whether 1 1 the control signal of a converter cell is ‘1’, ‘0’, or a transition ‘1’-‘0’ or ‘0’-‘1’ defined by the raw PWM. The masks are obtained from the information provided in Fig. 2 [7], [8]. Fig. 4(a) shows an example for Band 3. In this example, the output signal that defines the state of Cell 1 (sx1 ) is ‘0’ during 0 the Intervals 2 and 3, and ‘1’ during the Intervals 5-8. In the 00 0.01 0.02 Interval 1, there is a transition ‘1’-’0’, and in the Interval 4, 0 0.01 0.02 Time (s) Time (s) the transition is in the opposite direction, i.e. ‘0’-’1’. Such (b) transitions are defined by the crossing of the reference signal Fig. 3. Single carrier PWM implementation: (a) reference signal and band with the triangular carrier, i.e. by the raw PWM. signal, and (b) modified reference signal and triangular carrier. Fig. 4 shows a possible implementation for the digital processing. The information included in the masks is designed 1 2 3 4 5 6 7 8 Counter Single Carrier Waveform according to this digital implementation. Coming back to the Band 3 Dedicated example in Fig. 3, when the counter indicates Intervals 1 or 4, 1 for 2 3 4 5 6 7 8 Counter Single CarrierCarrier vxref Waveform Cell 1 (sx1) the raw PWM should be applied to Cell 1. To achieve this, the 1 Band 3 Raw Dedicated information provided by the Mask A is ‘1’ (Mask A1 signal) Carrier for 0 vxref PWM and it leads the raw PWM to the output of the AND gate Cell 1 (sx1) 1 1 Raw sx1 associated to Cell 1 (Fig. 4(b)). During those intervals, the PWM 0 0 Mask B should provide a ‘0’ (Mask B1 signal) to let the raw 1Switching PWM 0 0 PWM 1 1 1 1 PWM reach the output sx1 through the OR gate. When the sx1 Transition ON ON 0 counter indicates Intervals 2 or 3, the Mask A1 signal is ‘0’, for Cell 1 imposing the output of the AND gate to be ‘0’ and therefore Switching PWM ‘-’ Do Not Care (sx1) 0 0 PWM 1 1 1 1 Transition Mask preventing the raw PWM to go to the next stage. The final ON A1 ON 1 0 0 1 for Cell 1 output for Cell 1 is defined by the state of mask B (signal Mask B1 0 0 0 0 1 1 1 1 ‘-’ Do Not Care (sx1) Mask B1), which is ‘0’ in this case. Similarly, the output sx1 1 0 0 1 Mask A1 is imposed to be ‘1’ by the signal Mask B1 during the Intervals Mask B1 0 0 0 0 1 1 1 1 5-8. Using this simple two-signal masks, the state of each cell is defined. Fig. 5 shows the block diagram for the proposed (a) implementation. Table I shows the masks for all the cells and Mask B1 bands in the case of a five-level FC converter. Raw PWM sx1 OR AND The generation of the masking codes is done off-line and, Mask A1 given a specific n−level FC converter, the masks are always Mask B1 Mask B2 the same. The mask pointer needs to be synchronized with sx2 OR Raw PWM sx1 OR AND AND the carrier signal and it increases whenever the slope of the Mask A1 Mask A2 carrier changes. The number of the interval is odd/even when Mask B2 Mask B3 sx3 OR sx2 the carrier signal has a positive/negative slope, respectively. OR AND AND Mask A2 Mask A3 Table II shows the comparison of the proposed PD-PWM implementation with the methods presented in [7]–[10]. Mask B4 Mask B3 sx4 OR s OR x3 AND x

Mask A3

Mask A4 AND

(b) Mask B4 sx4analysis of intervals and Fig. 4. Generation of PWM signals usingOR masks: (a) (b) proposed digital AND processing circuitry. Mask A4

IV. S IMULATIONS AND E XPERIMENTAL R ESULTS Simulations and Experimental tests are performed on a low power grid-connected five-level FC converter. The proposed PD-PWM implementation has been programmed in a DSPACE

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1

2

3 4 5 6 7

8 Counter

Resulting PD Arrangement

1 1 issue 0 0 of 0 this 0 0journal, 0 Maskbut A1 has not been fully edited. Content may change prior to final publication. Citation information: DOI Cell article 1 1 been 0 0 accepted 1 0 0 0for0 publication Mask A1 This has in a future Cell 1 Cell 1 Cell 2 Carrier Cell 3 Carrier Cell 4 Carrier 0 10.1109/TPEL.2015.2427201, 0 1 1 1 1 1 1 Mask B1 vxref 0 0 0 0 1 1 1 1 Mask B1 IEEE Transactions on Power Electronics

Cell 1 Carrier

Cell 2

0 1 0 1 0 0

Cell 3 Cell 4

Band 4

0 1 0 1 1 0

1 0 0 1 0 1

0 0 0 1 0 1

0 0 1 0 0 1

1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 Band 1 0 0

Detector Single Carrier Waveform

Band 3

r4

vxref

Band 4

Band 2

Band 3

Band 4 Band Band 12 Band 3 Band 1 Band 2 Band 1 Cell 1

Band 1

Band 1

Band 1 Band 2

Carrier 2

1 0 0 Carrier 3 0 1 1 33 44 55 66 77 00000 1 00 001 00 10110 0 10 100 10 11 10 00 00 00 00000 0 10 100 10 00101 1 11 101 00 10 10 00 00 10 00000 0 00 010 11 10110 1 10 101 00

0 0 0 0 Band Carrier4 Band 41 1 1 1vxref1 88 Counter CounterBand 4 00 Mask 0 A1 0 0 1 Mask A1 Cell Cell 11 1 Mask 10 Mask 1 B1 1Band 13 B1 00 Mask Mask A2 A2 Cell 2 Cell 110 Mask 1 0 Band042 Mask B2 B2Band 2 0 Mask A3 00 Mask 0 A3 1 Cell 1 Cell 333 10 Mask B3 Band Mask B3Band 1 010 Mask 0 A4 1 1 Mask A4 Cell Cell 244 0 Mask B4 10 Mask 1 B4 0Band 0

Single Carrier Waveform

Band 1

Cell 1 Single Carrier Waveform Band 3

1 2 3 4 5 6 7 8 CounterCell 2 Resulting Cell 1 1 0PD0Arrangement 1 0 0 0 0 Mask A1 Cell 31 Cell 1 Carrier Cell 20Carrier CarrierB1Cell 0 0Cell 0 3 1Carrier 1 1 Cell 1 4Mask vxref8 1 2 3 4 5 6 7 Cell 2 0 0 1 0 0 1 0 0 Mask A2 Cell 42 Band Cell 1 1 11 00 0 0 0 01 1 0 1 Mask 0 B2 0Cell 04 Cell 3 0 0 0 0 1 0 0 1 Mask A3 Cell 0 0 0 0 1 1 1Band 133 1 1 1 1 0 0 0 0 Mask B3 CellCell2 4 0 0 1 0 00 01 00 1 0 0 Mask A4 1 0Band 0 Cell 24 0 0 1 1 1 1 0 0 Mask B4

Cell 3

4

vxref Band 4

Cell 4

Band 3

Band 1 vxref

Band 4 Cell 1

Carrier 1

Band Cell 3 2 Cell 3

Band 2 Cell 4

Band 1

1

0 1

Cell 1

0 1

0Cell 1

2

0

Cell 3

Cell 4

0 1 0 1 0 1

1 0 0 1 0 1

1 0 0 0 1 1 0 1 1 1 0 0 0 Mask 0 0 1Signals 1 1

0 1 0 1 1 0

0 1 0 1 1 0

Mask A2 Cell 2 Mask B2 Mask A3 Cell 3 Mask B3 Mask A4 Cell 4 Mask B4

Code Single Carrier WaveformDigital Sequencer Signal Raw Band 3 PWM Processing 1 2 3 4 5 6 7 8 Counter Comparator

Mask A Cell 1 Mask B 1 2 3 4 5 6 7 Mask A 1 0 0Cell 0 02 1 0 Mask 0 B 0 0 0 0 0 1 0 0 1 0 0 0 0 Mask A 0Band0 0 0 1 1 0Cell 3 Mask 0 B 1 0 Detector 0 1 0 0 0 0 1 1 0 0 0 Mask A 1 0 0 1 vxref0 0 0Modulation Cell 4 v' Signal Rescaler Mask 0 B 0 0 0 1 1 0

4

sx1 sx2 sx3 sx4

TABLE III PARAMETERS OF G RID -C ONNECTED FC C ONVERTER

Cell 1

Cell 2 Cell 3 Cell 4

Band 2

8 0 1 1 0 0 0 0 xref 0

Counter Mask A1 Cell 1 Mask B1 Mask A2 Cell 2 Mask Mask B2 Signals Code sx1 Mask A3 Sequencer Digital sx2 Cell 3 Signal Raw Mask B3 sx3 PWM Processing Mask A4 Comparator sx4 Cell 4 Mask B4 CH2:vdc

Circuit Parameter RMS Grid Voltage, E Dc-Bus Voltage Source, Vdc Dc-Bus Capacitor, Cdc Flying Capacitors, C1 , C2 , C3 Grid Inductance, L Carrier Frequency, fs Fundamental Frequency, f Balance booster inductance, Lb Balance booster capacitance, Cb Balance booster resistor, Rb

CH3:vCa1

Value 60 V 110V 2 mF 220 µF 6 mH 4.1 kHz 50 Hz 1mH 1.5µF 68Ω

CH4:vCa2 CH5:vCa3

Single SingleCarrier CarrierWaveform Waveform Band Band 14 11 23 2 Band 11 01 00 00 Counter 00 10 01 A 01 Mask 00 00 Mask B 01 01 00 A 00 Mask 01 01

33 44 55 66 00 00 00 00 01 01 01 01 11 01 00 00 00 00 01 01 00Cell 10 111 01 01 01 00 00 00 00 00 10 01Cell 01 012 01

77 00 01 00 01 00 01 11 00

88 10 01 00 01 00 01 01 00

Counter Counter Mask Mask A1 A1 Cell 11 Cell Mask Mask B1 B1 Mask A2 A2 Mask Cell 22 Cell Mask B2 B2 Mask Mask A3 A3 Mask Cell 33 Cell Mask B3 B3 Mask Mask A4 Mask A4 Cell 44 Cell Mask B4 B4 Mask

1 1 0 0 0 0 1 1 Mask B Band 1 Single Carrier Waveform 0 0 0 0 1 0 0 1 Mask A Band 2 Cell 3 Band 3 1 1 1 1 0 0 0 0 Mask B 1 2 controller 3 4 5 6 7 with 8 Counter 1006 integrated DS board. The 1 2 5203 3 4 5 FPGA 6 7 8 Counter 0 A11Cell 01 Mask1 A0 0 1 0 0 0 0 Mask A1 1 0 0 0 10 00 100 0 0 Mask parameters of the converter in table III. Cell 1are given Cell 4 Cell 1 0 0 0 0 00 01 011 1 1 Mask 0 B 0 0 0 1 1 1 1 Mask B1 1 B1 0 proposed 0 Mask The performance of the PD-PWM implementation

CH1:vab

CH6:va

Single Carrier Waveform

0

Band 2

0 1 0 1 0 1

2 3 4 Modulation 5 6 7 8 Counter v'xref 1 0 0 0Signal 0 1 Rescaler 0 0 Mask A1 Cell 1 1 0 0 1 0 0 0 0 Mask A1 Cell 1 0 0 0 0 0 0 1 1 Mask B1 0 0 0 0 1 1 1 1 Mask B1 Cell Mask 2 0 0 1 0 0 0 0 1 Mask A2 0 0 1 0 0 1 0 0 Mask A2 Band Carrier Cell 2 Signals Fig.1 5.1 Single Diagram of the proposed PD-PWM implementation. Waveform Code 0Detector 0 0 0 0 0 Mask B2 1 1 0 sx1 0 0 0 1 1 Mask B2 Sequencer Digital Cell 3 0 1 0 0 1 0 0 0 Mask A3 0 0 0 sx2 0 1 0 0 1 Mask A3 Signal CellRaw 3 0 0 Modulation 1 1 0 0 0 0 Mask B3 PWM Band 1I 41 1 sx3 1 0 0 0 0 Mask B3 Processing TABLE vxref 0 0 Signal 0 1Rescaler 0 0 v'1xref 0 Comparator Mask A4 Cell 4 0 1 FC 0 sx4 0 C0ONVERTER 0 1 0 Mask A4 4 -L EVEL M ASKS U SED IN ACell F IVE 0 10 02 0 31 14 0 50 Mask 0 0 1 1 1 1 0 0 Mask B4 6 B4 7 8 Counter Single Carrier Waveform Single Carrier Waveform Single Carrier Waveform

vxref1

1 0 vxrefCell 2 11 22 11 010 Band 43 rrier 00 100 vCell xref 00 01 Band Cell 4 Cell 4 1 Carrier 10 010 Band 3 00 100 Band 3 10 10 00 000 Band 2 Band 2 10 110 Carrier 1

Mask A2 Band Cell4 2 Mask B2 Mask A3 Band Cell3 3 Mask B3 Mask A4 Band Cell2 4 Mask B4

0

1 0 0 0 0

1 Mask A2Cell 2 Cell 2

0 0 1 0 0 1 0 0 Mask A2

Cell 2 Mask B2 1 Single 0 0 under 0Carrier 0 0 a0Waveform 1 1 0 0 on 0 0a 1 grid-connected 1 Mask B2 is 1tested closed-loop operation 0 1 0 0 1 0 0 0 Mask A3Cell 3 0 0 0 0 1 0 0 1 Mask A3 3 FC0 converter, as shown inCellFig. 6. An RLC voltage balancing Cell 3 0 1 1 0 0 0 0 Mask B3 Band1 21 1 1 0 0 0 0 Mask B3 0 0 0 is 1 connected 0 0 1 0 Maskto 4 converter booster the output [7]–[9]. The dcA4Cell 0 1 0 0 0 0 1 0 Mask A4 Cell 4 Cell 4 0 0 0 1 1 0 0 Mask B4 0 0 source 1 1 1 with 1 0 0 VMask = bus0 1voltage voltage dc B4 110V. 2 3is4provided 5 6 7by 8dc Counter Single Carrier Waveform Single Carrier Waveform Traditional current 1 0 Carrier 0 decoupled 0 0Carrier4 1 0id -i0q Mask A control loops are used Carrier 2 3 Band 2 Band 1 Cell 1 v[21]. for the grid connection The FCs xref 0 0 0 0 0 0 1 1 Mask B are charged using the 1 2 3 4 5 6 7 8 Counter Band 4 1 2 3 4 5 6 7 8 Counter precharging method proposed in [22]. The line-to-line voltage 0 0 00 01 000 01 Mask 0 A10 1 Mask 1 A 0 0 0 0 1 0 0 Mask A1 Cell 1 Cell 2(v 1 11 ,Mask Cell 1 FC voltages vab10 , 00dc-bus voltage vdc and vCa , and B1 2 0 B 0 0 0 0 0 Ca 1 0 10 00 000 00 Mask 0 B10Band0 3 Mask 0 1 0 0 0maintains 0 1 Mask A2the FC vCa Fig. Mask A2 6(a). The0 converter 0 3 1 ) 1are 0 shown 0 0 0 0in Cell 2 Cell 10 Mask 0 B20 Band 022 Mask 1 A 1∗ 0 0 0 0 0 0 Mask ∗ B2 0 0 0 0 10at00 the 00 0 reference voltages values (V = 27.5V, VC2 = 55V, Cell 3 C1 A3 0 1 0 0 1 0 0 0 Mask 0∗ 0 0 0 01 11 01 0 0 0 Mask A3 B 03 Mask Cell 3 VC3 = 82.5V). At t0 =0 Cell 50ms, the changes 0 0reference 1 1 0 0 current 0 0 Mask B3 0 0 0 0 0 0 0 0 Mask B3 Band 1 ∗ ∗ 0 0 0 1 0 0 1 0 Mask A 0 0 0 1 0 0 1 0 Mask A4 0 0 i0 =3A Mask A4 As it can be observed, the proposed from Cell 4 d 0 0 1to1 i0d =5A. Cell 4 0 0 0Cell 0 14 1 0 0 Mask B4 0 0 0 0 00 00 00 0 1 0 Mask Mask B well 1 B40 0 performs PD-PWM implementation under closed-loop Single Carrier Waveform operation the voltages Cell 1 in the FCs remain unaffected Singleand Carrier Waveform Band 1 during this transient. Fig. 6(b) shows similar results obtained Cell 2

Band1 12

3 4 5 6 7 8 Counter 1 0 0 0 0 0 0 1 Mask A1 Cell 1 Cell 3 0 0 0 0 0 0 0 0 Mask B1 1 2 3 4 5 6 7 8TABLE Counter 0II 1 1 0 0 0 0 0 Mask A2 Cell 2 Cell 4 B2 C1OMPARISON ULTILEVEL 0 0MMask 0 0 0 OF0PD-PWM 0 0 I1MPLEMENTATIONS Mask0 A0 0 0 0 IN0 FC 0 0 0Cell 1 11 0 0 0 Mask A3 C ONVERTERS 0 0 0 0 0 0 0 0 Mask0 B0 0 0 0 0 0 0 Mask B3 Cell 3 0 0 1 Implementation 1 0 Mask A4 A0 0 of 0 PD-PWM 1 1 0 0 0Number 0 0 ofMask0Shape Cell 4 0 0 0Cell 0 02 0 0 0 Mask B4

B 0 Carriers 0 0 MaskCarriers 1 Triangular 0 0 0 2 Mask A Cell 3 (n − 1) Trapezoidal 0 0 0 Mask B n−1 Triangular 0 0 0 0 0 1 1 0 Mask A Cell 4 0 0 0 0 0 0 0 0 Mask B

Implementations 0 0 0 0 0 Proposed one 0 0 0 1 1 [7], [8], [10] 0 0 0 0 0 [9]

Difficulty Low High Medium

CH8: ib CH9: ic CH7: ia CH1:80V/div CH2:80V/div CH3:80V/div CH4:80V/div TB: 10ms/div CH5:80V/div CH6:30V/div CH7:4.0A/div CH8:4.0A/div CH9:4.0A/div (a) Simulation

CH2:vdc

CH3:vCa1

CH1:vab

CH4:vCa2 CH5:vCa3

CH6:va

CH7: ia CH8: ib CH9: ic CH1:80V/div CH2:80V/div CH3:80V/div CH4:80V/div TB: 10ms/div CH5:80V/div CH6:30V/div CH7:4.0A/div CH8:4.0A/div CH9:4.0A/div (b) Experimental Fig. 6. Closed-loop grid-connected FC converter operating with the proposed modulation technique. The dc-bus voltage is provided by dc voltage source with Vdc = 110V. The current reference changes from i∗d =3A to i∗d =5A at t=50ms. Top waveforms: line-to-line output voltage, dc-bus and FC voltages. Bottom waveforms: grid voltage and output currents. (a) Simulation and (b) experimental results.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2427201, IEEE Transactions on Power Electronics 5

experimentally from the laboratory prototype. V. C ONCLUSION In this letter, a new implementation of PD-PWM for a FC converter using just a single carrier has been presented. The modulation signals have been properly level-shifted and rescaled to operate in the range of a single triangular carrier. The PWM pulses have been digitally processed to achieve the same effect as in the case of other complex implementations based on using several trapezoidal carriers. The proposed PDPWM implementation has been presented in a general way so that it could be applied to FC converters with any number of levels. It is easy to apply and very suitable to be processed in a digital processor. In this letter, the proposed PD-PWM implementation has been tested on a five-level FC converter together with an RLC voltage balancing booster and it has shown excellent results.

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