Single-Stage Power Factor Correction AC-DC Converter Based on Continuous Input Current Charge-Pump Topologies Cícero S. Postiglione, Arnaldo J. Perin
Claudinor B. Nascimento
Institute of Power Electronics - INEP Federal University of Santa Catarina – UFSC Florianópolis, BRAZIL
[email protected],
[email protected]
Technological Federal University of Paraná Ponta Grossa, PR – BRAZIL
[email protected]
Abstract— This paper presents a new single-stage power factor corrected (PFC) ac-dc converter. The topology is based on CIC-CPPFC (Continuous Input Current Chargepump Power Factor Correction) technique, achieving continuous conduction mode (CCM) input current with high power factor and reduced current ripple by using a coupled inductor, meeting IEC 61000-3-2 regulations for wide load range without additional input filter. The converter operates with zero voltage switching (ZVS) resulting in high efficiency for a wide load range. It is also a cost effective and competitive solution for low power applications where a two stage approach is costly and passive filters are not recommended. Another feature is the absence of a bulky dclink capacitor, reducing costs and presenting a significant advantage over many single-stage solutions.
I.
INTRODUCTION
Power supplies are used to convert the mains voltage AC to low voltage DC needed to power various consumer and office electronic products. Today, there are over 10 billion electronic power supplies in use worldwide [1]. Usually the first stage of these power converters is a diode rectifier followed by a bulky capacitor, demanding from the mains non-sinusoidal line currents with high harmonic distortion and low power factor (PF). In addition, their efficiency is low, typically under 70% [1]. In order to reduce power quality degradation brought about by electronic equipments, standards such as IEC 61000-3-2 have been created. Therefore, high power factor with low total harmonic distortion (THD) became a requirement for the utility companies. To meet these requirements the study and development of power factor correction (PFC) techniques for switch-mode power supplies became expressive, resulting in many solutions. The simplest way to achieve PFC is to add a passive filter before the rectifier. However, passive PFC is not recommended for applications above 100 W mainly because of size and weight constrains [2]. For such cases, high frequency switch-mode PFC converters are more suitable. The most common active PFC technique is the two-stage approach, which consists in the addition of a front-end converter for PFC, typically the boost converter, to the dc-dc converter,. However, overall efficiency is reduced, since the input power is processed twice. Furthermore, the addition of another converter and its control circuitry implies in high cost for low power applications [3]. To overcome these drawbacks, singlestage PFC approaches have been developed. The main idea behind single-stage techniques is to integrate the
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PFC stage with the dc-dc converter into a single ac-dc converter. Unfortunately, most of the proposed singlestage topologies, especially those based on a single power switch and(or) operating in discontinuous conduction mode (DCM), suffer from low efficiency due to switching losses, high current stress, high voltage on the dc-link capacitor and high EMI noise [4]. The search for more efficient topologies led to complex converters; some authors even suggest the use of full-bridge and LCC resonant converters, which could cost as much as a two-stage solution, due to the large number of components and auxiliary circuits required. Therefore the advantages over the two-stage approach are minimal [5]. Besides PFC, another important characteristic to be considered in the development of SMPS is efficiency. Over the past years, the United States (Environmental Protection Agency (EPA) ENERGY STAR® program and the State of California), China, Europe, Canada, and Australia have been working together to explore ways to encourage the improved energy efficiency of external power supplies and thereby reduce the power consumed by those finished products that are sold with an external power supply. The environmental advocacy group Natural Resources Defense Council (NRDC) estimates that movement toward more efficient external power supplies has the potential to save more than 25 billion kWh annually on a worldwide basis [6]. Thus, high efficiency must be pursued in any new power supply design. While full-load efficiency is important, new requirements are demanding a flatter efficiency curve, with requirements at light loads as well. While the requirements for external power supplies specify efficiency, averaging data at four different load values (25%, 50%, 75% and 100% of rated load), the internal computer power supply requires a minimum efficiency given for each of four different loads. In either case, maintaining high efficiency at a load of 20% of rated power represents a significant design task [7]. In this work a single-stage PFC converter suitable for low power (75 - 300 W) SMPS is presented. The main advantages of the proposed converter are high power factor and high efficiency, both for wide-load range. The converter topology is based on CIC-CPPFC technique, typically used in electronic ballasts and known for its high power factor with the addition of few passive elements [8]-[13], therefore presenting low cost and high power density.
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II. PROPOSED CONVERTER
III. ANALYSIS AND DESIGN EQUATIONS
The proposed converter schematic circuit is presented in Fig. 1. It is a combination of a CIC-CPPFC [11] with a ZVS half-bridge converter. Unlike previously proposed topologies [12]-[14], the inverter is connected between the input capacitors Cfi, i = 1, 2, and the power switches, resulting in a different converter, with different operation stages and characteristics. This allowed a significant reduction of the dc-link capacitor from hundreds to just a few microfarads. Only a small capacitance is necessary, in order to keep the voltage ripple negligible at the switching frequency and its voltage can be kept under 400V for the entire load range. In addition, capacitor CB is only responsible for delivering a fraction of the output energy, some part is transferred directly from the input, therefore, increasing efficiency. Furthermore, the PFC feature does not imply in additional current to the power switches. Any current that goes through the switches has to go through the transformer, increasing the efficiency even more.
In the present analysis, the mains voltage is considered to be in its positive half-cycle, close to the peak and the circuit is operating in steady-state with a constant switching frequency (fs) and a duty cycle of 50%, which closely represents the circuit operation at the maximum power. The switching frequency is much higher than the mains frequency and input voltage Vin(t) can be considered constant over one switching period. Thus, current through capacitor Cf1 can be written as follows: dvCf 1 (t ) d (vin vCf 2 (t )) iCf 1 (t ) C f 1 Cf1 dt dt (1) dvCf 2 (t ) C f 1 iC f 2 (t ) dt Capacitors Cf1 and Cf2 have the same values of capacitance and they are large enough to neglect the voltage ripple across them during one switching period. The following considerations are also taken into account: x Inductors Lin1 and Lin2 have the same values of magnetizing inductances and the leakage inductance is negligible; x Capacitors CS1 and CS2 are the parasitic capacitances of switches S1 and S2, respectively; x The dc-link capacitor, CB, is large enough so that dc-link voltage ripple is negligible over one switching period; x Voltage across capacitor Cin never reaches zero; x The secondary circuits are refered to the primary side; x The transformer is modeled by its magnetizing (Lm) and leakage (Lr) inductances. All other components are assumed to be ideal.
Fig. 1 - Proposed converter
Another advantage of this PFC technique over most single-stage (S2) solutions based on DCM operation is the continuous conduction mode (CCM) of the line input current with a current ripple of twice the switching frequency, which allows a significant reduction of size and weight of the filtering elements and increases efficiency. In fact, if the coupled inductors Lin where ideal, with no leakage inductance, no input filter would be necessary. However, unlike previous studied topologies [12]-[14], this converter does not operate properly if inductors Lin are decoupled. In this paper, the switches of the converter are driven complementarily with a duty cycle of 50%. Therefore, variable switching frequency is used to regulate the output voltage. The topology output characteristic makes it necessary to increase the switching frequency with the reduction of load. However, it is more sensitive to frequency variations than those presented in [12], [14] and an increase of 30% on the switching frequency results in 50% reduction of the output power. In addition, the transformer magnetizing inductance is designed so that the converter achieves ZVS even when no current is drained from the transformer secondary windings. The price is an increase of the reactive power, increasing conduction losses. But this resulted in a flatter efficiency curve with close to 90% efficiency for a wide load range. Even though traditional PWM can be used to control the converter, it is not studied in this paper because the operation stages become dependent of the duty-cycle. However, it is not studied here for the sake of brevity. Unlike many S2PFC topologies it is not possible to divide the converter into a PFC stage and a dc-dc converter to study them, separately, which makes the analysis and design a challenging task.
A. Principle of Operation Interval 1 – (t0, t1): Before t0, lower switch S2 was conducting the current through Lin2. At t0, S2 is turned off. Cs1 then starts to discharge and Cs2 charges. Thus, the voltage across the upper switch S1 decreases and across the lower switch S2 increases. At t1, voltage VS1 is zero and VS2 is equal to the “dc-link” voltage VCB.
Fig. 2 – First operation interval.
Interval 2 – (t1, t2): When voltage VS1 reaches zero at t1, the body diode of switch S1 is directly biased, charging the “dc-link” capacitor CB through Lr and Lm. During this interval, switch S1 is commanded to turn on under zero voltage. The voltage across the transformer, Vab, is imposed by capacitor Cin, VCin.
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Lin1
D1
D2
Cin
Cf1
S1 Lr
Vin Cf2
CS1
Lm
I0` Lin2
D3
DS1
CB DS2
CS2
S2
D4
Fig. 7 – Sixth operation interval.
Fig. 3 – Second operation interval.
Interval 3 – (t2, t3): At t2, current through Lr inverts and S1 is turned on, taking on the increasing current. Capacitor Cin continues to discharge until t3, when the voltage across it reaches VCB/2.
Interval 7 – (t6, t7): At t6, S1 is blocked under zero voltage. The current through inductor Lin1 is divided between capacitor Cin, CB and CS1. CS2 discharges and CS1 charges.
Fig. 8 – Seventh operation interval.
Fig. 4 – Third operation interval.
Interval 4 – (t3, t4): At t3, diode D1 is directly biased, initiating the current transition of the coupled inductors Lin1 and Lin2. Current through Lin1 increases while current through Lin2 decreases. The current rate is function of the coupled inductors leakage inductance. If the leakage inductance is zero, this transition is instantaneous.
Interval 8 – (t7, t8): At t7, when voltage across lower switch S2, VS2, reaches zero, the body diode of S2 is turned on. During this interval, switch S2 is commanded to turn on. Voltage Vab is equal to VCin - VB.
Fig. 9 – Eighth operation interval.
Fig. 5 – Fourth operation interval.
Interval 5 – (t4, t5): At t4, the voltage across Cin is clamped in VB/2. Current through Lr divides equally between the coupled inductors Lin1 and Lin2, making the currents through D1 and D4 to increase and decrease, respectively, according to the charge of capacitor CB. At t5, current through CB reaches zero, naturally blocking D4.
Interval 9 – (t8, t9): At t8, current through Lr inverts and S2 takes on the increasing discharge current of CB. This operation interval ends at t8 when the voltage across Cin reaches VB/2. Lin1
D1
D2
Cf1
Cin
S1 Lr
Vin Cf2
D3
CS1
Lm
I0` Lin2
DS1
CB
DS2
CS2
S2
D4
Fig. 10 – Ninth operation interval.
Interval 10 – (t9, t10): At t9, diode D4 is directly biased, turning on, initiating the current transition of the coupled inductors Lin1 and Lin2. This interval is similar to interval 4. Fig. 6 – Fifth operation interval.
Interval 6 – (t5, t6): At t5, capacitor Cin discharges over the transformer. Since the voltage over Cf1 is constant, the voltage over Lin1 varies according to voltage VCin (resonance). This operation interval ends at t6, when switch S1 is turned off. Fig. 11 – Tenth operation interval.
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Interval 11 – (t10, t11): Voltage across Cin is clamped in VB/2. Currents through D4 and D1 increase and decrease, respectively, according to the charge of capacitor CB. At t11, current through CB inverts, naturally blocking D1.
Fig. 12 – Eleventh operation interval.
Interval 12 – (t11, t12): Capacitor Cin continues to charge. Since the voltage over Cf2 and CB are constant, the voltage over Lin2 varies according to voltage VCin (resonance). This interval ends at t10, when S2 is turned off.
B. Design Equations In order to derive the design equations the coupled inductors and the transformer leakage inductances are neglected. The dead time between the switches control signals is also negligible. Therefore, the first, second, fourth, seventh, eighth and tenth intervals occur instantaneously, reducing the operation stages to six, as presented in [11]. However, differently from [11] the current through the inverter is not sinusoidal, but a combination of the output current referred to the primary of the transformer (I’0) and its magnetizing current (iLm), which can be approximated as the sum of a square wave with a triangular wave with null mean value. The key components in this topology are: the capacitor Cin, the magnetizing inductance of the transformer and the load current referred to the primary of the transformer. This component values along with the switching frequency determine the output power and the dc link voltage. Applying Kirchhoff’s Law of current to the equivalent circuit of the third interval gives: (2) iCin (t ) iLin 2 (t ) I `0 (t ) iLm (t ) 0 Currents through Cin and Lm are given by (3) and (4), respectively.
iCin (t ) Cin
Fig. 13 – Twelfth operation interval.
dvCin (t ) dt
(3)
t
The main waveforms of the converter operation over one switching period are shown in Fig. 14.
iLm (t )
1 vLm (t ) dt iLm (0) Lm ³0
(4)
From eq. (1) and since no current is flowing through Lin1, current through Lin2 can be considered constant and equal to the input current multiplied by two. Neglecting Lr, voltage over Lm can be approximated as vCin. Thus: t dv (t ) 1 3 Cin Cin I Lin 2 I ´0 vCin (t ) dt iLm (t2 ) 0 (5) dt Lm t³2 Solving (5), gives: (6) vCin ( t ) k1 cos Z0 t k2 sen Z0 t
Where:
k1
vCin (t2 )
k2
Z0
1 Lm Cin
(I´0 ILin2 ) iLm (t2 ) Cin Z0
(7)
(8)
Equation (9) defines the Į parameter, where 0 < Į < 1 and represents the rate of the charge-pump natural frequency over the switching frequency: It has direct influence on the dc link voltage. The higher Į is, the higher is the dc link voltage. However, an analytical equation to express VCB was not obtained. Reference [16] shows that for the boost converter working in DCM, the ratio VCB/Vin, has influence over the PF. The same happens to the studied topology and since the dc-link voltage depends on Į, the PF also depends on it.
D
Fig. 14 – Theoretical waveforms at line peak voltage.
Z0 Zs
1 2S f s Lm Cin
(9)
An optimization study to define the magnetizing inductance Lm was not developed. But simulation results has shown that an Į close to 0.7 guarantees ZVS with VCB close to 400V and low input current THD.
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Capacitance Cin is obtained by isolating it in (6) and defining values for (t3-t2), VCB, VCin max, I’0 and ILm(t2). Simulation results have shown that (t3-t2) must be around 10% of the switching period (Ts). By observing vCin waveforms in Fig.14, VCin (t2 ) VCin max and the following equation can be written:
VCB V VCin min CB 2 2
VCin max
VCB VCin min
(10)
Where VCB is always higher than the mains peak voltage.
Cin
sin(t3 Z0 ) (iLm (t2 ) I Lin 2 I ´0 ) Z0 (vCin (t3 ) vCin (t2 ) cos(t3 Z0 ))
vLin 2 (t )
Lin 2
diLin 2 (t ) dt
Cf
(11)
During the fourth interval, voltage over capacitor Cin is clamped and equal to VCB/2. Writing Kirchhoff’s voltage law for the external branch gives: (12) vi (t ) vLin1 vLin 2 VCB 0 Since, vLin1 (t )
variations of this parameters have low influence over the converter operation. The proper design of this components is a compromise between cost (low values) and performance (higher values). They also influence the converter dynamic response, but this topic is not covered here. Equations (24) and (25) provide rough guidelines the values for these parameters as functions of Lm and Cin. (24) Lin Lm
0
diLin 2 (t ) VCB 0 dt iLin 2 ( t ) t Vi VCB ³ diLin 2 (t ) 2 Lin 2 t³ dt iLin 2 ( t4 ) 4
vi (t ) 2 Lin 2
iLin 2 (t )
(t 5 t 4 )
Vi VCB (t t4 ) iLin 2 (t4 ) 2 Lin1
2 Lin 2 (iLin 2 (t4 ) iLin 2 (t5 )) Vi VCB
In order to validate the presented study, simulation and experimental results for the converter shown in Fig. 1 are presented. The specifications for the converter are shown in Table I and the converter component values obtained for the given specification are presented in Table II. TABLE I – Prototype Specifications.
(13)
Parameter Line Input Voltage - Vi Output Voltage - V0 Output Rated Power – P0 Switching frequency – fs Maximum Switching Freq. Standard
(14)
(15)
(16)
t
I Lin1
Cin
dvCin (t ) 1 I ´0 vLm (t ) dt iLm (0) (20) dt Lm ³0
Solving (20) leads to:
vCin (t )
k1 cos Z0 t k2 sen Z0 t
(21)
Where:
k1
vCin (t5 )
k2
I Lin1 I ´0 iLm (t5 ) Cin Z0
Parameter Lin1, Lin2 Cf1, Cf2 T1 Lm Lr CB Cin L0 C0
(18)
Supposing current through Lin1 is constant during this interval and substituting (3) and (4) in (19), gives:
Value 220 Vef r 10% / 60 Hz 24 Vdc r 10 % 200 W 30 kHz 75 kHz IEC 61000-3-2 Class D
TABLE II – Component Values
(17)
Equation (18) gives the duration in which capacitor Cin voltage is clamped. Writing Kirchhoff’s Law of current to equivalent circuit of the sixth interval gives: (19) iLin1 iCin I `0 iLm
(25)
IV. SIMULATION AND EXPERIMENTAL RESULTS
Substituting (13) in (12), gives:
vi (t ) 2 vLin 2 VCB
10 Cin
Component Value 500 PH, 2% leakage 1 PF n = 6.2 500 PH 12 PH 1 PF 100 nF 50 PH 9900 PF
Fig. 15 shows simulation results for the dc-link maximum voltage vs. the switching frequency for different values of capacitances Cin. Fig. 16 presents the mains current THD vs. the switching frequency for different capacitances of Cin as well. Small values of Cin results in high dc-link voltage, but lower input current THD at lower power (higher frequency). Increasing the capacitance of Cin, decreases the dc-link voltage, but the input current THD increases more with the reduction of load.
(22)
The voltage across the primary of the transformer (Vab) over half the switching period can be approximated by the voltage on capacitor Cin. Thus, t t6 t4 · 1 §3 Vab ¨ ³ vCin (t ) dt ³ vCin (t ) dt ³ vCin (t ) dt ¸ (23) ¸ T ¨t t3 t5 ¹ 2 ©0 The capacitances of Cf1 and Cf2 and the inductance of Lin1 and Lin2 must be set to guarantee that they work as good voltage and current sources, respectively. Small
Fig. 15– Maximum dc-link voltage VS switching frequency for different values of Cin.
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Fig. 21 and Fig 22 show the same results for the converter operating with an output load of 30 W (15%). Even with a THD of 65%, input current would comply with IEC 61000-3-2 Class D if it where applicable at such low power.
Fig. 16– Line input current THD VS switching frequency for different values of Cin.
Fig. 17 presents the output power vs. the switching frequency for different capacitances Cin. By changing Cin, the circuit natural frequency (Ȧ0) is also changed, therefore, Į is also altered, which results in a displacement of the operation point for the same switching frequency. However, for small values of Cin, in this case lower than 47 nF, the behavior of the circuit becomes different in the lower frequencies because Cin does not have enough energy to supply the load and the operation stages become different from the described ones.
Fig. 18 – Simulation results: (a) Dc-link voltage, (b) Capacitor Cin voltage.
Fig. 19 – Line input voltage (100 V/div) and current (1 A/div) at 12MS/s for P0 = 200 W: (a) Without input filter, (b) With input filter.
Fig. 17 – Output Power VS switching frequency for different values of Cin.
Fig. 18 shows simulation results for (a) the dc-link voltage and (b) the capacitor Cin voltage at the rated power over the period of the mains. The presented design equations are valid for the time interval when voltage Cin does not reach zero. During the short interval, when voltage across Cin reaches zero, no energy is been transferred to the transformer secondary, so the output capacitance is responsible for supplying the load current during these intervals. This is also responsible for the current distortion close to the zero crossing of the mains. If a bulky CB were used, voltage vab would be high enough to transfer energy to the secondary. However, this circuit operation mode is slightly different and the design equations presented in this paper are not valid. There is an intermediate value that can be used but the input current becomes more distorted and a displacement between the mains voltage and current occurs naturally. Fig. 19 presents experimental results for (a) the line input voltage and current without, and; (b) with additional input filter. As can be seen, power factor correction is achieved in both situations. Fig. 20, shows the line input power quality analysis. The power factor is 98.9% and THD is 15%. Simulation results for the line input current at full load with a leakage inductance of 2% for the coupled inductors and no additional input filter confirmed the current ripple of Fig 19 (a).
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Fig. 20 - Harmonic content of input current with IEC 61000-3-2 Class D limits and power quality results at the rated power.
Fig. 21 – Line input voltage (100 V/div) and current (200 mA/div) at 12MS/s for P0 = 30W with input filter.
main characteristics of the presented converter are high power factor, high efficiency, high power density, small number of components and low cost. The main advantages over most single-stage solutions are reduced dc-link voltage, no need for a bulky electrolytic dc-link capacitor and CCM input current. Although, higher output capacitance is necessary, low voltage capacitors cost less than high voltage ones. However, low output voltage applications; lower than 12 V, with small ripple, less than 2%, may require a bulky dc-link capacitor. Fig. 22 - Harmonic content of input current with IEC 61000-3-2 Class D limits and power quality results at P0 = 30 W.
REFERENCES
The oscillation of the input current close to the zero crossing in Fig. 19 and Fig. 21 are due to the low damping factor of the used input filter, which can be reduced by adjusting it. The power factor and efficiency trend curves as functions of the output power are depicted in Fig. 23. High power factor is achieved and even with the PF deterioration when power is reduced, it complies with the IEC 61000-3-2 Class D standard, even below 50 W. However, the PF could be improved by altering Cin, for example. As showed in Fig. 15 and Fig. 16 there is a trade off between the dc-link maximum voltage and the input current THD. The obtained efficiency is high over the tested range, from 15% to full load. Fig. 24 shows switch S1 current at the rated power. It can be seen that soft switching is achieved at the line peak and close to the zero crossing of the line input voltage. The power MOSFETs used in the prototype and the output Schottky diodes were FCP11N60F and MBR20200CT, respectively.
[1]
[2]
[3]
[4]
[5]
[6] [7]
[8]
[9]
[10]
[11]
[12]
Fig. 23 - Efficiency and power factor trend curves vs. output power.
5A
[13]
400 V
[14]
[15] Fig. 24 – Switch S1 voltage and current - (a) Close to the line peak voltage, (b) Close to line voltage zero crossing.
[16]
V. CONCLUSIONS A single-stage SMPS with PFC has been presented. As in [13], the presented converter is suitable for low power applications, where two-stage approach is costly. The
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