Single-Switch Power Factor Correction ACDC Converter with Storage Capacitor Size Reduction A. Lhzaro, A. Barrado, J. Pleite, R. Vkquez, J. Vhzquez, E. Olias. Universidad Carlos I11 de Madrid Departamento de Tecnologia Electronica Grupo de Sistemas Electr6nicos de Potencia Avda. Universidad, 30; 2891 1, LeganCs, Madrid, SPAIN Tel.: +34-91-6249428; FAX: +34-91-6249430 E-mail:
[email protected] Abstract - In universal line applications with hold-up time requirement, the single-stage PFC ACIDC converters may not be more attractive than the conventional two-stages approach if the size and cost of the storage capacitor are too high. Furthermore, computer related applications, in which the holdup time is a very important requirement, will have to comply with Class D limits of the low frequency harmonic regulation IEC 61000-3-2. Therefore, for these applications, a not very distorted line current will be required. In this paper, a new single-stage ACBC converter suitable for universal line applications is proposed. The main difference with other solutions is the low voltage swing on the storage capacitor while the line varies within its universal range. This feature allows reducing the size and cost of the storage capacitor. Additional advantages of the proposed converter are topology simplicity (single-switch converter) and IEC 61000-3-2 Class D compliance. The experimental results confirms the above mentioned advantages.
1) European range - Class A compliance. The new version of the IEC 61000-3-2 regulation has broadened the application of Class A limits to the most product, therefore single-stage approach [6-121 has widened the zone in which this solution is competitive. Even passive PFC solutions have result in a very interesting solution around the 100 W output power[13-141. The two- stage approach [15] will be used when the power level does not allow distortion in the line current. P s h PFC
I. INTRODUCTION
The low frequency harmonic regulation IEC/EN 61000-3-2 [I] has adopt a new direction [2], now electronic equipment are classified according to use. Most of electronic equipment will be classified into Class A. Into this Class very distorted currents are allowed for low power applications because the limits are absolute. Therefore if the size and cost can be reduced andor the efficiency is improved it does not matter what happen with the line current. In this new scope, several circuits are now obsolete and some others could change its application field. Some very interesting comparisons between two-stage and single-stage approach can be found in [3-51, however, the new version of the IEC 61000-3-2 regulation modifies this scope. In Fig. 1 a possible new distribution of the PFC AC/DC converters as a function of the output power, is shown. In this figure, the different solutions have been classified by means of the input-voltage range (European or Universal) and the limits which the power supply have to comply depending on the use of the corresponding final equipment. Four combinations (voltage range - class to comply with) can be distinguished, they can be described as follows:
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Fig. 1 : New approximate distribution of PFC ACDC converters as a function of the output power and the harmonic regulations and line-voltage range requirement.
2) European range - Class D compliance. The valid zone for single-stage solutions is not so wide due to restrictive Class D limits, on the other hand the size of the passive solution is not so competitive as in the previous case. 3) Universal range - Class A compliance. For this equipment, some single-stage solutions which good efficiency and competitive part list in spite of a very distorted input current should be very useful. When hold-up time is required, the size and cost of the storage-capacitor limit the application of these solutions due to high voltage swing on the storage capacitor. 4) Universal range - Class D compliance. These are a very restrictive requirements. For very low power applications single-stage solutions still could be used. If the output power range increases, some single-stage converters with voltage range selector [16] could be an attractive solution. In this paper a new single-stage AC/DC converter is presented. If the zones 0 and 0, shown in Fig. 1 are
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considered, the proposed converter could be interesting mainly because Class D limits are complied and the size and cost of the storage capacitor is contained. 11. PROWSED CONVERTER
The proposed converter belongs to a new family of AC/DC PFC converters presented in [17]. The power stage of the proposed converter is shown in Fig. 2.a). The main differential characteristic of this converter is that the storage capacitor absorbs and provides energy each switching cycle. For those line angles in which the instantaneous line voltage is high, the storage capacitor, mainly absorbs energy and when the line voltage is near zero volts, Cl mainly provides the energy to feed the output. The power balance is produced each half line-cycle. The resulting average storage-capacitor voltage can be designed to be lower or higher than output voltage. Due to the presence of an additional branch (Tz, Dss, DS2) the load can be feed at any moment, even when the instantaneousinput-line-voltageis zero. a)
front-end, a single-stage converter with a voltage on storage capacitor clamped to the peak value of line voltage. (This case does not corresponds to a concrete topology, but several solutions obtain similar results, e.g. [6], [7]). And finally the proposed converter. In Fig 3.a, it can be seen, how the best results corresponds to the two-stages approach due to the fixed storage capacitor voltage. Between the two single-stage solutions analyzed, the proposed converter present a lower volume for the storage capacitor for the three different output voltages considered. This result is due to the reduced voltage achieved swing on Cl. a) Universal range
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b) European range
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Fig. 2:a) Power stage of the SII-Fl converter.b) Theoretical duty cycle and line current.
The voltage on storage capacitor and its size and cost will be discussed in the next paragraph. The additional main features can be described as follows: 1) Versatility in IEC 61000-3-2 compliance. The converter meets IEC 6 1000-3-2 Class A limits with a margin wide enough. If Class D compliance is required, this converter can also be designed for this aim. In Fig. 2.b) it can be seen a typical line-current (theoretical waveform). 2) Advantageous part list and component count. The proposed converter is a single-switch topology which is controlled by means of a single voltage-mode control loop based on a low cost IC controller. 111. VOLTAGE ON THE STORAGE CAPACITOR AND STORAGE-CAPACITORSIZE
In Fig. 3 it is shown the storage-capacitor sizes for three different ACJDC converters: a two stage approach with boost
Fig. 3: Storage capacitor size comparison in three AC/DC converters. Operation with a) Universal range of input voltage. b) European range of input voltage.
In Fig. 3.b is presented a similar table for European line voltage. In this case, the three ACIDC converters presents similar results are obtained because the line voltage variation is quite low within the European range. The light differences are due to the capacitor exploitation. It is important to notice than the same results have been obtained when the storagecapacitor voltage is around the 400 V and when this voltage is around 30, 60, 80 V (proposed converter). This is due to the fact that for a higher storage voltage, a lower value of capacitance is required to store the same energy, however the capacitors with a higher rated voltage present a higher size. A detailed description can be found in [ 181. The proposed converter can be designed in order to fix the minimum and maximum voltage on the storage capacitor
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which are produces due to the line voltage variation. This aspect allows a better exploitation of the capacitors and it will be treated in the design guidelines section. The voltage swing on the storage-capacitor voltage is quite lower than the range in which the universal line voltage varies. Finally, the low voltage on storage capacitor does not contribute to additional voltage stress on the other devices of the converter. Iv. SWITCHING PROCESS
The converter has two operation modes depending on the instantaneous magnitude of the input-line voltage as it is illustrated in Fig. 4.a. The principal switching mode is Mode 2, therefore its corresponding switching process will be described in more detail.
Fig. 4: a) . Switching modes along l i e cycle. b) Mode 2 switching frequency theoretical waveforms. Equivalent circuit of each stage of the switching cycle.
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A . Mode 2 switchingprocess. The main switching frequency waveforms together with the equivalent circuit of each stage are represented in Fig. 4.b. The switching process can be summarized as follows: 1) Stage I: SI is On. Lzl is magnetized with the voltage on storage capacitor and L I l is magnetized with the input voltage. The duration of this stage normalized with the switching period is d. 2) Stage 2: L22 resets through DS2 and L12 via DSI. Therefore, each switching cycle, single processing energy flows through DSI and double processing energy flows through DS2, the average currents through DS1 and DS2 can be seen en Fig. 5. The normalized duration of this stage is d,.
A MathCAD@-developed calculus program allows describing the effect of each dimensionless design parameter on the performance of the converter. This information can be seen in Fig. 5 and Fig. 6 and it is also explained in the design process section.
B. Single processing ratio & input current In Fig. 5 it can be seen the input current waveform for designs with a different single processing ratio, Kp. In the proposed converters, if the processing ratio is maintained constant, the same input current waveform is obtained. Therefore, it is possible to find a Kp value which define the boundary between the compliance with Class A and Class D
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limits. In Fig. 5, it can be seen how the value of Kp=0.78 present a ninth harmonic (this is always the more restrictive harmonic in this type of current waveform) touching it corresponding Class D limit. Thus, for a Kp value higher than 0.78, Class A limits will be complained, on the contrary if Kp
