(SiP) Modules for Wireless Multiradio - IEEE Xplore Digital Library

System-in-Package (SiP) Modules for Wireless Multiradio Nigel Martin and Helena Pohjonen Nokia Technology Platforms PL 86, FI-24101 Salo, Finland Email: [email protected], [email protected] Abstract Mobile devices: phones, terminals, PDAs etc. will include an increasing number of methods of cellular access, such as: GSM, WCDMA, CDMA etc. and complementary cellular wireless access such as: WLAN, BT, Positioning, Receiving and Broadcasting capability. This paper analyzes how System in Package (SiP) can be utilized in Multiradio wireless access mobile devices, and what characteristics are needed in such SiPs to provide future mobile devices with wireless access. Guidelines and directions are presented to aid in the design and partitioning of SiPs. The embeddation of IC(s) die inside a SiP module interposer, the reduced need for the traditional type of shielding of the total system, and the option to include passive components with high performance requirements as SMD parts inside SiPs are options to achieve a 50% area and thickness reduction. A minimal number of implementation technologies and materials, I/Os and part count reduction by about 50 % may also result. Introduction There are several forms of hardware integration methods that allow miniaturization of the electronics; monolithic, system and hybrid integration, which today can be called System in Package (SiP). SiP in a broad sense uses all forms of electronic parts such as: integrated circuits (ICs), discrete semiconductor devices, surface mountable discrete and special devices. SiP can also use various interconnection techniques such as flip chip, wire bonding and chip stacking, and several part assembly and substrate techniques. Used in an effective way, SiPs represent one way for modularized electronics to be manufactured quickly, with the best possible size and performance balance [1]. Monolithic integration is a key miniaturization method with the main technology used in mobile devices being silicon. However, some cellular and non-cellular specifications are relatively demanding concerning isolation, linearity, filtering and output power requirements etc. Additionally, the energy source, the battery, sets certain limits relating to time and temperature, on the selected architectures and circuit solutions. All requirements cannot be satisfied with one integration media, such as silicon system on chip (SoC) – others include GaAs, SMD devices with specific requirements, specific filters and duplexers. The RF, analog and mixed-signal functionalities in mobile products require both active and passive devices. Monolithic integration takes care most of the active devices, however the required passive devices cannot be totally integrated with current state-of-the-art passive integration technology either due to their values, or their performance requirements. However, the tendency should be towards the use of a minimum number of technologies and materials leading to

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maximum reliability in the near future in portable electronics. Future environmental requirements will also benefit from a minimal use of different, but clearly controlled and traceable, materials. Balanced use of SiP and SoC enables minimum part count For efficient architecture partitioning, SiP and SoC can be considered as equivalent parallel approaches, even though design flow(s) for SiP is/are far from mature and currently do not include options for SiP/SoC partitioning trade-offs, design for reliability including thermal and EMC, testability, size and cost. Fig. 1 shows an analysis of the part count of several multimode wireless product electronics products that include WCDMA and GSM functionality. 120 100 80

Number of ICs

60

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40

Number of parts/20

20 0 A B C D E F G H I

J K

Best balance = smallest part count

Figure 1. Number of electronic parts (y axis) in different multimode wireless products (A, B, …, and K) based on the data available from reference [2]. The balanced maximal use of SoC and SiP in system integration offers the smallest total electronics part count. However, this requires good timing with both miniaturization techniques. Essentially, SiP can be seen as the medium term link to the reality of SoC. Since the current reality is that SoC is not ready for the full integration of wireless multi-access, SiP allows the implementation of wireless multi-access in the most compact and lowest cost form for products shipping in the medium term. However, the balanced use of SiP and SoC requires support from EDA design flows and tools to become a real efficient method for decreasing system level turn around time, Figs. 2 and 3. The reality of having SiPs used on a motherboard design is the lower level of sophistication needed for the actual motherboard e.g. lower line/space requirements. If the I/O pitches of the SiPs are chosen well, the motherboard specification requirements can be relaxed, thus reducing the cost, in addition to the turnaround times.

1347 2006 Electronic Components and Technology Conference

Current EDA does not support feedback and system level iteration

Basic SiP options SiPs use less power and perform better than separately packaged chips on a motherboard, since all connection paths are shorter, requiring less power from the on-chip drivers. However, there are many possible ways to construct the SiP, depending on the key drivers involved in the specific architecture and design:

SoC All possible combinations in implementations: all leading to different number of parts, form factors, size and timeto-market

SiP

System architecture

• Maximized SoC Integration at selected technologies, stacked • Maximized SoC Integration at selected technology + passives as SMD • Maximized SoC Integration + passive integration + other passives as SMD • Maximized SoC Integration + passive integration & Embeddation in SiP interposer + other passives as SMD

SMD

Figure 2. SoC, SiP and SMD are on equal place in system partitioning but currently iteration cannot be made effectively due to incomplete electronic design automation (EDA) tools.

SoC3 turn time: SoC3 turnaround around tim8e:… 816 …weeks 16 weeks S oC2 turn around time: SoC2 turn around tim8e:…816 …weeks 16 weeks

Figure 4. The SiP is formed with wire bonded stacked die inside the package. SMDs may surround the SiP on the motherboard, if necessary. Die stacking shown in Fig. 4 is a relatively mature packaging technique. Interconnection such as wire bonding or flip chip techniques can also be used.

SoCturn around time: SoC around time: 8 …16 weeks 8turn …16 weeks

SoC1 turnaround around tim8e:… 816 …weeks 16 weeks SoC1 turn time:

SMDDs s SM

Ready and/or Std ICs standard ICs

Time advantage: 6 …13 weeks

block(s)m made ICIC IPIPblocks ade compatible (like adding com SiPs redispatible tributionwith etc) for SiP

Time –to-market Delta: 5 …13 weeks turnaround around SSiP iPturn Time: 3…6 weeks time: 3 …6 weeks

2…3 weeks

Integrated pas sives Integrated passives: asseparate chips, 8 weeks or4 on… separate substrate 4…8 weeks

Time Figure 3. Relative turnaround times of SoC vs. SiP. Effective use of SiP(s) leads to multiplication of the time advantages and time-to-market deltas.

Figure 5. A passive integration die on top of the active die. Large value passives are not available either as cost effective, or small enough with most of passive integration technologies, therefore these remain as four SMD capacitors shown in this SiP Generally SiPs should be able to include most of the parts and technologies needed also in wireless systems, Fig. 6, additionally they should be compatible with other SiPs and system integration technologies like system motherboards.


4%

8%

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2%

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12% 68%

Capacitors Resistors Coil Ferrites for RF chokes Crystals RF filters Other modules Figure 6. Typical distribution of the number of non-IC components needed in mobile RF. SiP should be a viable implementation route, parallel to SoC and the use of IP blocks for any system architecture. This requires that the SiP be thought off holistically from the start, in that ideally no part of the SiP should be designed without consideration for the various other parts of the SiP. SiPs have been designed using a combination of PWB software and in-house tools. However, we see that the optimum environment is one where the IC design tool is extended to encompass the substrate and other associated die interconnects, system testability including thermal issues with modeling, reliability, yield on SiP and SoC level, cost and several environmental aspects. Following on from the EDA flow ideal, the SoC design environment would interface directly, as a sub-set of the SiP design task, nominally using the same EDA tool suite. Thus, the situation may arise where more than one SiP design may call for the inclusion of any particular SoC design. The SOC design will be in the central library to be “called up” by whichever SiP design requires it. SiP designs must be compatible with generally agreed Open Interfaces standards, i.e. standards such as Mipi (www.mipi.org) and DiGRF (www.digrf.org) or similar should be followed. In SiPs this will be a 3D task, as opposed to the PWB world where 2.5D is typically sufficient. The 3D aspect includes: Thermal, Electromagnetic and Test access. The absence of, or difficulty in achieving, an ideal power plane can cause real challenges in designs where multiple voltages are present. The modeling of the power delivery structure, and subsequently being able to monitor in the time and frequency domain presents real challenges for the EDA tools.

Using SiPs The use of SiPs in product development and manufacturing will ease the burden on individual product programs, since the entire SiP will have been fully tested and developed as a separate task. In this respect, the SiP will be off-the-shelf component for product programs, with minimal adaptation and limitations for various product concepts. The normal die-level test suite will be supplemented by individual die suppliers, with the provision of test vectors to the SiP level integrator, to enable final test. The individual die test (KGD), whether IC or PI, responsibility resides at the chipmaker, whether the SiP is made in their facilities or elsewhere. Typically, KGD requires distinct process steps such as: • Semi-finished product typology • Process description • Parametric testing • SPC, EWS & Burn-In • Visual inspection • Certificate of conformance • Yield Marking • Identification, Marking, Labeling & Trace-ability • Packing • Process change Notification • Qualification • Failure analysis • Warranty / responsibility The testing of the SiP must be fully completed and compliant before delivery to the system level manufacturer. The composite SiP yield should be considered in all design phases, including the internal interconnection, so that the total SiP cost is minimized. SiPs must be compatible with the system level manufacturing process, and compatible with module level processes such as the key component review. Daisy Chain testing, at Level 3, must be made on all SiPs to be used in system level products before ramp-up authorization is achieved. For ensuring thermal aspects separate thermal test SiPs including thermal test dies dissipating typical and maximum power of the product can be manufactured and tested in worst case product usage environment. Materials used in modules are normally the same as in electrical components in general. To name some, epoxy resin or BT resin (Bismaleimide Triazole) with additives ensuring required properties and functionality are used in module interposers. In addition, epoxy resin can be used in module molding for the hermetical sealing function. Interconnections are normally formed by carefully adjusted metallurgy which forms a reliable solder joint between the module and motherboard, as well as between separate parts and the interposer inside the module. As in other electrical parts, materials used for modules need to fulfill environmental requirements. These requirements can be dictated by national or international laws or voluntary agreements specified by industrial associations or companies. Current legislation in Europe requires the


electronics industry to prepare itself for the phasing out of some restricted substances. These substances are named in so called RoHS directive (Restriction of certain Hazardous Substances in electrical and electronic equipment; 2002/95/EC). The directive defines that mercury, lead, cadmium, hexavalent chromium; two types of brominated flame-retardants (PBB and PBDE) must be phased out by 1.7.2006. In addition to the European Union’s definition of two types of brominated flame-retardants, some national laws or law proposals (e.g. State of Maine/US - LD1790 - Sec.1.38 MRSA c. 16-D or State of New Jersey/US - AB3057) are asking companies to monitor or report the use of brominated flame-retardants or bromine and chlorine in general. Shielding and Thermal issues Shielding in mobile terminals has traditionally been effected with the use of supra shielding metal cans, thus encasing the components in a Faraday cage, soldered to the substrate. Supra shielding is a relatively low risk technique, since with sufficient design iterations it is usually possible to tailor the shielding to fit the RF needs of the design. However, the substrate area needed to accommodate the attachment of the shield to the substrate, along with the headroom needed from the top of the components to the supra shield, represents a significant loss in available volume. The time required for the various design iterations using supra shielding can be crippling for the timely introduction of a product. In addition, this solution sets certain limitations for products’ mechanical design and manufacturing process. Various other shielding techniques have emerged, e.g. side plating of modules, to address this issue, however most involve additional steps in the SiP manufacturing process. We envisage a SiP shielding implementation where the shielding is inherent in the substrate, perhaps using the Copper layers of the substrate to form the Faraday cage around the die. Edge plating, through-vias and microvias may all be utilized in the construction of the z-dimension of the cage. It may be needed to create more than one shield within a SiP e.g. where a transceiver VCO needs to be shielded from another part of the transceiver, e.g. PA o/p stage. In all these shielding scenarios, the “star” principle for RF grounding should be adhered to, thus ensuring the minimization or absence of Eddy currents. The ever-decreasing size of mobile terminals, combined with the increasing need for processing power, leads to an increasing energy density within mobile terminals. Thus, techniques must be developed and utilized in SiP designs to facilitate the improved thermal paths, preferably copper, needed to guide the energy away from the heat generating parts of the assembly.

x

X

X

X

x

X x

X X

x

X

X

x X

Figure 7. Typical multimode (WCDMA and GSM) engine showing shielding borders with spacings and dies (marked with x) occupy about half of the system area [2]. Dissipated power 4

W

3.5 3

GSM single slot PA GSM dual slot PA

2.5 HSDPA WCDMA PA 2

WCDMA PA

1.5 1

Typical area for dissipated power

0.5 0 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 Efficiency of the PA

Figure 8. Dissipated power of cellular power amplifiers (PA) vs. their efficiency covering GSM, WCDMA and high-speed data packet access (HSDPA) [3]. A power amplifier (PA) typically consumes 20 …30 % of the power of a cellular product leading to 2 to 3 W worst-case maximum power dissipation in a cellular product. Additionally, the increasing number of applications means the addition of more base band and applications processors and therefore added dissipated power. For portable products, there are several local and national legal requirements concerning maximum allowable surface temperature (discomfort limits) of the product used in touch with a human skin. These requirements, the manufacturer of the product must fulfill, totally independently of what applications or implementation


technologies – SiP, SoC or something else - included in the product are. This is the primary guiding topic, in addition to minimization of the power dissipation. Thermal vias in the substrate to either the top or bottom of the die, or both, will be needed to ensure sufficiently low thermal resistance paths. Other, low cost heat transfer media will be needed in the near future. Thermal modeling of SiPs will be required in cases where there is significant heat generation. This will be done in conjunction with the system level thermal management modeling process.

• Embedding elements such as ferrites and acoustic wave filters will require careful assessment of the size/cost benefit Testing, environmental and known good die related issues with time to market and cost are the most urgent challenges to be overcome. T Acknowledgments The authors would like to thank Arja Mehtala (Nokia Technology Platforms) for her support concerning the environmental aspects of this work. References 1. Tummala, R.R., “SOP: What is IT and Why? A New Microsystem-Integration Technology Paraigm – Moore’s Law for System Integration of Miniaturized Convergent Systems of Next decade,” IEEE Transactions on Advanced Packaging, Vol. 27, No. 2 (2004), pp. 241-249. 2. End of the Beginning, Progress in technology, Design, and Manufacturing Cost in 3G UMTS Handsets, Portelligent (www.teardown.com), 36 p., 2004. 3. V. Loukusa, H. Pohjonen, A. Ruha, T. Ruotsalainen, O. Varkki, Systems on Chip Design: System Manufacturer Point of View, Proceedings of the Design Automation and Test Conf, Paris, 2004, 2p.

Oscillator modules Multidie memory stacks since 1997 Power amplifier modules since 1998 Front end + PA modules since 2001 Multidie stacks in RF, baseband and energy management SiP radio modules IP Block re-use Increasing Thermal Challenge Increased Functionality Decreasing materials, manufacturing steps and cost 2004

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Figure 9. Mobile SiPs and Requirements towards the future. Conclusions System in Package is a viable technology for increasing modularity in wireless systems, speeding up time to market as connected in parallel with monolithic integration, getting the best out of the various active SoC integration, passive integration, SMD technologies, interconnections, and packaging approaches available leading to a minimum number of I/Os and materials in system implementation and therefore improved reliability and increased yield. The most potential directions in future SiPs developments are: • Embedding dies inside SiP interposer/substrate for thinner and smaller area for achieving 50 % area and thickness reduction • Reducing routing density and complexity on system board level • Reduced traditional shielding of the total system • Enhanced thermal capability without using any additional material or parts • From high I/O count parts to lower I/O count parts, when the functionality of SiPs is increasing • Minimum number of parts in wireless electronics target being 50% part count reduction every third year • Minimum total system cost
