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voltage is obtained from a three-phase 380-V ac utility voltage with a diode rectifier. The normal dc input voltage Vin = 480−600 V. If a full-bridge dc/dc converter ...
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 6, JUNE 2013

Soft-Switching Converter With Two Series Half-Bridge Legs to Reduce Voltage Stress of Active Switches Bor-Ren Lin, Senior Member, IEEE, and Chia-Hung Chao

Abstract—This paper presents a new soft-switching dc/dc converter for high-input-voltage applications. Two half-bridge converters connected in series with interleaved asymmetric pulsewidth modulation (PWM) are adopted to limit the voltage stress of each power switch at one-half of the input dc bus voltage. In each half-bridge converter, two asymmetrical dc/dc circuits with the same active switches are connected in parallel at the output side to share the load current and reduce the current stresses of the secondary windings and rectifier diodes. Since two half-bridge converters are operated with interleaved PWM, the output ripple currents partially cancel each other so that the resultant ripple current at the output side is reduced. Active switches in the proposed circuit can be turned on at zero-voltage switching during the transition interval due to the resonant behavior by the output capacitance of MOSFETs and the leakage inductance of transformers. Experiments based on a laboratory prototype with 960-W rated power are provided to demonstrate the performance of the proposed converter. Index Terms—Power converters, power electronics.

I. I NTRODUCTION

P

OWER FACTOR CORRECTION (PFC) techniques have been proposed to improve power quality including reactive power reduction and harmonic elimination. Thus, line current is in phase with line voltage with near-unity power factor. For the single-phase line voltage in South Africa or India, the maximum line voltage may be greater than 350 V. The dc bus voltage with boost-type PFC may be equal to 500 V. For three-phase 380-V (or 480-V) ac/dc converters, the dc bus voltage may be higher than 800 V. Thus, power MOSFETs with 600-V voltage stress cannot be used in second-stage dc/dc converters. Threelevel dc/dc converters [1]–[10] can overcome these problems with more power switches, split capacitors, and clamp diodes such that the voltage stress of power switches can be reduced to one-half of the dc bus voltage. However, the complicated control scheme and high circuit cost are the main drawbacks of multilevel dc/dc converters. High circuit efficiency and high power density are also demanded for modern switching-mode

Manuscript received November 29, 2011; revised February 23, 2012; accepted March 3, 2012. Date of publication March 22, 2012; date of current version February 6, 2013. This work was supported by the National Science Council of Taiwan under Grant NSC 101-2221-E-224-MY2. The authors are with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou 64002, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2012.2191758

power supplies. Actively clamped converters [11]–[13] have been proposed to achieve zero-voltage-switching (ZVS) turn-on for all switches with an auxiliary switch and one clamp capacitor. Thus, the magnetic flux can be reset, and the voltage stress of a power switch can be limited. Active clamp techniques can reduce switching losses, but they cannot effectively improve or reduce the voltage stress of active switches. Full-bridge phaseshift converters [14], [15] can also achieve soft switching for all power switches. However, it is difficult for the MOSFETs in the lagging leg to realize ZVS turn-on at wide load ranges. Asymmetrical half-bridge converters [16]–[18] have the advantages of ZVS turn-on and low voltage stress on power switches. For medium- or high-power applications, interleaved pulsewidth modulation (PWM) [19]–[21] with phase shifting of several circuit cells connected in parallel can reduce the current stresses of power switches and reduce the ripple current on input and output capacitors. This paper presents an interleaved soft-switching converter for high-input-dc-voltage applications. Two capacitors and two half-bridge converters are connected in series to limit the voltage stress of active switches at one-half of the dc bus voltage. Two half-bridge converters are operated with interleaved PWM to reduce the output ripple current and share the load current. For each half-bridge converter, there are two circuit cells with the same active switches connected in parallel at the output side to further reduce the current stress of transformer windings and the size of magnetic cores. Based on the resonant behavior at the transition interval, power switches can be turned on at ZVS. Finally, experiments based on a 960-W prototype are presented to verify the effectiveness of the proposed converter. II. C IRCUIT C ONFIGURATION Fig. 1 shows the circuit configuration of the proposed dc/dc converter for high-input-voltage applications. The input dc voltage is obtained from a three-phase 380-V ac utility voltage with a diode rectifier. The normal dc input voltage Vin = 480−600 V. If a full-bridge dc/dc converter is used in the second stage to obtain low output voltage, a low-frequency insulated-gate bipolar transistor can be used as the power switches to regulate output voltage. However, the converter size with low switching frequency cannot be reduced. To further reduce the converter size with high switching frequency and MOSFET devices, two half-bridge converters were used in the proposed circuit to achieve load current sharing and reduce ripple current at the output capacitor with interleaved

0278-0046/$31.00 © 2012 IEEE

LIN AND CHAO: SOFT-SWITCHING CONVERTER WITH TWO SERIES HALF-BRIDGE LEGS

Fig. 1.

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Proposed new interleaved ZVS half-bridge converter.

PWM operation. The PWM signals of the two half-bridge converters (circuits 1 and 2) are phase shifted by one-half of the switching period. Thus, the ripple currents of the output inductors partially cancel each other, and the size of the output inductors is decreased. Each circuit includes two asymmetric half-bridge converter cells with the same half-bridge leg to increase the load current. The components of circuit 1 include Q1 , Q2 , Cc1 , Cc2 , Lr1 , Lr2 , T1 , T2 , D1 −D4 , Lo1 , Lo2 , and Co . The components of circuit 2 include Q3 , Q4 , Cc3 , Cc4 , Lr3 , Lr4 , T3 , T4 , D5 −D8 , Lo3 , Lo4 , and Co . Vin1 and Vin2 are the input voltages (Vin1 = Vin2 = Vin /2). Cc1 −Cc4 are the dc blocking capacitances. Lr1 −Lr4 are the resonant inductances. Lm1 −Lm4 are the magnetizing inductances of transformers T1 −T4 , respectively. D1 −D8 are the rectifier diodes, and Lo1 −Lo4 are the output filter inductances. C1 −C4 are the output capacitances of MOSFETs Q1 −Q4 , respectively. The first converter cell in circuit 1 includes Q1 , Q2 , Cc1 , Lr1 , T1 , D1 , D2 , and Lo1 . Q2 is the main active switch and Q1 is the auxiliary switch in the first converter cell. The second converter cell in circuit 1 includes Q1 , Q2 , Cc2 , Lr2 , T2 , D3 , D4 , and Lo2 . Q1 is the main active switch and Q2 is the auxiliary switch in the second converter cell. Therefore, Q1 is operated as the main switch for converter cell 2 and as the auxiliary switch for converter cell 1. Switch Q2 is operated as the main switch for converter cell 1 and as the auxiliary switch for converter cell 2. The voltage stress of Q1 and Q2 equals Vin /2. In the same manner, the voltage stress of Q3 and Q4 is clamped to Vin /2. Since the PWM signals of the two half-bridge converters are generated using an asymmetric PWM scheme, active switches can be easily turned on at ZVS during the transition interval. III. O PERATION P RINCIPLE Before the discussion of the proposed converter, the following assumptions are made to simplify the system analysis. 1) Four transformers T1 −T4 are assumed to be identical, having the same magnetizing inductances Lm1 = Lm2 = Lm3 = Lm4 = Lm and the same turns ratios n = np /ns1 = np /ns2 .

Fig. 2. Key waveforms of the proposed converter.

2) Active switches Q1 −Q4 are ideal and have the same output capacitances C1 = C2 = C3 = C4 = Cr . 3) We assume that Cc1 = Cc2 = Cc3 = Cc4 = Cc , Lr1 = Lr2 = Lr3 = Lr4 = Lr , and Lo1 = Lo2 = Lo3 = Lo4 = Lo . 4) Lr  Lm , and Cr  Cc . 5) The energy stored in the resonant inductor Lr is greater than the energy stored in the resonant capacitor Cr such that the ZVS turn-on of all switches can be achieved. Based on the ON/OFF states of Q1 −Q4 and D1 −D8 , the proposed converter has 16 operation modes in one switching period. The key waveforms of the proposed converter over one switching period are shown in Fig. 2. An asymmetric PWM scheme is adopted to control active switches Q1 −Q4 . In each half-bridge leg, two switches (Q1 and Q2 ) and (Q3 and Q4 ) are complementary with a short dead time. However, the gate signals of Q1 and Q3 are phase shifted by one-half of a switching cycle. Since the PWM waveforms of the two halfbridge converters are symmetrical, only eight operation modes during the first half of a switching period are discussed and shown in Fig. 3. Before time t0 , switches Q1 and Q4 are in the ON state, and rectifier diodes D1 −D5 and D8 are conducting. Mode 1 [t0 ≤ t < t1 ]: At time t0 , diode currents iD1 and iD4 decrease to zero. In circuit 1, semiconductors Q1 , D2 , and

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Fig. 3. Operation modes of the proposed converter during the first half of a switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8.

LIN AND CHAO: SOFT-SWITCHING CONVERTER WITH TWO SERIES HALF-BRIDGE LEGS

D3 are conducting in this mode. The primary voltages vT 1,p ≈ −vCc1 < 0 and vT 2,p ≈ Vin /2 − vCc2 > 0. Thus, magnetizing current iLm1 decreases with the current slope of −vCc1 /Lm , and iLm2 increases with the current slope of (Vin /2 − vCc2 )/Lm . The secondary-side voltages of T1 and T2 are negative and positive, respectively. Thus, diodes D2 and D3 are forward biased and conducting. Since the inductor voltages vLo1 = (vCc1 /n − Vo ) > 0 and vLo2 = ((Vin /2 − vCc2 )/n − Vo ) > 0, inductor currents iLo1 and iLo2 increase in this mode. In circuit 1, power is transferred from input voltage source Vin1 to the output load through Q1 , T2 , Lr2 , Cc2 , D3 , and Lo2 in this mode. On the other hand, the energy stored in capacitor Cc1 is also transferred to the output load through Q1 , T1 , Lr1 , D2 , and Lo1 in this mode. In the same manner, Q4 , D5 , and D8 are conducting in circuit 2. The primary voltages vT 3,p ≈ Vin /2 − vCc3 > 0 and vT 4,p ≈ −vCc4 < 0. Thus, magnetizing current iLm3 increases, and iLm4 decreases. The secondarywinding voltages of T3 and T4 are positive and negative, respectively. Thus, diodes D5 and D8 are forward biased and conducting. Since the inductor voltages vLo3 = ((Vin /2 − vCc3 )/n − Vo ) > 0 and vLo4 = (vCc4 /n − Vo ) > 0, inductor currents iLo3 and iLo4 increase in this mode. In circuit 2, power is transferred from input voltage source Vin2 to the output load through Cc3 , Lr3 , T3 , Q4 , D5 , and Lo3 in this mode, and the energy stored in capacitor Cc4 is transferred to the output load through Q4 , T4 , Lr4 , D8 , and Lo4 in this mode. This mode ends at time t1 when switch Q1 is turned off. Mode 2 [t1 ≤ t < t2 ]: At time t1 , switch Q1 is turned off. C1 and C2 are charged and discharged, respectively. Since C1 and C2  Cc1 and Cc2 , capacitor voltages vC1 and vC2 are approximately given as iLr2 (t1 ) − iLr1 (t1 ) (t − t1 ) 2Cr iLr2 (t1 ) − iLr1 (t1 ) vC2 (t) ≈ Vin /2 − (t − t1 ). 2Cr vC1 (t) ≈

(1)

Primary currents iLr1 and iLr2 are almost constant in this mode. The operation behavior of circuit 2 in this mode is the same operation behavior in mode 1. This mode ends at time t2 when vC1 = VCc1 and vC2 = VCc2 . Then, the primary voltages of T1 and T2 are zero, and the secondary-winding voltages of T1 and T2 are also zero. Mode 3 [t2 ≤ t < t3 ]: This mode starts at time t2 when vC1 = VCc1 and vC2 = VCc2 . At this instant, the primaryand secondary-winding voltages of T1 and T2 are all zero. Thus, diodes D1 −D4 are all conducting to commutate inductor currents iLo1 and iLo2 . During this mode, inductor voltages vLo1 = vLo2 = −Vo such that output inductor currents iLo1 and iLo2 decrease. Diode currents iD1 and iD4 increase, and iD2 and iD3 decrease. Capacitors C1 and C2 are continuously charged and discharged, respectively, in this mode iLr2 (t2 ) − iLr1 (t2 ) (t − t2 ) 2Cr iLr2 (t2 ) − iLr1 (t2 ) vC2 (t) ≈ vCc2 − (t − t2 ). 2Cr

vC1 (t) ≈ vCc1 +

(2)

The operation behavior of circuit 2 in this mode is the same operation behavior in mode 1. If the energy stored in inductors

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Lr1 and Lr2 is greater than the energy stored in capacitors C1 and C2 , then C2 can be discharged to zero voltage. This mode ends at time t3 when vC2 = 0. At this instant, the antiparallel diode of Q2 is conducting. The time interval between modes 2 and 3 can be approximately expressed as Δt13 = t3 − t1 ≈

Cr Vin . iLr2 (t1 ) − iLr1 (t1 )

(3)

In order to achieve ZVS turn-on for switch Q2 , the dead time td between active switches Q1 and Q2 must be greater than the time interval Δt13 . Mode 4 [t3 ≤ t < t4 ]: At time t3 , vC2 = 0. Since iQ2 = iLr1 − iLr2 < 0, the antiparallel diode of Q2 is forward biased and conducting. Before switch current iQ2 is positive, Q2 must be turned on to achieve ZVS. Diodes D1 −D4 are still in the commutation interval. The inductor voltages vLr1 = Vin /2 − VCc1 and vLr2 = −VCc2 . Inductor current iLr1 increases and iLr2 decreases in this mode ΔiLr1 Vin /2 − vCc1 = Δt Lr

vCc2 ΔiLr2 =− . Δt Lr

(4)

This mode ends at time t4 when diode currents iD2 and iD3 are decreased to zero. If the load current Io is equally distributed into four output inductors, then inductor current variation ΔiLr1 in this mode is approximately equal to Io /(2n). Thus, the time interval in this mode is approximately given as Δt34 = t4 − t3 ≈

Lr Io Lr Io = . 2n(Vin /2 − vCc1 ) 2nvCc2

(5)

During this mode, switch Q2 is in the ON state, and the secondary side of circuit 1 is in the commutation interval. Thus, the secondary-winding voltages of T1 and T2 are zero. The output inductor voltages vLo1 = vLo2 = −Vo . The duty loss due to resonant inductances Lr1 and Lr2 in this mode can be expressed as δloss,4 =

Δt34 Lr Io fs ≈ Ts 2nvCc2

(6)

where Ts is the switching period and fs is the switching frequency. Mode 5 [t4 ≤ t < t5 ]: At time t4 , diode currents iD2 = iD3 = 0. Thus, diodes D2 and D3 are turned off. In this mode, active switches Q2 and Q4 are conducting in the primary side. The transformer primary voltages vT 1,p ≈ Vin /2 − vCc1 , vT 2,p ≈ −vCc2 , vT 3,p ≈ Vin /2 − vCc3 , and vT 4,p ≈ −vCc4 . Thus, diodes D1 , D4 , D5 , and D8 are conducting in the secondary side. Inductor currents iLr1 and iLr3 increase and iLr2 and iLr4 decrease in this mode. The output inductor voltages vLo1 = (Vin /2 − vCc1 )/n − Vo , vLo2 = vCc2 /n − Vo , vLo3 = (Vin /2 − vCc3 )/n − Vo , and vLo4 = vCc4 /n − Vo . In circuit 1, power is transferred from input voltage source Vin1 to the output load through Lr1 , Cc1 , T1 , Q2 , D1 , and Lo1 in this mode. In circuit 2, power is delivered from input voltage Vin2 to the output load through Lr3 , Cc3 , T3 , Q4 , D5 , and Lo3 . This mode ends at time t5 when switch Q4 in circuit 2 is turned off. Mode 6 [t5 ≤ t < t6 ]: At time t5 , Q4 is turned off. Since iLr3 (t5 ) − iLr4 (t5 ) > 0, C3 and C4 are discharged and

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 6, JUNE 2013

charged, respectively. Voltages vC3 and vC4 can be approximately expressed as iLr3 (t5 ) − iLr4 (t5 ) Vin − (t − t5 ) 2 2Cr iLr3 (t5 ) − iLr4 (t5 ) vC4 (t) ≈ (t − t5 ). 2Cr

output inductor voltages vLo1 = vLo2 = −Vo . Thus, the duty loss due to inductances Lr3 and Lr4 can be expressed as

vC3 (t) ≈

δloss,8 = (7)

Inductor currents iLr3 and iLr4 are almost constant in this mode. The operation behavior of circuit 1 in this mode is the same operation behavior in mode 5. This mode ends at time t6 when vC3 = vCc3 and vC4 = vCc4 . Then, the primary-winding voltages of T3 and T4 are equal to zero. Mode 7 [t6 ≤ t < t7 ]: At time t6 , vC3 = vCc3 , and vC4 = vCc4 . At this instant, the primary- and secondary-winding voltages of T3 and T4 are all equal to zero. Thus, diodes D5 −D8 are conducting to commutate inductor currents iLo3 and iLo4 . Diode currents iD6 and iD7 increase, and iD5 and iD8 decrease. The output inductor voltages vLo3 = vLo4 = −Vo . Therefore, output inductor currents iLo3 and iLo4 decrease. Capacitors C3 and C4 are continuously discharged and charged in this mode, respectively iLr3 (t6 ) − iLr4 (t6 ) (t − t6 ) 2Cr iLr3 (t6 ) − iLr4 (t6 ) vC4 (t) ≈ vCc4 + (t − t6 ). 2Cr

vC3 (t) ≈ vCc3 −

(8)

Δt57

(9)

In order to achieve ZVS turn-on of Q3 , the dead time td between active switches Q3 and Q4 must be greater than the time interval Δt57 . Mode 8 [t7 ≤ t < t8 ]: At time t7 , capacitor voltage vC3 = 0. Since iQ3 = iLr4 − iLr3 < 0, the antiparallel diode of Q3 is conducting. Before iQ3 is positive, Q3 must be turned on to achieve ZVS. Diodes D5 −D8 are still in the commutation interval. The primary- and secondary-winding voltages of T3 and T4 are all zero. Thus, the inductor voltages vLr3 = −vCc3 and vLr4 = Vin /2 − vCc4 . Inductor current iLr3 decreases and iLr4 increases in this mode vCc3 ΔiLr3 =− Δt Lr

Vin /2 − vCc4 ΔiLr4 = . Δt Lr

(10)

This mode ends at time t8 when diode currents iD5 and iD8 decrease to zero. The time interval in this mode is approximately given as Δt78 = t8 − t7 ≈

Lr Io . (2nvCc3 )

(11)

During this mode, switch Q3 is in the ON state, and the secondary side of circuit 2 is in the commutation interval. The

(12)

Then, the operating modes of the proposed converter in the first half of a switching period are completed. The PWM waveforms of modes 9–16 in circuit 1 are symmetrical to the PWM waveforms of modes 1–8 in circuit 2. In the same manner, the PWM waveforms of modes 9–16 in circuit 2 are symmetrical to the PWM waveforms of modes 1–8 in circuit 1. IV. C IRCUIT C HARACTERISTICS In the system analysis, the transition intervals at turn-on and turn-off instants, such as between modes 2 and 3 and modes 6 and 7, are much shorter than the turn-on time of active switches. Thus, we can neglect the transition intervals when designing the circuit characteristics. The duty cycles of Q1 and Q3 are δ. The duty cycles of Q2 and Q4 are (1 − δ). From the volt–second balance on the primary windings of T1 −T4 at steady state, the average capacitor voltages VCc1 −VCc4 are obtained as VCc1 = VCc3 = (1−δ)Vin /2

If the energy stored in inductors Lr3 and Lr4 is greater than the energy stored in capacitors C3 and C4 , then C3 can be discharged to zero voltage. This mode ends at time t7 when vC3 = 0. At this instant, the antiparallel diode of Q3 is conducting. The time interval between modes 6 and 7 can be expressed as Cr Vin . = t7 − t 5 ≈ iLr3 (t5 ) − iLr4 (t5 )

Δt78 Lr Io fs . ≈ Ts (2nvCc3 )

VCc2 = VCc4 =

δVin . 2

(13)

The dc voltage conversion ratio of the proposed converter can be obtained from the volt–second balance on the output inductors Lo1 −Lo4 at steady state 2δ(1 − δ) − δloss,16 (1 − δ) − δloss,4 δ Vo + Vf = Vin 2n

(14)

where Vf is the voltage drop on diodes D1 −D8 and δloss,4 and δloss,16 are the duty losses in modes 4 and 16, respectively. The duty losses in modes 4, 12, 8, and 16 can be obtained from (6) and (12) Lr Io fs Lr Io fs = 2nvCc2 nδVin Lr Io fs Lr Io fs = = . 2nVCc3 n(1 − δ)Vin

δloss,4 = δloss,12 = δloss,8 = δloss,16

(15)

From (14) and (15), the output voltage of the proposed converter is expressed as   Vin Lr Io fs (16) − Vf . Vo = δ(1 − δ) − n nVin It is clear that the output voltage is related to the duty cycle δ, input voltage Vin , switching frequency fs , inductance Lr , and load current Io . The average magnetizing currents of Lm1 −Lm4 can be obtained by the current–second balance on dc blocking capacitances Cc1 and Cc2 ILm1 = ILm3 =

(2δ−1)Io 4n

ILm2 = ILm4 =

(1−2δ)Io . (17) 4n

The ripple currents on inductances Lm1 −Lm4 can be expressed as ΔiLm =

VCc1 (δ−δloss,16 )Ts δ(1−δ)Vin Ts − Lr Io /n = . (18) Lm 2Lm

LIN AND CHAO: SOFT-SWITCHING CONVERTER WITH TWO SERIES HALF-BRIDGE LEGS

Thus, the maximum and minimum magnetizing currents of Lm1 −Lm4 are given as (2δ−1)Io δ(1−δ)Vin Ts −Lr Io /n + 4n 4Lm (1−2δ)Io δ(1−δ)Vin Ts −Lr Io /n + = iLm4,max = 4n 4Lm (2δ−1)Io δ(1−δ)Vin Ts −Lr Io /n − = iLm3,min = 4n 4Lm (1−2δ)Io δ(1−δ)Vin Ts −Lr Io /n − = iLm4,min = . 4n 4Lm (19)

The root-mean-square (rms) values of switching currents iQ1,rms −iQ4,rms can be expressed as (24), shown at the bottom of the page. The voltage stresses of Q1 −Q4 are given as

iLm1,max = iLm3,max = iLm2,max iLm1,min iLm2,min

The output inductances of Lo1 −Lo4 can be obtained as Lo = Lo1 = Lo2 = Lo3 = Lo4 [VCc1 /n − Vo − Vf ](δ − δloss,16 )Ts = ΔiLo    (1−δ)(1−2δ)Vin Lr Io fs Lr Io fs δ − + 2 2n n nVin (1−δ) Ts = . ΔiLo1

(20)

Thus, the maximum and minimum output inductor currents are given as iLo1,max = iLo2,max  = iLo3,max = iLo4,max  (1 − δ)(1 − 2δ)Vin Lr Io fs Io + + = 2 4 4n  2n Ts Lr Io fs × δ− nVin (1 − δ) Lo iLo1,min = iLo2,min  = iLo3,min = iLo4,min  (1 − δ)(1 − 2δ)Vin Lr Io fs Io − + = 2 4 4n  2n Ts Lr Io fs × δ− . (21) nVin (1 − δ) Lo The average currents on rectifier diodes D1 −D8 are expressed as DIo 4 ≈ (1 − D)Io /4.

ID2 = ID3 = ID6 = ID7 ≈ ID1 = ID4 = ID5 = ID8

(22)

The voltage stresses of rectifier diodes D1 −D8 are given as VD1,stress = VD4,stress = VD5,stress = VD8,stress (1 − δ)Vin 2VCc1 Lm ≈ = n(Lm + Lr ) n VD2,stress = VD3,stress = VD6,stress = VD7,stress δVin 2(Vin − VCc1 )Lm ≈ . = n(Lm + Lr ) n

(23)

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VQ1,stress = VQ2,stress = VQ3,stress = VQ4,stress =

Vin . 2

(25)

At time t1 in mode 2, inductor currents iLr1 and iLr2 are approximately given as iLo1,max n δ(1 − δ)Vin Ts − Lr Io /n (2δ − 1)Io Io − ≈ − 4n 4L 4n m   (1 − δ)(1 − 2δ)Vin Lr Io fs + − 2 3  4n 2n Ts Lr Io fs × δ− nVin (1 − δ) Lo iLo2,max iLr2 (t1 ) = iLr4 (t9 ) ≈ iLm2,max + n δ(1 − δ)Vin Ts − Lr Io /n (1 − 2δ)Io Io + ≈ + 4Lm 4n   4n (1 − δ)(1 − 2δ)Vin Lr Io fs + + 2 3  4n 2n Ts Lr Io fs × δ− . (26) nVin (1 − δ) Lo iLr1 (t1 ) = iLr3 (t9 ) ≈ iLm1,min −

At time t5 in mode 6, inductor currents iLr3 and iLr4 are approximately given as iLo3,max 2n δ(1 − δ)Vin Ts − Lr Io /n (2δ − 1)Io Io + ≈ + 4Lm 4n   4n (1 − δ)(1 − 2δ)Vin Lr Io fs + + 2 3  4n 2n Ts Lr Io fs × δ− nVin (1 − δ) Lo iLo4,max iLr4 (t5 ) = iLr2 (t13 ) ≈ iLm4,min − n δ(1 − δ)Vin Ts − Lr Io /n (1 − 2δ)Io Io − ≈ − 4n 4L 4n m   (1 − δ)(1 − 2δ)Vin Lr Io fs + − 2 3  4n 2n Lr Io fs Ts × δ− . (27) nVin (1 − δ) Lo iLr3 (t5 ) = iLr1 (t13 ) ≈ iLm3,max +

If the energy stored in inductors Lr1 and Lr2 is greater than the energy stored in capacitors C1 and C2 in mode 2, then capacitor

iQ1,rms = i

Q3,rms   2 2   2  Io (1−2δ)Io Io Lr Io fs Io (2δ−1)Io Lr Io fs Lr Io fs + + − ≈ 2 δ− δ− + 4n 3nVin (1−δ) 4n 4n nVin (1−δ) 4n 4n nVin (1−δ) iQ2,rms = i

Q4,rms   2  2 2 Io Io Io (2δ − 1)Io (1 − 2δ)Io δloss,4 + + − ≈ 2 (1 − δ − δloss,4 ) + (1 − δ − δloss,4 ) (24) 4n 3 4n 4n 4n 4n

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C2 can be discharged to zero voltage. Thus, the ZVS condition of Q2 can be given as Lr ≥

Cr Vin2 2 2 [iLr1 (t1 ) + i2Lr2 (t1 )]

(28)

where C1 = C2 = C3 = C4 = Cr . If the energy stored in inductors Lr3 and Lr4 is greater than the energy stored in capacitors C3 and C4 in mode 6, then capacitor C3 can be discharged to zero voltage. Thus, the ZVS condition of Q3 can be given as Lr ≥

Cr Vin2 2 [i2Lr3 (t5 ) + i2Lr4 (t5 )]

.

(29)

In the same manner, the ZVS conditions of Q1 and Q4 are given respectively as Cr Vin2 Lr ≥ 2 2 [iLr1 (t13 )+i2Lr2 (t13 )]

Cr Vin2 Lr ≥ . 2 2 [iLr3 (t9 )+i2Lr4 (t9 )] (30)

From (28)–(30), the ZVS condition of Q1 −Q4 can be expressed as Cr Vin2 Cr Vin2 , Lr ≥ max . (31) 2 [i2Lr1 (t1)+i2Lr2 (t1)] 2 [i2Lr3 (t5)+i2Lr4 (t5)] We assumed that the voltage ripples of dc blocking capacitors Cc1 and Cc2 are less than the α percentages of their average voltages ΔvCc1 = ΔvCc3

1 = Cc1

δT

  Io 1 − ILm1 δTs iLr1 dt ≈ Cc1 4n

0

=

(1 − δ)δIo Ts α(1 − δ)Vin < αVCc1 = 2nCc1 2

ΔvCc2 = ΔvCc4 =

1 Cc2



δT iLr2 dt ≈



Io 1 + ILm1 δTs Cc2 4n

0 2

=

δ Io Ts αδVin . < αVCc2 = 2nCc2 2

(32)

Thus, the dc blocking capacitance Cc = Cc1 = Cc2 = Cc3 = Cc4 is given as δIo . (33) Cc > (αnVin f )

frequency of the proposed converter is fs = 100 kHz. The assumed circuit efficiency at rated power is 90%. We assume that the maximum duty cycles of switches Q1 and Q3 are 0.41 at minimum input voltage and full-load condition. At duty cycle δ = 0.5, we assume that the maximum duty cycle loss in modes 4 and 16 is less than 15% δloss,T = δloss,4 +δloss,16 ≈

4Lr Io fs 16Po Lr fs ≈ < 0.15. (34) nVin ηVin2

From (34), the inductances of Lr1 −Lr4 are expressed as Lr1 = Lr2 = Lr3 = Lr4 = Lr


δmax Io = 0.44 μF. αnVin,min fs

(46)

The selected capacitances of Cc1 −Cc4 are 0.44 μF. The capacitance of output capacitor Co is 3600 μF. VI. E XPERIMENTAL R ESULTS Experimental results with the circuit parameters derived from the previous section are provided to verify the effectiveness and performance of the proposed converter. The input voltage range is from 480 to 600 V with a nominal dc bus voltage Vin ≈ 540 V. The PWM IC TL494 is used to generate two gate signals vQ1,gs and vQ3,gs . The gate drive IC L6384 is adopted to generate four gate signals vQ1,gs −vQ4,gs with a dead time. A type-II voltage controller with k-factor is adopted to regulate the output voltage. Fig. 4 shows a picture of the experimental prototype. Fig. 5 shows the measured gate voltages of Q1 −Q4 at full load and different input voltage conditions. Gate voltages vQ3,gs and vQ4,gs lag vQ1,gs and vQ2,gs by one-half of a

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Fig. 6. Measured waveforms of the gate voltage, drain voltage, and switch current of Q1 at nominal input voltage and at (a) 50% load and (b) 100% load.

Fig. 5. Experimental waveforms of the gate voltages of Q1 −Q4 at full load with (a) Vin = 480 V, (b) Vin = 540 V, and (c) Vin = 600 V.

switching period, respectively. Figs. 6 and 7 show the gate voltage, drain voltage, and drain current of switches Q1 and Q2 at 50%- and 100%-load conditions with nominal input voltage Vin = 540 V. We can observe that active switches Q1 and Q2 are turned on at ZVS. Similarly, switches Q3 and Q4 are also turned on at ZVS. Fig. 8 shows the measured waveforms of gate voltages vQ2,gs and vQ4,gs and inductor currents iLr1 −iLr4 at full load and nominal input voltage. The inductor currents iLr1 = −iLr2 and iLr3 = −iLr4 , and vQ4,gs , iLr3 , and iLr4 are phase shifted half of a switching period with respect to vQ2,gs , iLr1 , and iLr2 . Fig. 9 shows the measured waveforms of gate voltages vQ2,gs and vQ4,gs and the dc blocking capacitor voltages vCc1 −vCc4 at full-load condition. Fig. 10 shows the measured waveforms of gate voltages vQ2,gs and vQ4,gs and the secondary diode currents iD1 −iD8 at full-load condition.

Fig. 7. Measured waveforms of the gate voltage, drain voltage, and switch current of Q2 at nominal input voltage and at (a) 50% load and (b) 100% load.

LIN AND CHAO: SOFT-SWITCHING CONVERTER WITH TWO SERIES HALF-BRIDGE LEGS

Fig. 8. Measured waveforms of gate voltages vQ2,gs and vQ4,gs and inductor currents iLr1 −iLr4 at full load and nominal input voltage.

Fig. 9. Measured waveforms of gate voltages vQ2,gs and vQ4,gs and the dc blocking capacitor voltages vCc1 −vCc4 at full-load condition.

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Fig. 11. Measured waveforms of the output inductor currents iLo1 −iLo4 and the circuit 1 and 2 output currents iLo1 + iLo2 and iLo3 + iLo4 at full-load condition.

Fig. 12. Measured efficiencies of the proposed converter for different input voltages and load conditions.

Fig. 11 shows the measured waveforms of the output inductor currents iLo1 −iLo4 and the circuit 1 and 2 output currents iLo1 + iLo2 and iLo3 + iLo4 at full-load condition. Fig. 12 shows the measured efficiencies of the proposed converter at different load conditions. VII. C ONCLUSION

Fig. 10. Measured waveforms of gate voltages vQ2,gs and vQ4,gs and the secondary diode currents iD1 −iD8 at full-load condition.

A new interleaved half-bridge converter, which achieves ZVS turn-on for all active switches with a wide range of input voltages and load conditions, has been presented in this paper. Two split capacitors and two half-bridge converter circuits connected in series were adopted to clamp the voltage stress of each active switch at Vin /2. Two half-bridge converter circuits were operated with an interleaved PWM scheme such that the output ripple currents can partially cancel each other. In each half-bridge converter circuit, two asymmetrical PWM cells with the same active switches were connected in parallel to share the load current, reduce the current stress of the transformer windings, and achieve ZVS turn-on for all switches. Finally, experiments with a 960-W prototype have been provided to verify the effectiveness of the proposed circuit.

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Bor-Ren Lin (S’91–M’93–SM’02) received the B.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988 and the M.S. and Ph.D. degrees in electrical engineering from the University of Missouri, Columbia, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronics Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics. He has authored more than 300 published technical conference and journal papers in the area of power electronics. His main research interests include power factor correction, multilevel converters, active power filters, and soft-switching converters. Dr. Lin is an Associate Editor of the IEEE T RANSACTIONS ON I NDUS TRIAL E LECTRONICS . He was the recipient of the Research Excellence Awards in 2004, 2005, 2007, and 2011 from the Engineering College and the National Yunlin University of Science and Technology. He was also the recipient of the Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the 2007 Taiwan Power Electronics Conference, and the 2009 IEEE Power Electronics and Drive Systems Conference.

Chia-Hung Chao is currently working toward the M.S. degree in electrical engineering from the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan. His research interests include the design and analysis of power factor correction techniques, switching-mode power supplies, and soft-switching converters.