Abstract-- In this paper, a novel single-stage isolated AC-. DC converter is proposed for single-phase high power PFC applications. The circuit is derived by ...
9th International Conference on Power Electronics-ECCE Asia June 1 - 5, 2015 / 63 Convention Center, Seoul, Korea
Soft-Switching Single Stage Isolated AC-DC Converter for Single-Phase High Power PFC Applications Chushan Li1, Yu Zhang2, and David Xu1 1
2
Department of Electrical and Computer Engineering, Ryerson University, Canada School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, China
Abstract-- In this paper, a novel single-stage isolated ACDC converter is proposed for single-phase high power PFC applications. The circuit is derived by combining the boost converter and the matrix-based isolated AC-DC converter. Compare to traditional PFC plus DC/DC configuration, this topology has no diode front end and the number of semiconductors in the current path is minimized. Thus the conduction loss is decreased. By adding a small clamping capacitor and two small size commutation inductors, softswitching for all switches can be realized. Thus the system efficiency can be significantly improved. Furthermore, traditional PWM technology can be applied. Problems of resonant based soft-switching converters including large EMI filter size, high devices voltage and current stress, and low light load efficiency can be avoided. In this paper, the topology derivation and circuit operational analysis are given. The control strategy is introduced and a simulation is carried out to verify the circuit. Index Terms—AC-DC, PFC, Single stage, Soft-switching.
I. INTRODUCTION Power factor correction (PFC) is a widely-used technology to save the electric energy and minimize the interference of power electronics converters to the grid. In most of the utility interfaced applications, such as electrical vehicles chargers and communication centers, galvanic isolation is also required [1]. As a result, a twostage system configuration, which consists of a front-end circuit stage with PFC function followed by an isolated DC-DC stage, is commonly employed [2-3]. Usually, the frond-end stage is composed by a diode rectifier bridge followed by a boost switch cell. A large DC link capacitor is required between the two stages [4]. However, this two-stage solution suffers from low total efficiency. Since PFC stage usually cannot achieve soft-switching. At the same time, the soft-switching of the dc-dc stage cannot be guaranteed under light load condition. If resonant based soft-switching converters are applied, large EMI filter will be required. Besides that, large bulk electrolytic type dc link capacitors are required between these two stages, which increase the system volume and lower the reliability. Single stage AC-DC converters with isolation are attractive in researches. Since fewer conversion stages always lead to higher power density. Several types of single stage solutions are developed for PFC applications. Single switch based solutions are popular especially in low power range [5-6]. However, the efficiency of these solutions is pretty low as the energy in leakage
2015 KIPE
inductance is difficult to handle. In higher power range, full bridge type topologies are preferred [4, 7-9]. The significant advantage of these topologies is the elimination of the boost cell in the PFC stage. But the problem of these solutions is that a large volume of DC electrolytic capacitor is still required to form the DC link between the rectifier and the full bridge circuit, which limits the circuit performance. If the capacitance is decreased to be a very small volume [1], the DC link voltage will keep fluctuating with the input AC voltage. The soft-switching process of DC-DC stage will then become complex. Of course, DC capacitor can be replaced by using an inductor to form a current source DC link [10-11]. But during the operation, when the inductor and the leakage inductor of the transformer are connected together during the switching transient, high voltage spike will take place on switches. In order to clamp the over-voltage, complex active clamping circuit or passive snubbers have to be implemented. These also decrease the circuit efficiency. Matrix type topologies are alternative solutions in this area. In order to eliminate the diode rectifier, the AC-side switches are implemented by bidirectional switches. Depending on different AC input source types, these topologies can attribute to current-source input converter [12-13] and voltage source input converter [14-16]. The current-source input converters are still facing voltage clamping problem. Although it can be solved by operating the secondary switches to create soft-switching condition [13], it is impossible to implement for PFC circuit with uncontrolled diode-rectifier secondary. On the other hand, the voltage–source input converters require phase-shifting control to realize soft-switching for all switches. Since the input AC voltage is varying from peak to zero, full-range soft-switching operation cannot always be guaranteed. Thus, in this research area, new topology or soft-switching method remains to be figured out. In this paper, a boost-matrix based single stage isolated PFC converter is proposed. Compare to traditional PFC plus DC/DC configuration, this topology has fewer conduction loss since it has no diode front end and the number of semiconductors in the current path is minimized. The converter can realize soft-switching for all the switches in the whole load range, thus the voltage spike can be clamped and also the efficiency performance is enhanced. Furthermore, the converter applies traditional PWM technology, which facilitates the design
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of EMI filter and increases the light load efficiency. In this paper, the topology derivation and circuit operational analysis are given. The control strategy is introduced. A simulation is carried out to verify the circuit functionality. II. TOPOLOGY DERIVATION AND CIRCUIT OPERATIONAL ANALYSIS A. Topology derivation Lin
vin
S2
S4
S2n
S4n
Do1 Do3 Lk T1 n1
Cr S3
S5
S3n
S5n
Co R
n2 Do2 Do4
(a) Matrix type converter with clamping capacitor Cr
Lin
Lr2 Lr1
vin
S1 S1n
S2
D2 S4
D4
S2n
D2nS4n
D4n
D1 D1n
Cr
S3
D3 S5
D5
S3n
D3nS5n
D5n
Do1 Do3 Lk T1 n1
n2
Co R
Do2 Do4
(b) Proposed boost-matrix type AC-DC converter Fig. 1 Demonstration of derivation process for proposed converter
The proposed topology is derived from matrix-type isolated AC-DC converter with current-fed input [12]. First, a capacitor Cr with tens of nF is added between the mid-points of two bridges in order to clamp the voltage spike taken place when the input inductor Lin and high frequency transformer T1 leakage inductor Lk are connected together. The derived circuit is shown in Fig. 1(a). But this circuit is hard to realize soft-switching since there is no additional commutation path. To solve this problem, a new bi-directional switch S1(S1n) with two commutation inductors Lr1 and Lr2 are added. The final version of the proposed topology is shown in Fig. 1(b). The new circuit can be considered as the combination of an AC boost and a matrix-type isolated AC-DC converter. S1(S1n) is the boost main switch, which conducts during the boost “on” time. All the Matrix circuit S2(S2n)-S5(S5n), Do1-Do4 acts as the “boost diode”. Half of the switches conduct during the “off” time to deliver the energy to the output and achieve high frequency isolation. Dx(Dxn) (x=1..5) denotes the anti-parallel diodes of the active switches. The function of Lr1 and Lr2 are to realize ZCS turn-on and turn-off for all the switches. In the following section, the circuit operational principle and analysis are given to shown the operating principle of soft switching. B. Circuit Operational Analysis All the switches can be attributed into two groups, which are S1-S5 and S1n-S5n. The switching pattern is decided by the direction of the input inductor current iLin.
If iLin is positive according to the directions defined in Fig. 1(b), S1-S5 are active to realize PFC function while S1n-S5n are all kept off during this period. If iLin is negative, S1-S5 are changed to normal off and S1n-S5n are changed to active switching. One switching period can be further divided into two symmetric sub-periods corresponding to plus and minus cycle of T1. One subperiod is divided into six stages. The plus cycle is taken as example to demonstrate the operation. The corresponding equivalent circuits are given in Fig. 2(a)(g), the key waveforms are shown in Fig. 3. During this sub-period, the polarity of iLin is positive, thus S1n-S5n are kept off. Also, assumption has made that the output DC voltage vdc remains almost constant during one switching period. Stage 0 [t0-t1]: The equivalent circuit of this stage is shown in Fig. 2(a). Before stage 1, S2, D2n, S5 and D5n is in ON state, S1, S4 and S3 are in OFF state. Lin, Lr2 and Lk are discharged to the output. The inductor current thus decreases gradually in the same rate. The capacitor voltage vCr is in steady state, which can be given by: n (1) vCr = 1 vdc n2 The voltages on S1, S3 and S4 are equal to vCr. The leakage inductor current iLk is equal to iLin. Stage 1 [t1-t2]: The equivalent circuit of this stage is displayed in Fig. 2(b). At the time t1, S1 is turned on. Cr begins to resonant with Lr1, Lr2 and Lk. The current in Lr1 begins to rise gradually from zero. Thus S1 is ZCS turned on. Also, the current decreasing rate of D2n, D5n, S2 and S5 is limited by Lr2. This implies that they are all in ZCS condition. Assuming that energy in Cr is large enough compared to Lr1 and Lr2, vCr will keep almost constant during this stage. The duration of this stage can be calculated as: ( L + Lr 2 )iLin (2) t2 − t1 ≈ r1 vCr Stage 2 [t2-t3]: At the time t2, current in Lr2 decreases to zero and is reverse blocked by D2n and D5n. S2 and S5 can be turned off in this stage. The voltages on S3, S4, S2n and S5n change to half of vCr. Cr continues to be discharged through Lk. The current in Lk decreases to zero gradually, which means that the Do1 and Do4 are turned off in ZCS. The duration of stage 2 and 1 can approximately calculated by:
t3 − t1 ≈
π
2
Lk Cr
(3)
Stage 3 [t3-t4]: In this stage, as shown in Fig. 2(d), only S1 and D1n are in ON state. Lin and Lr1 are charged by vin. Stage 4 [t4-t5]: At the time t4, S3 and S4 are turned on. Cr begins to resonant with Lr1, Lr2. The current in Lr1 begins to fall gradually to zero and reverse blocked by D1n. Thus S1 and D1n are under ZCS condition. Also, the current increasing rate of S3 and S4 is limited by Lr2. It implies that they are in ZCS condition. Similar with stage 1, the duration of this stage can be calculated as: ( L + Lr 2 )iLin (4) t5 − t 4 ≈ r 1 vCr
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The equivalent circuit is displayed in Fig. 2(e). Stage 5 [t5-t6]: In this stage, current in Lr1 decreases to zero. S1 can be turned off in this stage. Cr continues to be discharged by vin through Lin and Lr2 and vCr goes to negative finally. The equivalent circuit is shown in Fig. 2(f). It can be found that, during this interval, voltages on all the off-state switches are clamped by Cr. vCr and iLin follow the below resonance equations: v +v iLin = I Lin 0 cos [ωr (t − t4 )] + in Cr sin [ωr (t − t4 )] (5) Zr
(c) Stage 2 [t2 t3]
vCr = −vin + (vin + VCr 0 ) cos [ωr (t − t4 ) ] − Z r I Lin 0 sin [ωr (t − t4 )] (6) Where Ȧr and Zr are given by: ωr =
1 ( Lr 2 + Lin )Cr
Zr =
Lr 2 + Lin Cr
(7),
ILin0 is the initial values of iLin, VCr0 is almost equal to vdcxn1/n2. The duration of stage 4 and 5 can be calculated by using (6) where vCr is equal to -vdcxn1/n2. Stage 6 [t6-t7]: The equivalent circuit of this stage is shown in Fig. 2(g). After vCr falls below -vdcxn1/n2, Do2 and Do3 are turned on. Cr Begins to resonant with Lk. The maximum voltage overshoot will be: L (8) Δv = I Lin max k Cr The maximum switch voltage on the primary side will be: L n (9) Vswitch = 1 vdc + I Lin max k n2 Cr According to the analysis, all the switches are actually clamped to Cr during the operation. According to (9), an important design criterion is that to keep the inductance of Lk as small as possible. Carefully designed T1 can limit the inductance so as to limit the over voltage of vCr and maintain the voltages on switches under safety level. It also can make the volume of Cr smaller.
(d) Stage 3 [t3 t4]
Lin
Lr2
iLin vin
Lr1
S1
S2
D2 S4
D4
S2n
D2nS4n
D4n
D1
S1n
Lk T1
Cr
S3
D3 S5
D5
S3n
D3nS5n
D5n
D1n
Do1 Do3
n1
n2
Co R
vdc
Do2 Do4
(e) Stage 4 [t4 t5]
(f) Stage 5 [t5 t6]
(a) Stage 0 [t0 t1] (g) Stage 6 [t6 t7] Fig. 2 Operational process of proposed converter
Following the stage 6, another sub-period begins where S1, S2 and S5 become active. The commutation process will be similar with the first sub-period.
(b) Stage 1 [t1 t2]
C. Soft-switching design criterion The realization of soft-switching for all switches is not critical for the proposed circuit. According to the former analysis, there are three commutation stages in
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one sub-period, which are stage 1, stage 4 and stage 5. Minimum commutation time should be guaranteed. For the stage 1 and 4, according to (2) and (4), the worst case takes place when input current iLin reach its maximum value. Since the inductance of Lr1 and Lr2 is pretty small, these two intervals are very short compared to one switching period. During the gate signal generation, a common “ON” deadtime is inserted, where the duration is given by:
td 1 =
n2 ( Lr1 + Lr 2 )iLin max n1vdc
(10)
For the stage 5, minimum commutation time is set to ensure that vCr will become negative before S1(S1n) is turned on again. According to (6), the worse case takes place during the AC voltage and current crossing zero. The maximum duration of the time is given by:
td 2 =
π
(11)
( Lr 2 + Lin )Cr
2 In order to realize this minimum commutation time, a maximum duty cycle limit which is no less than (11) is applied to S1(S1n).
S1 S2, S5 S3, S4
vdcn1/n2
vCr iin
ik
iin,ik
ir2
ir1
ir1,ir2
vs1n
vs1,vs1n
vs1 vs2
vs2,vs2n
vs2n
t0 t1 t2t3
t4 t5 t6
vdcn1/n2 t7
Fig. 3 Key waveforms of proposed converter
Vg
D. Conduction loss minimization Besides soft switching, there is another clear advantage of this topology. Normally, during the boost “on” stage when Lin is energized, for the two-stage solution where the PFC stage is composed by diode rectifier and boost cell, or single stage isolated AC-DC converter using full-bridge topology, at least three or four switches are within the conduction path if accounting the input diode bridge [1, 4, 10]. As is shown in Fig. 2(d), the proposed circuit requires only two switches S1 and S1n during the boost “on” stage. This feature is coincident with the well developed bridgeless AC-DC converter for PFC stage [17-18]. Due to this feature, the conduction loss of the converter is reduced significantly. III. CONTROL STRATEGY EXPLANATION The control strategy of the proposed PFC converter is simple. As traditional CCM PFC controller such as UC3854 [19] can be used to implement CCM close loop control. Only a additional modulation block is required to generate the gating signals for all the switches. It only needs digital logic gates and flip-flop gates. The complete control diagram is shown in Fig. 4. It is divided into two parts. The first part of the control diagram is the typical control diagram for CCM PFC control, where Vg represent the input grid voltage. Hi is the current sampling gain. GVdc and GI are the compensator gains for DC voltage loop and current control loop respectively. It should be noticed that as traditional PFC control samples the voltage and current after the diode rectifier, so two math blocks which are used to calculate the absolute values of AC voltage and AC inductor current are added. In the gate signal distribution block, the generation of the gate signal is based on the original gating signal from PFC controller, which is given by Gpfc. It is also the gate signal for S1(S1n) after an off-delay is added. Gpfc is also sent to a J-K flip-flop gate to generate two complimentary square signals. These two square waves are “AND” with the complimentary wave of Gpfc. The two result signals are for S2(S2n), S5(S5n) and S3(S3n), S4(S4n) respectively after off-delays are added. A detection of the direction of iLin is required. The detection results are marked as Ip and In. if Ip is “1” and In is “0”, signal for S1n- S5n are disabled and kept off. Conversely, S1- S5 are kept off.
2
Fig. 4 Control diagram for proposed converter
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IV. SIMULATION RESULTS OF PROPOSED CIRCUIT A simulation is carried out to verify the proposed circuit. An inductor Lsource is added to the AC input voltage source to emulate the grid impedance. And a capacitor Cfilter is added to represent the input filter. The value of all the components is given in TABLE I. The design of main circuit components such as input inductor Lin and output capacitor Co follows the common design process for traditional PFC front end stage. Commutation inductors Lr1 and Lr2 require several hundreds of nH to guaranteed the ZCS. In this simulation, 2.5ȝH is selected to show the ZCS process more clearly in simulation. The leakage inductor Lk is defined by the manufacturer’s performance. 0.01 p.u., or 0.68ȝH is selected for the simulation. According to these value, Clamping capacitor Cr is set to be 50nF to limit the voltage overshoot less than 100V under full load condition.
found that the waveforms in Fig. 5 when AC input voltage is on the peak are similar with Fig. 3 shows. The soft switching performance of S1 displays clearly as indicate at the time of t1 and t5. There is very few voltage and current overlap at the time of the switching transient. In a same manner, the soft switching performance of S2(S2n) displays at the time of t2 and t4. On the other hand, the spike of voltage ringing on Cr is also control to be lower than 500V, which is safe for all 650V switches. According to the waveforms shown in Fig. 6 when AC input voltage is crossing zero, the soft-switching is still realized even if the transformer current Lk and the input current ILin are all nearly zero. This is because that the VCr can be self reversed by resonance with Lin. G1
1 0.5 0
VCr 400 200 0 -200 -400
TABLE I SPECIFICATION OF SIMULATION FOR PROPOSED CIRCUIT Output power Pout 3kW Input AC voltage Vin 208Vac Output DC voltage Vdc 540Vdc Switching frequency fsw 100kHz Input inductor Lin 150ȝH Converter Commutation inductor Lr1, Lr2 2.5ȝH Clamping capacitor Cr 50nF Leakage inductor Lk 0.68ȝH Turn ratio n1:n2 35:54 Output capacitor Co 2.2mF Switch voltage rating Vswitch 650V Source impedance Lsource 100ȝH Grid Grid filter capacitor Cfilter 6.8ȝF
ILin,ILk 6 4 2 0 -2
iLin
iLk ILr1, ILr2
8 6 4 2 0 -2
iLr1
iLr2 Vs1, Vs1n
600 400 200 0
vs1
vs1n Vs2, Vs2n
vs2
400 200
G1 1 0.5
t1 t2
0 500
VCr(V)
2ȝs/div
Fig. 6 Key waveforms in one switching period when AC input voltage is crossing zero
0 -500 50
vs2n
0
Vdc, Vref(V)
545
ILin,ILk(A)
0
540
ILr1, ILr2(A)
vdc
vref
-50 535
20 10 0
Vin(14.75V), Iin(A)
50
Vs1, Vs1n(V)
0
400 200 0
iin vin
-50
Vs2, Vs2n(V)
50
400 200 0
ILin(A)
0
Fig. 5 Key waveforms in one switching period when AC input voltage is on the peak
The simulation results are given in Fig. 5-Fig. 7. The key waveforms of the components in one complete switching period are shown in Fig. 5 and Fig. 6. It can be
-50
5ms/div
Fig. 7 Simulation waveforms for Input and output waveforms
Fig. 7 shows the input and output waveforms of the AC-DC converter. The voltage waveform of vin is scaled down to be the same level with input current iin. It shows
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that the PFC function is almost realized. Although the current is slightly distorted during the zero-crossing transient which can also be found in the inductor current iLin, which limit the THD to be 6.5%, further optimization can be made to improve the current waveform shape. V. CONCLUSIONS In this paper, a boost-matrix-type single stage isolated AC-DC converter is proposed for high power single phase PFC applications. The advantages of the converter include soft-switching for all the switches in all the load range and traditional PWM technology applied. Conduction loss is also minimized by using bridgeless concept. In this paper, the topology derivation and circuit operational analysis are given. The soft-switching condition is derived by calculation. A control strategy is also introduced to show that the circuit can be control by traditional PFC controller plus a simple gating distribution circuit. A simulation is carried out to verify the circuit.
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