Space Vector and Carrier-Based PWM Modulation ... - IEEE Xplore

3 downloads 0 Views 1MB Size Report
Tennessee Technological University, Cookeville, USA [email protected], [email protected], [email protected]. Abstract—The nine-switch converter (NSC) has ...
Space Vector and Carrier-Based PWM Modulation Schemes for Maximum Utilization of Voltage Sources of a Nine-Switch Converter Kennedy Aganah, Student Member, IEEE , Sosthenes Karugaba, Student Member, IEEE, Olorunfemi Ojo, Fellow, IEEE Department of Electrical and Computer Engineering/Center for Energy Systems Research Tennessee Technological University, Cookeville, USA [email protected], [email protected], [email protected] Abstract—The nine-switch converter (NSC) has been used in power quality conditioners and AC motor drives. However, it has not attracted much attention because of its amplitude, frequency and phase-shift limitations primarily due to the constraint on the modulation index of the converter. To satisfy the modulation constraint and correctly synthesize the desired voltages, 'appropriate' DC offsets must be added to the phase voltage commands. This study proposes space vector (SV) and carrier-based (CB) modulation schemes for the NSC that enable the realization of the converter full capacity. The mathematical formulation of the SV and CB pulsed-width modulation schemes are supported by MATLAB/Simulink simulations and validated with experimental results.

I.

INTRODUCTION

Recently, some researchers have shown keen interest in the nine-switch converter (NSC) shown in Fig. 1. It has been used in independent control of two 3-phase AC loads [1]-[4] and in unified power quality conditioners, [5] , [6]. The NSC has also been used to control the doubly-fed induction generator [7], permanent-magnet synchronous generator [8] and a six-phase machine drive system [9]. Hereinafter, the upper portion of the NSC comprising the upper and middle switches (Tap, Tbp, Tcp and Tam, Tbm, Tcm) is referred to as NSC1 whereas the lower portion comprising the middle and lower switches (Tam, Tbm, Tcm and Tan, Tbn, Tcn) is NSC2. The NSC topology requires a higher rated DC-link voltage to produce the same output voltages compared to using two, 2-level voltage source converters [1], [2].This limitation might overshadow the gains that come with its reduced component count as the switches may be unduly overstressed. In the topology shown in Fig. 1, observe that the middle switches (Tam, Tbm, Tcm) are shared between NSC1 and NSC2. This condition imposes switching constraints that limit the amplitudes and frequencies of the phase voltages to be synthesized. To ensure Kirchoff's voltage law (KVL) and Kirchoff's current law (KCL) are not violated during operation , the modulating signals of NSC1 at any instant must always be greater than the modulating signals of NSC2 [1], [3], [4]. This has been accomplished in

978-1-4673-0803-8/12/$31.00 ©2012 IEEE

[1], [2], [10] by adding ‘appropriate’ DC offsets to the two modulating signals so that the switching constraint is not violated. So far, however, there has been little discussion about how these ‘appropriate’ offsets are chosen. For example, whereas [2] adds 1/4 of the DC voltage to upper reference and subtracts same from the lower reference, [10] selects DC offsets equal to the maximum and the minimum of the phase voltages for upper and lower references respectively. The aim of this study is to determine mathematically the DC offset expressions required to ensure the realization of the converter full capacity. The paper is organized in the following order. In Section II, a detailed Space Vector Pulse-Width Modulation (SVPWM) scheme of the nine-switch converter is outlined followed by that of the Carrier-Based Pulse-Width Modulation (CB-PWM) scheme in Section III. In Section IV simulation and experimental results are presented.

Figure 1: Topology of the nine-switch converter

II.

SPACE VECTOR PWM (SV-PWM) OF NINE-SWITCH CONVERTER

A. Space vector diagram and switching sequence In the NSC topology shown in Fig. 1, there are 26 different possible switch combinations of the top and bottom switches. However, Kirchoffs’ current and voltage laws must be obeyed to prevent short-circuiting the DC source and ensure current continuity. Thus, the following constraint on the switching functions must be satisfied: (1) S ip + S im + S in = 2

2521

where Sip, Sim, Sin are respectively the switching functions of the upper, middle and bottom devices and have a value of unity when they are turned-on and take a value of zero when turned-off. The subscripts i = a, b, c refer to the output phase to which the device is connected; p, m, n refers to the top, middle and bottom devices of the converter leg, respectively. In addition to the constraint in (1), to realize an independent control of the two 3-phase AC outputs, the active states of NSC1 are chosen such that they produce zero states in NSC2 and vice versa [2]. The aforementioned constraints reduce the allowed switching states to fifteen (15). When expressed in the stationary reference frame, they are shown as in Fig. 2 [11][12]. For example, U1 has the effect of producing an active vector, U1 [2Vd/3, 0, -Vdc/6] in NSC1 but a zero vector, U1 [0, 0, -Vdc/2] in NSC2. However, U7 has the opposite effect; producing a zero vector, U7 [0, 0, Vdc/2] in NSC1 and an active vector, U7 [2Vd/3, 0, -Vdc/6] in NSC2. Any desired two 3-phase voltage sets expressed in the stationary ∗ ∗ reference frame , Vqd 1 , Vqd 2 may be synthesized from their respective immediate adjacent space vectors, Vqda , Vqdb and Vqdc , Vqdd respectively in addition to the zero vectors

Vqd 01 , Vqd 02 and Vqd 03 as shown in Fig. 2. The normalized times that the switching devices producing

Vqda , Vqdb ,

Vqdc , Vqdd , Vqd 01 , Vqd 02 and Vqd 03 are applied are t a , t b ,

t c , t d , t01 , t02 and t03 respectively. Hence,

⎡taVqda + tbVqdb + t01Vqd 01 + ⎤ ⎫ ∗ Vqd ⎥⎪ 1 =⎢ ⎣⎢t02Vqd 02 + t03Vqd 03 ⎦⎥ ⎪⎪ ⎬ ⎡tcVqdc + t dVqdd + t01Vqd 01 + ⎤ ⎪ ∗ Vqd 2 = ⎢ ⎥⎪ ⎣⎢t02Vqd 02 + t03Vqd 03 ⎦⎥ ⎪⎭ where, ∗ ∗ ∗ ∗ ∗ ∗ Vqd 1 = Vq1 + jVd 1 , Vqd 2 = Vq 2 + jVd 2 ,

Expanding and separating (2) into real and imaginary parts, gives the expressions for the normalized turn-on of the device times listed in (3). t a = (VddbVq∗1 − VqqbVd∗1 ) / Δ1 ⎫ ⎪ tb = (VqqaVd∗1 − VddaVq∗1 ) / Δ1 ⎪ ⎪ Δ1 = VqqaVddb - VddaVqqb ⎪ ⎪ ∗ ∗ tc = (Vddd Vq 2 − Vqqd Vd 2 ) / Δ 2 ⎪ ⎪ t d = (VqqcVd∗2 − VddcVq∗2 ) / Δ 2 ⎪⎬ (3) ⎪ Δ 2 = VqqcVddd - Vqqd Vddc ⎪ ⎪ t0 = t 01 + t02 + t 03 ⎪ t0 = 1 − (t a + tb + t c + t d ) ⎪ ⎪ t01 = αt0 , t02 = βt 0 ⎪ ⎪⎭ t03 = γt 0 = (1 − α − β)t0 where, α , β and γ are the distribution factors for the zero vectors U01, U02 and U03 respectively. The zero voltage vectors have no effect on the values of t a , t b , t c , t d . The expression for the normalized times in (3) can be generalized as [13]: t a = 1.5V1 (cos α1 − 1 / 3 sin α1 ) ⎫ ⎪ ⎪⎪ tb = 3V1 sin α1 (4) ⎬ tc = 1.5V2 (cos α 2 − 1 / 3 sin α 2 )⎪ ⎪ t d = 3V2 sin α 2 ⎪⎭ * * V1 = mag (Vqd 1 ) / Vdc , V2 = mag (Vqd 2 ) / Vdc * where χ1 = angle(Vqd 1 ) = π ( n1 − 1) / 3 + α1

(2)

* χ 2 = angle(Vqd 2 ) = π ( n2 − 1) / 3 + α 2

and mag( ) refers to the magnitude of the variable in the parentheses; the integers n1 , n2 are the space vector sector numbers (1~6) shown in Fig. 2.

Vqdx = Vqqx + jVddx ;

x = a, b, c, d ,01, 02 or 03

V qdb t b

Vqd* 1

V qdd t d

Vqdata V qdc t c

(a)

Vqd* 2

(b)

Figure 2: Space vector diagrams of nine-switch converter (a) NSC1 output (b) NSC2 output

2522

TABLE I: SWITCHING SEQUENCE FOR ALL POSSIBLE SECTOR COMBINATIONS

Switching Sequence

* Vqd 1 in

* Vqd 2 in

U01->Ua->Ub->U03->Uc->Ud->U02->U02->Ud->Uc->U03->Ub->Ua ->U01 U01->Ua->Ub->U03->Ud->Uc->U02->U02->Uc->Ud->U03->Ub->Ua ->U01 U01->Ub->Ua->U03->Uc->Ud->U02->U02->Ud->Uc->U03->Ua->Ub ->U01 U01->Ub->Ua->U03->Ud->Uc->U02->U02->Uc->Ud->U03->Ua->Ub ->U01

( I,III,V) ( I,III,V) ( II,IV,VI) ( II,IV,VI)

( I,III,V) ( II,IV,VI) ( I,III,V) ( II,IV,VI)

The sum of the normalized active times in (4) must be less than or equal to unity as given by (5). Substituting the expressions of the active times given as in (4) into (5), the modulation indices constraint can be determined by taking the partial derivatives of (5) with respect to α1 and α 2 , and then setting the resulting expressions to zero. Equation (6) shows the resulting expression to which any modulation scheme must therefore obey. (5) t a + tb + t c + t d ≤ 1 m1 + m 2 ≤ 2 / 3

(6)

where the modulation indices are defined * * m1 = 2 mag (Vqd 1 ) Vdc and m2 = 2 mag (Vqd 2 ) Vdc .

as

The switching vector sequence for the proposed SVPWM scheme is shown in Table I. Fig. 3 shows the corresponding switching patterns for all the possible sector combinations. Note all three zero vectors are being used but appropriate distribution factors may be chosen to achieve a particular PWM scheme. For example, if the desired ∗ ∗ voltages, Vqd 1 , Vqd 2 are located in sectors I and VI respectively, the corresponding switching sequence is U01->U1->U2->U03->U7->U12->U02->U02->U12->U7->U03>U2->U1 ->U01. B. Generalized neutral voltages for NSC The average neutral voltage can be approximated by (7). If the normalized times are expressed in terms of the line-toline voltages, and maximum/minimum phase voltages , the generalized neutral voltages after some mathematical manipulations for all possible sector combinations can be generalized as given by (8). ⎡V0 at a + V0btb + V0c tc + V0 d t d + ⎤ (7) < Vn 0 >= ⎢ ⎥ ⎣V01t01 + V02 t02 + V03t03 ⎦ ⎡Vdc / 2(1 - 2α) + (α - 1)Vmax1 +⎤ ⎫ Vn0 = ⎢ ⎥⎪ ⎣αVmax2 - α(Vmin1 + Vmin2 ) ⎦⎪ ⎬ ⎡Vdc / 2(2β - 1) + (β - 1)Vmin2 + ⎤ ⎪ Vm0 = ⎢ ⎥⎪ ⎣βVmin1 - β(Vmax1 + Vmax2 ) ⎦ ⎭

(8)

where Voa, V0b, V0c, V0d are respectively the zero sequence voltages of the active vectors Ua ,Ub, Uc, and Ud; Vmax1 = max( Van , Vbn , Vcn ); Vmin1 = min( Van , Vbn , Vcn ); Vmax2 = max(Vxm , Vym , Vzm ) ; Vmin2 = min( Vxm , Vym , Vzm )

Vjn and Vkm are the phase voltages; j = a, b, c; k = x, y, z; Vdc is the DC-link voltage as shown in Fig. 1. In general, there

are three (3) zero vectors; and depending on the choice of the values for α , β and γ, all 3 zero vectors, or 2 zero vectors or 1 zero vector can be applied. Under all possibilities the sum of α , β and γ must be less than or equal to unity. For example when α =β = γ = 1/3, the neutral voltages in (8) reduce to (9). This condition corresponds to the classical SV-PWM in the 2-level converter when α = β = 1/2 [13]. Vn0 = Vdc / 6 − 1 3 (2Vmax1 − Vmax2 + Vmin1 + Vmin2 ) ⎫ ⎬ Vm0 = -Vdc / 6 − 1 3 (Vmax1 + Vmax2 − Vmin1 + 2Vmin2 )⎭

(9)

Equation (8) represents the general DC offsets that must be added to the two sets of modulation signals so that the switching constraints are not violated. In particular if α = β = 0 and γ = 1, the expressions in (8) reduce to (10) which are the same as those in [10] for discontinuous CB-PWM. Vn0 = Vdc / 2 − Vmax1 ⎫ ⎬ Vm0 = − Vdc / 2 − Vmin2 ⎭

III.

(10)

CARRIER-BASED (CB) PWM OF THE NINE-SWITCH CONVERTER

Based on the feasible switching states and (1), it can be shown that the switching functions of the devices in a leg are related by (11) and the voltages between the converter legs and the mid-point of the DC-link capacitor are given by (12) as follows: Sip + Sim Sin = 1⎫⎪ ⎬ Sin + Sip Sim = 1⎪⎭

(11)

V j 0 = V jn + Vn 0 = Vdc (2 S ip − 1) / 2 ⎫ ⎬ Vk 0 = Vkm + Vm 0 = Vdc (1 − 2 S in ) / 2⎭

(12)

The expressions for the switching functions, (13), of the top and bottom devices can be obtained from (12) and the corresponding modulation signals can be obtained as in (15). S ip = (V jn + Vn 0 ) / Vdc + 0.5 ⎫⎪ ⎬ S in = − (Vkm + Vm 0 ) / Vdc + 0.5⎪⎭

(13)

The relationship between the switching functions and the modulation signal is given by: (14) Sip = 0.5(1 + M ip ) and Sin = 0.5(1 + M in ) Substituting (14) into (13) results into the following expressions for the modulation signals. * M ip = 2V jn / Vdc + 2Vn0 / Vdc , * M in = −( 2Vkm / Vdc + 2Vm 0 / Vdc )

⎫⎪ ⎬ ⎪⎭

(15)

where Mip, Min are respectively the modulation signals of the upper and bottom devices.

2523

(a)

(c)

(b)

(d)

Figure 3: Switching sequence for all possible sector combinations between NSC1 and NSC2 outputs where

∗ Vqd 1

,

∗ Vqd 2

are located in sector (a) I, III or V

and I, III, or V ;(b) I, III or V and II, VI or VI; (c) II, VI or VI and I, III or V and (d) II, VI or VI and II, VI or VI. Vxm [V]

Van [V]

50 0 -50 0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

Vym [V]

Vbn [V]

50 0 -50 0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

50 0 -50 0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

0.09

50 0 -50 0.04

Vzm [V]

Vcn [V]

50 0 -50 0.04

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

0.09

(a)

50 0 -50 0.04

(b)

Figure 4: Phase voltages with α = β = γ = 1/3 for (a) NSC1 output (f1 = 60 Hz) and (b) NSC2 output (f2 = 30 Hz) using SV-PWM

2524

voltages, for phases 'abc' and 'xyz', respectively, to be synthesized are: Van = (50/√3) cos(2π60t), Vbn = (50/√3)cos (2π60t - 2π/3), Vcn = (50/√3)cos (2π60t + 2π/3); Vxm = (50/√3) cos (2π30t), Vym = (50/√3)cos (2π30t -2π/3), Vzm = (50/√3) cos (2π30t +2π/3). The DC-link voltage of 100 V is used and therefore m1 = m2 = 1/√3, (where m1 = peak(2Vjn/Vdc) and m2 = peak(2Vkm/Vdc) are the peaks of the reference modulation signals). The converter switching frequency chosen is 1 kHz. These simulations are performed for both SV-PWM and CB-PWM schemes.

Mip

0.8

Min

0.6 0.4

Mip, Min

0.2 0 -0.2 -0.4 -0.6

A. SV- PWM The implementation of the SV-PWM in MATLAB/Simulink consists of first identifying the sectors of the desired voltages to be synthesized. The time of application of active and zero vectors are then calculated and arranged according to the predefined switching pattern depicted in Fig. 3. Fig. 4 shows all the phase voltages for NSC1 and NSC2 produced using the proposed SV-PWM. The low frequency components of the synthesized voltages and the reference voltages have been superimposed. With α = β= γ = 1/3, Fig. 4 shows that, the desired voltages have correctly been synthesized.

-0.8 0.04

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

0.09

Figure 5: Continuous CB-PWM signals of the upper and lower switches with f1 = 60 Hz, f2 = 30 Hz, α = β= γ = 1/3 V an [V]

50 0 -50 0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

0.09

V bn [V]

50 0 -50 0.04

V cn [V]

50 0 -50 0.04

V ym [V]

V xm [V]

(a) 50 0 -50 0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

B. Continuous CB-PWM (CPWM) Fig. 5 shows the carrier based modulation signals corresponding to SV-PWM given in (9). The generated voltages shown in Fig. 6 with the low frequency components and reference voltages superimposed on each other. They are exact replica of the waveforms generated using the SV-PWM in Fig. 4. In the simulation, α = β = γ = 1/3 (equivalent to SVPWM) in (8) have been apportioned to synthesize the desired voltages. This equal apportioning of the zero vectors results in maximum voltage utilization for both NSC1 and NSC2. By injecting the neutral voltages into the modulation scheme, the sum of the modulation indices is increased from unity to 1.155.

50

1

0 -50 0.04

Mip

0.8

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

Min

0.6

0.2

0 -50 0.04

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

Mip, Min

V zm [V]

0.4

50

0.09

-0.2

(b) Figure 6: Phase voltages with α = β = γ = 1/3 for (a) NSC1 output (f1 = 60 Hz) and (b) NSC2 output (f2 = 30 Hz) using CPWM

IV.

0

-0.4 -0.6 -0.8

SIMULATION AND EXPERIMENTAL RESULTS

Simulations were performed using Matlab/Simulink to validate the proposed PWM schemes. In the following simulations, the desired two sets of balanced 3-phase

-1 0.04

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

0.09

Figure 7: Discontinuous CB-PWM signals for the upper and lower switches with f1 = 60 Hz, f2 = 30Hz and δ = 0o

2525

C. Discontinuous CB-PWM (DPWM) If we define α = 0.5[1 + sgn((cos 3(ω1 t + δ))] and α + β = 1 (i.e. γ = 0), we can generate infinite DPWM

schemes by simply varying the modulation angle, δ . In the above expressions, sgn(X) is 1, 0 or -1 for X > 0 , X = 0 and X < 0 , respectively; δ is the modulation angle and ω1 is the frequency of NSC1 output. Fig. 7 shows the modulation signals with δ = 0o and the corresponding 3phase voltages of both outputs are shown in Fig. 8. Fig. 9 shows the corresponding converter line-to-line voltages.

Van [V]

50

of Fig. 1(a). Furthermore, it should be noted that Sam = 1, Sbm = 1 and Scm = 0 for the constraint in (1) to be met. Under such circumstances, an observation on Fig. 1 will reveal that this with this state, the voltage across the switches Tap, Tam, Tbn and Tcm will be equal to Vdc, whereas for the voltage across the other switches will be zero. Since at any particular switching condition, two switches will be on in one phase, using the per phase truth table the voltage stress on each device in a leg can be determined in terms of the switching functions, as shown in Table II for phase 'a'. Fig. 10 shows the simulation of the voltage stress on each device in a leg showing that the switching losses per cycle on the middle devices are about twice those of the top and bottom devices.

0

TABLE II: CALCULATING DEVICE VOLTAGE STRESS

-50 0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

State 1 2 3

Vbn [V]

50 0

0.04

Vxy [V]

-50

Vcn [V]

50 0

0.04

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

Vxz [V]

-50 0.09

Vab [V]

50 0 -50 0.04

0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

50 -50 0.04

Sin 1 1 0

Device Voltage (1- Sip)Vdc (1- Sim)Vdc (1- Sin)Vdc

100 0 -100 0.04

0.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.05

0.06

0.07

0.08 0.09 0.1 Time [secs]

0.11

0.12

0.13

0.14

100 0 -100 0.04 100 0 -100 0.04 100 0 -100 0.04

(a) 0.045

0.05

0.055

0.06

0.065

0.07

0.075

0.08

0.085

0.09

50

100 0 -100 0.04

0.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.05

0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.05

0.06

0.07

0.08 0.09 0.1 Time [secs]

0.11

0.12

0.13

0.14

0 -50 0.04

0.045

0.05

0.055

0.06 0.065 0.07 Time [secs]

0.075

0.08

0.085

0.09

Vxz [V]

V zm [V]

Sim 1 0 1

0

Vxy [V]

V ym [V]

V ac [V]

V xm [V]

(a)

Sip 0 1 1

100 0 -100 0.04

Figure 8: Phase voltages with δ = 0o (a) NSC1 output (f1 = 60 Hz) and for (b) NSC2 output (f2 = 30 Hz) using DPWM

A. Voltage stress on the devices It can be shown that when a device is turned-off, the voltage across it is equal to the input DC voltage, Vdc. As an example consider the condition following combination of switches on all three phases (a, b and c): Sap = 0, San = 1, Sbp = 1, Sbn = 0, Scp =1 and Scn = 1. This represents the state U1

2526

Vac [V]

Vab [V]

(b) 100 0 -100 0.04 100 0 -100 0.04

(b) Figure 9: NSC line-to-line voltages with (a) f1 = 60 Hz, f2 = 30Hz and(b) f1 = f2 = 60Hz using CPWM

VTip [V]

100 50 0

0

0.005

0.01

0.015

0.02

0.025

0.03

0

0.005

0.01

0.015

0.02

0.025

0.03

0

0.005

0.01

0.015 0.02 Time [secs]

0.025

0.03

VTim [V]

100 50 0

V Tin [V]

100 50 0

Figure 10: Voltage stress on devices

Figure 12: CB-PWM signals of the upper and lower switches with f1 = 60 Hz (Ch1), and f2 = 30 Hz (Ch2), α = β= γ = 1/3

B. Experimental Results The assembled prototype of the NSC is shown in Fig. 11. The gate PWM signals were generated using dSPACE ds1104 real-time controller. Using the assembled prototype, a 100V DC voltage was supplied to the converter with a balanced resistive load connected to the six phases in order to get access to the neutral point. However, the line-to-line voltages were measured at no-load. The experimental waveforms are shown in Figs. 12-16. Fig. 12 shows the matching experimental waveforms of the modulation signals of the upper and bottom switching devices, which are found to agree well with the simulation results in Fig. 5. Figs. 13 and 14 show the experimental phase and lineto-line voltages corresponding Figs. 8 and 9 (a). Observe that the two different frequencies have been produced and match well with simulation results. In Figs. 15 and 16, the experimental waveforms using the same frequency (60 Hz) for NSC1 and NSC2 are also depicted.

V.

Figure 13: Phase voltages: Ch1, Ch2 - NSC1 output (f1 = 60 Hz) and for Ch3, Ch4 - NSC2 output (f2 = 30 Hz)

CONCLUSIONS

The space vector and a carrier-based modulation methodology for the NSC have been proposed. The generalized neutral voltages for the NSC have been derived for the first time in this paper.

Figure 14: Line voltages: Ch1, Ch2 - NSC1 output (f1 = 60 Hz) and for Ch3, Ch4 - NSC2 output (f2 = 30 Hz)

Figure 11: Nine-switch converter prototype

Simulation results show that injecting these neutral voltages into the modulation signals would result in maximizing the NSC voltage capacity. The effect of neutral

2527

voltage injection on the CB-PWM scheme in particular is that the sum of the modulation indices is increased from unity to 1.155. The two 3-phase voltages have been correctly synthesized using both SV-PWM and CB-PWM modulation techniques. It has also been shown by simulation that the voltage stress on each device will be equal to the input dc voltage (Vdc), with the middle switching devices having about twice of the stress as that of either the top or bottom switching devices.

REFERENCES [1]

[2]

[3]

[4]

[5]

[6]

[7]

Figure 15: Phase voltages: Ch1, Ch2 - NSC1 output (f1 = 60 Hz) and for Ch3, Ch4 - NSC2 output (f2 = 60 Hz)

[8]

[9]

[10]

[11]

[12]

Figure 16: Line voltages: Ch1, Ch2 - NSC1 output (f1 = 60 Hz) and for Ch3, Ch4 - NSC2 output (f2 = 60 Hz)

[13]

2528

Kazuo Oka, Kouki Matsuse, “A nine-switch inverter for driving two AC motors independently,” IEEJ Transactions on Electrical and Electronic Engineering, vol. 2 , no. 1,pp. 92-96, 2007. T. Kominami, Y. Fujimoto, “A Novel Nine-Switch Inverter for Independent Control of Two Three-Phase Loads, ”in Proc. 2007 IEEE 42nd IAS Annual Conf. on Industry Applications, pp.23462350, 23-27 Sept. 2007. Xiong Liu, Peng Wang, Poh Chiang Loh, and F. Blaabjerg, “A Compact Three-Phase Single-Input/Dual-Output Matrix Converter,” IEEE Transactions on Industrial Electronics, vol.59, no.1, pp.6-16, Jan. 2012. X. Liu, P. Wang, P. Loh, F. Blaabjerg, "A Three-phase Dual-Input Matrix Converter for Grid Integration of Two AC Type Energy Resources," IEEE Transactions on Industrial Electronics (Early Access). Congwei Liu, Bin Wu, N. R. Zargari, Dewei Xu and Jiacheng Wang; “A Novel Three-Phase Three-Leg AC/AC Converter Using Nine IGBTs,” IEEE Transactions on Power Electronics, vol.24, no.5, pp.1151-1160, May 2009. Lei Zhang, Poh Chiang Loh, Feng Gao, "An Integrated Nine-Switch Power Conditioner for Power Quality Enhancement and Voltage Sag Mitigation," IEEE Transactions on Power Electronics , vol. 27, no. 3, pp. 1177-1190, March 2012. Nyan Paing Soe, D. M. Vilathgamuwa, Kay-Soon Low , "Doubly Fed Induction Generator for wind energy generation using nine-switch power converter," in Proc. 2011 37th Annual Conf. on Industrial Electronics Society , pp.3608-3613, 7-10 Nov. 2011. M. Heydari, A. Y. Varjani, M. Mohamadian, H. Zahedi, "A novel variable-speed wind energy system using permanent-magnet synchronous generator and nine-switch AC/AC converter," in Proc. 2011 IEEE 2nd Power Electronics, Drive Systems and Technologies Conf. (PEDSTC), pp.5-9, 16-17 Feb. 2011. E. C. dos Santos, C. B. Jacobina, O. I. da Silva, "Six-phase machine drive system with nine-switch converter," in Proc. 2011 IEEE 37th Annual Conf. on Industrial Electronics Society pp.4204-4209, 7-10 Nov. 2011. Feng Gao, Lei Zhang, Ding Li, Poh Chiang Loh , Yi Tang and Houlei Gao, “Optimal Pulsewidth Modulation of Nine-Switch Converter,” IEEE Transactions on Power Electronics, vol.25, no.9, pp.23312343, Sept. 2010. S. M. D. Dehnavi, M. Mohamadian, A. Yazdian, and F. Ashrafzadeh, “Space Vectors Modulation for Nine-Switch Converers,” IEEE Transactions on Power Electronics, vol.25, no.6, pp.1488-1496, June 2010. S. M. Dehghan, M. Mohamadian, M. A. E. Andersen, "Full space vectors modulation for nine-switch converters including CF & DF modes," in Proc. 2010 IEEE 4th International Conf. on Power Engineering and Optimization (PEOCO), pp.89-94, 23-24 June 2010. O. Ojo, “The generalized discontinuous PWM scheme for three-phase voltage source inverters,” IEEE Transactions on Industrial Electronics, vol.51, no.6, pp. 1280- 1289, Dec. 2004.