Stress and Diffusion Resistance of Low Temperature CVD Dielectrics for Multi-TSVs on Bumpless Wafer-on-Wafer (WOW) Technology H. Kitada1, 2, N. Maeda1, K. Fujimoto3, Y. Mizushima2, Y. Nakata2, T. Nakamura2, T. Ohba1 1 The University of Tokyo, Yayoi, Bunkyo-ku, Tokyo, Japan Fujitsu Laboratories Ltd., Morinosato-Wakamiya, Atsugi, Kanagawa, Japan 3 Dai Nippon Printing, Wakashiba, Kashiwa-shi, Chiba, Japan E-mail:
[email protected]
2
Abstract For Cu through-silicon-via (TSV), stress and diffusion behavior of Cu using low temperature plasma enhanced (LTPE) CVD have been evaluated. The stress of multi-stacked thin Si wafers composed of Cu trough silicon via (TSV) and Cu/low-k BEOL structure was analyzed by the finite element method (FEM), aiming to reduce the stress of LSI devices of Three-Dimensional Integration (3DI). LTPE-CVD silicon-oxy-nitride (SiON) barrier films were formed down to 150°C. A critical density and thickness against to Cu diffusion into Si substrate has been estimated. In case of density 63% of bulk and/or thick-enough 100-nm, no change of electrical resistance after TSV process and 1000 cycles of thermal stress for stacked wafers are revealed. 1.
Introduction The Wafer-on-Wafer (WOW) process has been studied in terms of wafer-scale 3D manufacturability [1, 2] and thermal stress stability for TSV [3]. Ultra-thinning down to 7-μm of 300-mm wafer employed high performance 45-nm Node CMOS Logic devices has been successfully [4, 5]. In the TSV structure for 3DI, large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials [6]. It was clarified fabricating of the LT-TSV process also necessary for the low stress structure. In this paper, relationship between Cu diffusion and LT-PECVD SiON barrier films density are described. By optimizing dielectrics film properties [6], electrical resistance and reliability for bump-less multiple TSVs structure are discussed using wafer stacking of Damascene TSV and 45-nm Node BEOL interconnects. 2.
Experiments By employing a model for the TSV using FEM analysis was calculated for the thermal stress analysis. The residual stress calculated at room temperature assuming a free stress at 250°C of Cu and organic adhesive material. For dielectric films characteristics measurements, SiON and SiO2 dielectric films are deposited on Si substrate by PECVD using conventional silane-based reaction system. Deposition temperature is used from 100°C to 350°C. Relative density (d/d0) was measured by X-ray reflectivity (XRR). Sputtered Cu was formed onto the dielectrics surface and then annealed at 400°C for 10hr. For the evaluation of diffusion rate, Cu depth profiles were measured by Back Side Secondary Ion Mass Spectrometry (BS-SIMS). Wafer was thinned down to 10-μm and bonded by the face to back method onto another having 45-nm Node Cu interconnects. TSV opening and Cu plug filling were carried out using Dual-Damascene (DD) process as shown in Fig. 1. Figure 2 shows a SEM image of Bird's-eye view for the stacked wafer and void-free multiple TSVs array. 3.
Results and discussion Figure 3 shows the results of FEM analysis of the maximum principal stress around TSV of 100-μm thick Si. The Cu stress at the high aspect ratio via had exceeded the
yield stress (286MPa) of Cu. Figure 4 shows a calculation result of the displacement volume on TSV by thermal stress. Pumping volume at the dielectric films on TSV is decreasing with smaller via and lower process temperature. Cross sectional TEM image shows the significance of coverage of barrier metal and dielectric layer at via top and bottom region as shown in fig. 5. Dielectric barrier has only thickness of 30% compared with via top region at via bottom. Cu diffusion profile in the dielectric layers was analyzed by BS-SIMS after annealing at 400°C for thermal aging. Cu diffusion increases with decreasing the deposition temperature of dielectric layer. Figure 6 shows the Cu diffusion rate as a function of the film density relative to the value of bulk Si3N4 and SiO2 calculated using Cu depth profiles. Cu diffusion is higher at low density film formed at low temperature deposition. Figure 7 shows a critical thickness of dielectric films as a function of the relative density. It is defined as a thickness which terminates Cu diffusion within the dielectric layer. In case of density below 50%, thicker than 1000-nm dielectric layer would be needed to suppress Cu diffusion into Si substrate. Figure 8 shows cumulative failure distribution of Cu-BEOL via chain resistance with and without Cu-TSV. Contact resistance of Cu-TSV to Cu-BEOL is estimated at 0.21-mΩ. Thermal stress testing evaluation employed Cu-TSV and BEOL chain contact was carried out from -55°C to 125°C. There is no open failure and significant change in resistance distribution with TSV even after 1000 cycles testing as shown in table 1. 4.
Conclusions Low pumping stress on Cu-TSV caused by CTE mismatch is smaller in the case of a lower process temperature and minimizing via diameter. There were no resistance change in the Cu interconnects with TSVs process and after 1000 cycles of TC testing using LT-PECVD film dielectrics process formed at 150°C. LT-TSV process can be used for high reliability TSV structure for the wafer level stack process, enabling lowered total process temerature in the WOW technology. Acknowledgements This work is carried out in the WOW alliance and the WOW Research Center Corporation. We would like to thank DISCO Corporation, Nissan Chemical, FEI Company, and Fujitsu microelectronics, ATTO R&D Center, sample preparation and analysis. References [1] N. Maeda, et al., Proc. of AMC, (2008) p 91 [2] T. Ohba, et al., Microelectronic Eng. Vol. 87 (3) (2010) p 485 [3] H. Kitada, et al. IEEE IITC (2009) p 107 [4] Y. S. Kim et al. IEEE IEDM Tech. Dig., (2009) p 365 [5] N. Maeda, et al. VLSI Symp. (2010) p 105 [6] H. Kitada, et al. IEEE IITC S9.6 (2010) p 29
Fig. 1. Process flow of Dual-Damascene TSV interconnects for wafer staking.
Fig. 2. Bird's-eye view FIB-SEM image of stacked wafers and multiple TSV on BEOL device. Fig. 3. Maximum principal stress of around TSV of 100-μm thicker wafer.
Fig. 4. Pumping height on the TSV with process temperature. Fig. 5. Cross sectional TEM image (right side) of dielectric barrier at TSV side-wall.
Fig. 6. Cu diffusion coefficient as a function of relative densities. Relative density was refer to bulk Si3N4 as 3.44g/cm3. Fig. 7. Critical thickness of dielectric layer as a function of relative density.
Table. 1. Resistance change of Cu-TSV and BEOL interconnects after TC testing. Before TSV process After TSV process After TC 1000cycle
Fig. 8. Via chain resistance cumulative failure distribution of Cu BEOL interconnects with and without Cu-TSVs.
0.4um dense cahin (Ω)
1.04E+05
1.00E+05
1.01E+05
3um single line (Ω)
10.02
10.04
9.97
