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by sensitive circuits, by way of capacitive coupling and body effect. The victim may be impacted in various ways, such as threshold voltage modulation, delay ...
Substrate Coupling: Modeling, Simulation and Design Perspectives Ranjit Gharpurey1 and Edoardo Charbon2 1University

2

of Michigan, Ann Arbor, MI, USA Ecole Polytechnique Federale, Lausanne, Switzerland

Abstract The finite impedance of silicon substrates has several consequences for the design and performance of ICs. In this paper we discuss the state of the art in the areas of modeling and simulation of these effects. An overview of various modeling techniques is presented, with emphasis on integral-equation based boundary-element techniques. Numerical stability issues related to these techniques are discussed from a physical viewpoint. Impact on circuit design is considered by the means of specific examples. Keywords- substrate coupling, substrate noise, digital noise, power supply noise, impact ionization, constraintdriven optimization, boundary element method, finite element method, discrete cosine transform, fast fourier transform.

1. Introduction The effects of the finite impedance of silicon IC substrates on IC performance can be categorized into two primary types. The first relates to the impact on circuit performance due to the parasitic current path through the substrate, which leads to effects such as loading by substrate impedance, and the presence of parasitic feedback. Another major problem relates to the coupling of uncorrelated or partially correlated signals generated by one circuit or device into another. This is referred to as substrate noise. The subject of substrate noise has received great attention over the recent years due to the potentially harmful consequences in large and complex systems on chip. Scaling of technologies and the increase in the level of integration has made substrate noise an even a more arduous problem. More recently, substrate noise issues have moved from the analog and mixed-signal domain to purely digital designs as a consequence of increased miniaturization and innovative logic design. Substrate-coupled noise is distinct from unavoidable device related sources of noise, such as thermal, shot and flicker noise, in that the causes for this noise are intentional and appear by design. Digital switching activity onchip is a significant source of such noise. This type of noise is injected via capacitive coupling and impact ionization. It can be broadcast over large distances and picked up

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by sensitive circuits, by way of capacitive coupling and body effect. The victim may be impacted in various ways, such as threshold voltage modulation, delay skews and enhanced jitter and phase noise. At especially high risk are dynamic logic, memories, phase-lock loops, low noise amplifiers and oscillators [1],[15],[29]. Among the first to recognize substrate conductivity as a potential hazard have been engineers concerned with the latch-up and other reliability problems [2],[3]. Later, with the growing number of mixed-signal designs, it became apparent that noise injected by digital circuits was limiting the performance of analog circuits. Thus, a number of techniques were studied for substrate noise measurement and modeling [4],[10],[11],[15],[30]. With the development of modeling methodologies, substrate macro-models and design guidelines were reported. [7],[25],[31]. To simulate the propagation of noise through substrate, a multi-port model relating noise injectors and receptors is generally the first step. The model is built by solving a classical potential problem in a closed, electrically non-uniform volume representing the substrate. This can be accomplished numerically by Finite Element (FEM) or Finite Difference (FDM) methods whereby an impedance mesh resulting from the discretization of 3D substrate volume is reduced to the multi-port model. When the substrate is modeled as a resistive mesh, efficient iterative methods, such as, for example, Incomplete Choleski Conjugate Gradient (ICCG) with various types of preconditioners can be used. RC meshes require other techniques that efficiently compute the first most relevant poles and residues of an S-domain representation of the transfer function [5],[6],[9]. Other schemes have been developed to simplify the problem by proper physical discretization of the volume [13]. However, to date discretization remains a major concern to achieve accuracy in these approaches. A very successful alternative has been the use of integral equation based techniques such as the Boundary Element Method (BEM). In this approach only the contacts need be explicitly discretized, therefore the size of the matrix to be solved is much smaller, but dense [8],[14]. A two-dimensional FFT based pre-computation technique was employed in [14], that helped make the computation time of the Green function practical for problems requiring iterations. Heuristics to sparsify this matrix have been attempted using various types of relaxation techniques

[12], or Krylov subspace iterative methods, such as GMRES, in conjunction with either fast multipole algorithms or eigen-decomposition based techniques [23]. However, accuracy loss in the former and convergence performance in the latter are still major concerns. To address these issues, multilevel iterative solvers can be employed, whereby the algorithm operates on two or more discretizations, from coarse to fine for a given contact configuration. In [20] for example, two levels are used. At the lower level a number of sub-matrices are solved locally and the resulting residual is projected to the upper level. At the upper level the coarse grid problem is solved explicitly and the result is projected back to the finer problem, where it is used as a starting point for the next iteration. The iteration ends when the residual norm falls below a tolerance. With the significant reduction in simulation complexity, by use of the above simulation technqiues, and with improvements in computing power, substrate optimization and substrate-driven design have become a realistic option. Design methodologies and semi- or fully-automated design tools have been devised to mitigate the problem [9],[12],[13],[21],[27],[31],[34]. Despite the extensive activity in the field, the utilization of these techniques in the IC design space is still in its early stages and layout for substrate-coupling minimization is driven to a large extent by guidelines and rules of thumb. The latter approach may require iterations in silicon, especially for new technologies, and is thus an expensive option. More recently, techniques to evaluate specific pattern or injection signatures of digital blocks have been proposed. Applications include block analysis and optimization, electromigration control, clock distribution design, power supply routing, design for electromagnetic compatibility, enabling and disabling techniques for reverse-engineering etc. [18][22][24][32].

2. Physical Mechanisms Silicon substrates that are in wide commercial use today can be broadly categorized as high-resistivity and low-resistivity bulk types. Figure 1 shows examples of such types. Low-resistivity substrates are generally preferred for their good latch-up suppression properties [3] which is an important consideration in CMOS. Surface isolation techniques, such as guard-rings are more effective in high-resistivity substrates. At frequencies up to several GHz, silicon substrates exhibit a behavior that can be approximated as being purely resistive. Several mechanisms for substrate noise injection are identified in [16]. Capacitive parasitics associated with reverse-biased junctions are effective injection and reception mechanisms in BJT and CMOS technologies.

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1Pm

1Pm

U ~ 1:-cm

10Pm

U ~ 10-15 :-cm

U ~0.1 :-cm

300Pm U ~20-50 :-cm U ~ 1m:-cm 300Pm

(1)

(2)

Fig. 1: Typical (1) high-resistivity and (2) low-resistivity substrates

In CMOS devices, hot-electron effects also cause injection of majority-carriers into the substrate [17]. Hotelectron effects are observed when the field in the depleted drain-end of the transistor becomes large enough to cause impact ionization and generate electron-hole pairs. The dependence of the hot-electron induced substrate current Isub on device operating current is given by the following semi-analytical expression. K2 I sub = K 1 V ds – V dsat I d exp § – -------------------------------· © V ds – V dsat ¹

[1]

where Id is the drain current, Vds is the drain-to-source voltage and Vdsat is the drain-to-source voltage at saturation. K1 and K2 are semi-empirical constants [36]. Discussion of the frequency domain response of capacitive injection and impact ionization currents can be found in [17] and [18]. Body-effect or bulk-induced threshold voltage modulation is a very effective noisereception mechanism in CMOS devices. Electrically, for majority carrier flow, the substrate behaves as a distributed impedance. Currents injected into the bulk traverse varied paths, depending on material constants such as bulk resistivity and dimensions and also on specific boundary conditions set by the devices and contacts on the surface. In the following section we will discuss techniques to analyze and model this current flow.

3. Simulation and Extraction As mentioned earlier, techniques for extracting substrate models have relied on numerical techniques such as the finite-differences method, or semi-analytical approaches that use for example an integral-equation technique. In either case, in the low-frequency limit, where inductive effects can be neglected, the problem involves a

solution for the Laplace equation in the substrate. [2] Devices are treated as equipotential contacts and a lumped resistive or a frequency-dependent impedance network is extracted between these contacts. The impedance network can be used to model the substrate in a circuit simulator (Fig. 2). The injection and reception mechanisms are assumed to be modeled in the circuit simulator. This is usually the case, for example junction capacitors and the body effect are considered in most circuit simulators while some simulators also include hot-electron induced substrate current. This type of extraction approach has two important issues that need to be considered. The first is the computation time required for substrate extraction. The second issue relates to efficient use of the extracted models. A problem with N substrate contacts leads to a problem with O(N2) simulation elements in the circuit simulator. For a practical IC, it is not feasible to attempt a full scale circuit simulation of this order. Approximations can be employed to partition the problem into smaller sections [34]. Coarse-fine approximation techniques can be employed where the impact of distant contacts is not considered in detail [14]. Ultimately, the efficient use of such an extraction tool will rely on designer intuition, at least in the near future. We will discuss issues related to model extraction in greater detail here, and specifically techniques relying on an integral equation approach. This technique is emphasized here, because the combination of this approach with the FFT allows for efficient, iteration-friendly extraction techniques that can be used in layout-optimization problems. It is important to appreciate, however, that although integral-equation based approaches are fast, the techniques discussed below fundamentally rely on the planarity of the layer interfaces. Thus for complicated surface topologies, fully numerical mesh-based solvers are perhaps the most accurate.

Integral Equation Approach and the Substrate Green Function The integral equation approach to extracting the substrate model relies on the evaluation of the Green function in the multilayered substrate. The evaluation of node-tonode resistance (or impedance) in the electrostatic or quasi-static cases is similar to the problem of capacitance extraction in multi-layered dielectrics, with layer resistivities replaced by equivalent layer dielectric constants. A multi-node capacitance matrix relates the charge vector to the potential vector. The inverse of the capacitance matrix, referred to as coefficient of potential matrix [P], relates the potential at the nodes to the charge placed on

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D2

D3

D1

’2M = 0

Z31 Z12

1

2

Z23 Z2G

Z1G

3

Impedance model

Z3G

G

Fig. 2: A lumped electrical model of the substrate

the nodes. This matrix can be calculated by convolving the charge placed on a node with the Green function in the medium over the volume of the node The Green function is the potential due to a point charge placed at a given location in the medium and is a solution to the Poisson’s equation in the electrostatic case. The potential of a node can be defined to be that of a single point on the node by Eq. [3], or by computing the average potential on the node due to the given charge, by integrating Eq. [3] over the area of the node. The latter option offers the advantage of a symmetric [P] matrix. ) x =

³ U x' G x, x' dv'

[3]

v In a typical formulation of the problem, the charge density on a substrate contact is approximated by a uniform density. The contact itself is divided into sub-sections, to better approximate its charge profile. In order to compute any element pij of the [P] matrix, a unit charge is distributed uniformly over node ‘j’ and the average potential is computed over node ‘i’. This procedure is repeated for all pairs of nodes in the upper half of the [P] matrix. The lower half of the matrix is obtained from its symmetry. The [P] matrix is inverted to extract the node-to-node capacitors. The substrate model is generated by replacing the ratioed dielectric constants with the resistivities of the substrate layers. The above problem was analyzed in [14] assuming Dirichlet boundary condition (uniform potential) on the bottom face of a multilayered substrate, and Neumann boundary condition (zero normal field) on the other faces of the substrate (Fig. 3). Other boundary conditions may also be assumed [8]. Given the above boundary conditions, the potential at (x,y,z=0) due to a point charge located at (x’,y’,z’=0) was shown to be of the following form

Numerical Stability z=0 z= -dN

Z

HN z=-d2

Y X

H2

I=0 at z= -d,

H1

GIGn = 0 on other faces

H0

a

z=-d1

z=-d b

Fig. 3: Typical substrate cross-section and boundary conditions

f

¦

G =

f mn cos Gx cos Gx' cos ]y cos ]y'

[4]

m n = 0

:where mS nS G = ------- ] = -----a b and fmn is given by

[5]

C mn E N tanh J mn d + * N f mn = -------------- u ---------------------------------------------------abJH N E N + * N tanh J mn d

[6]

where Cmn = 4 for (m,n)>0, Cmn = 2 for (m=0 or n=0) and Cmn = 0 for (m=n=0). EN and *N are defined by the following equation for k=N.

Ek *k

=

Hk – 1 2 ----------- – T k Hk

Hk – 1 · § ---------- – 1 Tk © Hk ¹ Ek – 1

Hk – 1 2 k – 1· § 1 – H---------- T k 1 – ----------- T k © Hk Hk ¹

*k – 1

[7]

where T k = tanh J mn u d – d k ;E 0 = 1.0 ;* 0 = 0

[8]

The elements of the [P] matrix are then obtained from following 1 ) p ij = -----i = --------- ³ ³ G x y z x' y' z' ds'ds Qj Si Sj Si Sj

[9]

where Ii was defined as the average potential over node ‘i’ due to Qj and Si and Sj are the surface areas of nodes ‘i’ It was shown in [14] that the above expression could be efficiently calculated using a Discrete Cosine Transform. This formulation has been shown to be particularly suitable for fast calculation and layout optimization [22],[28],[34].

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Proper numerical evaluation of Eq. [6] is essential for the stable computation of the integral in Eq. [9]. In fact, numerical evaluation of Eq. [6] was implemented in [14] using a recursive routine that is reproduced below, instead of a direct computation of Eq. [7]. The recursion occurs over two subroutines, as shown. To within a constant, it can be shown that the routine evaluates the expression in Eq. [6]. The reason for the instability that arises in the direct computation of Eq. [7] is that the coefficients EN and *N rapidly converge to 1 and -1 respectively for large values of m and n. Simultaneously tanh(Jmnd) asymptotes to 1, due to which Eq. [6] approaches a 0/0 form. The code shown below performs a recursive implementation of Eq. [6], to avoid this indeterminate form.

/*kr[m1] = Hm1-1/Hm1*/ /*m1 is the Layer number*/ /*dz[m1] is the z coordinate of the bottom of layer m1*/ double bgnr(m1,m2,gama) {double x,bgdr(); if(m1==0) return(tanh(gama*(dz[0]-dz[1]))); else { x=tanh(gama*(dz[m1]-dz[m2])); x*= (kr[m1]*bgdr(m1-1,m1,gama)); x += bgnr(m1-1,m1,gama); return(x); } } double bgdr(m1,m2,gama) {double x,bgnr(); if(m1==0) return(1.0); else { x=tanh(gama*(dz[m1]-dz[m2])); x*=bgnr(m1-1,m1,gama); x+= (kr[m1]*bgdr(m1-1,m1,gama)); return(x); } }

The routines bgnr and bgdr represent the numerator and the denominator of Eq. [6] in a layer-wise calculation. The above routines can be shown to be inherently stable. Details regarding numerical stability can be found in [19], where numerically stable techniques for contacts defined in any layer of the substrate, have also been discussed. Physical intuition behind the stable recursion is presented below. Unlike the result of Eq. [6], that evaluates the effect of all substrate layers in the highest layer, in one calculation, the recursive routine in fact builds the solution one layer at a time. It can be easily proven that the general expression for the potential in the layer (-dk J mn d k + z @ J mn H k

[10] where )(-dk) is the potential and D(-dk) is the magnitude of the electric displacement at z= -(dkG  where G! . For the evaluation of potential in any given layer, therefore, we can equivalently replace the layer below it by its boundary potential and normal displacement vector. If the potential evaluated at the lowest layer is finite, the recursive nature of this procedure ensures that the potential in all layers can be evaluated precisely, without numerical instability. For the boundary conditions shown in Fig. 3, the potential in the lowest layer is given by ) = Sinh > J mn d + z @ , which allows for stable computation. Symmetry of the Green function in the observation layer at the surface between the observation point and the charge location (z,z’) [16] allow us to express the above expressions in a form that is equivalent to that in Eq. [6].

4. Macro-models and Macroscopic Characterization Many researchers have successfully combined extraction techniques of the type discussed in section 3, with circuit simulators, and successfully demonstrated a high correlation between simulated (or expected) and measured waveforms [4],[10],[11],[18],[25],[26],[35]. As the complexity of ICs increases, macromodeling approaches become critical to fast evaluation of substrate coupling. An approach based on digital signatures is presented in [18]. Substrate noise generated by patterns of inputs on digital logic can be analyzed by means of these signatures. In some cases, prediction of the impact of injected noise in frequency domain is possibly a faster solution. In the case of complex digital and mixed-signal blocks, the noise injected into the substrate is often in phase with the clock or other global synchronization signals. A closer analysis shows that the power spectrum associated with these types of noise has energy components located in a wide frequency band, not necessarily centered at the clock frequency [22]. A significant portion of this energy is usually concentrated around special frequency bands, e.g. at the inverse of the average gate delay. At DC or near DC frequencies, one also observes large spurious currents. This is due to the fact that impact ionization, by its very nature, only generates positive currents. Higher frequency components are due to glitches and fast switching phenomena occurring in large circuits. Other authors [34] have used efficient partitioning techniques on

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large scale ICs to localize the substrate problem in order to achieve high computation speed. Multigrid techniques are also especially useful for reducing the size of the problem for macromodeling [20].

5. Impact of Substrate Coupling on Circuit Performance Substrate coupling can impact circuit performance in several ways [31]. We consider some of the effects on analog and digital circuits below.

Analog Circuits The substrate behaves electrically as a distributed impedance. Analog circuits, especially low-noise or highdynamic range implementations, can suffer performance degradation if the impact of this impedance is not considered during design and layout. Thus it is important to be aware of the mechanisms by which the substrate impedance can impact circuit performance. In a high-gain amplifier, for example, the substrate can provide a path for signal feedback. Depending on the characteristics of the loop, the impact of this feedback could vary from a loss in bandwidth to oscillation. The feedback path also limits the maximum stable gain of high-frequency devices. Current injection into the substrate produces local variations of the substrate potential, which in turn impacts the threshold voltage of MOS devices built on the substrate and is thus a source of device mismatch. This can be of concern in high precision analogto-digital and digital-to-analog converters. The finite resistance of the substrate also acts as a loss mechanism in passive circuits. Passives such as inductors and capacitors built on lossy substrates can suffer a degradation in the quality factor due to power loss in the substrate. In addition to the above, a major risk introduced by substrate coupling in the possibility of noise injection into sensitive analog nodes. This is becoming an ever greater concern due to the increased levels of integration of analog and digital circuits. High dynamic range systems such as radio transceivers are especially susceptible to substrate noise. For example, the harmonics of low-frequency switching noise can couple into the substrate and appear in the desired band of the radio receiver front-end. Noise at low-frequencies can be upconverted by circuit non-linearity and similarly appear in-band. Harmonics of switching noise can also cause frequency pulling in oscillators, and thus cause unintentional modulation in transmitters. In each of the above examples the dynamic range of the system can suffer due to substrate noise.

Aggressor

Cc

Victim

Victim

Cs

Aggressor

Fig. 4: Analogy between classical capacitive coupling and substrate coupling

tp

Digital Circuits While analog circuits have been traditional areas of concern in relation to substrate noise, it is expected that some classes of digital circuits will also be impacted by this noise mechanism. We discuss one such effect below namely, the variation of logic delay induced by substrate coupling [31]. Logic gate delay t0.5 is a function of several factors, including fanout, supply voltage, transistor geometry, input waveform, and charge excess caused by charge sharing effects. Ignoring for now wiring parasitics, the gate delay is usually approximated by t 0.5 = R EFF u C G [11] where CG is the gate capacitance. REFF, the effective resistance, is the average transistor resistance during the output voltage swing. With some reasonable approximations, it can be shown that t 0.5 v 1 e V SB

[12]

where VSB is the voltage applied between its substrate contact and the source. Voltage ripple on substrate contacts can therefore apply directly to the logic circuit performance. The second source of substrate-induced delay is capacitive coupling with the bulk. Capacitive coupling between an aggressor and a victim signal line has been extensively studied. One of the first -yet complete- works on the subject can be found in [37]. This has also been discussed more recently in [38]. Classical line-to-line capacitive coupling is important since it can be seen as substrateto-line coupling with identical effects at a macroscopic level as shown in Fig. 4. Therefore the original analysis can be applied to the case of substrate coupling. Capacitive coupling may result in acceleration, extra delay, or glitches in the victim data. All three types of hazards can interfere for example with the timing of a datapath causing performance reduction or even functional errors. If equivalence Cc = Cs is assumed, then the standard model found in the literature can be used (Fig. 5).

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Resistor R1 represents the impedance holding the victim node at ground potential, while R2 is the effective impedance looking into the substrate contact from the aggressor perspective. Using standard analytical charge coupling models based on [37], one can estimate the charge noise present in the interconnect line due to substrate noise. A close form analytical model for the response voltage to charge injection v1(t) was derived in [37]. The voltage at the peak and the instant at which it occurs are respectively W ­ ° WW 1 W , 2 1 ® ln( 1 ) °¯W 2 W 1 W 2

v1 (t p )

Cc ­ 1 if ° C C e ° 1 c W ® 1 ° Cc ( W 1 )e W 2 W1 °¯ C1  Cc W 2

W1 W 2 otherwise

[13] where W1 = (R1 || R2)(C1+Cc) and the waveform of the aggressor voltage v2 is assumed to be a decaying exponential step with time constant W2. From charge noise one can derive the extra delay present on a gate. Empirical delay models based on cross-talk have been proposed in the literature. One such model, relating the length of the parallel running wire l and the average spacing s to the extra delay 'W, was proposed in [39]. The model computes 'W as m

l 'W = D ----ns

[14]

where D is a fitting constant, while m and n are parameters empirically observed to be near 2 and 1, respectively.

6. Conclusion In this paper, we have reviewed recent work in the area of modeling and extraction of substrate coupling. Possible mechanisms for performance degradation in analog and digital circuits have also been identified. Two topics that are not discussed here, but are of significant importance are techniques for mitigation of substrate noise and mea Victim

Aggressor Cc

V1

R1

C1

+

C2 V2

Fig. 5: Standard cross-coupling model

R2

surement techniques for accurate estimation of substrate noise. Substrate coupling and techniques for mitigation of the negative consequences of this parasitic phenomenon in ICs have been an active area of research for process and technology engineers, system architects and the simulation community. The significance of substrate coupling and related effects in the design of ICs can be expected to increase with the continued interest in achieving higher levels of integration.

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