HU, SENIOR MEMBER, IEEE. Abstract âA concise arrafytical expression for switch-induced error voltage on a switched capacitor is derived from the distributed.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL SC-19,NO. 4, AUGUST1984
519
Switch-Induced Error Voltage on a Switched Capacitor BING
Abstract voltage
—A
concise
on a switched
arrafytical
capacitor
model. The result, however, equivalent error
circuit.
voltage
circuit
With
voltage.
simulations
expression
switch
for
from
can be interpreted
switch-induced
error
the dependence
rate, source resistance,
is supported
SENIOR MEMBER, IEEE
““x,
in terms of a simple lumped
can be used to qnic$fy
expression
HU,
MQSFET
the distributed
we explore
turnoff
These results
The analytical
computer
STUDENT MEMBER, IEEE, ANp CHENMING
is derived
this expression
on process,
parameters.
J. SHEU,
A
of the
and other
predict
?----f”
the error
by the close agreement
with
-L—
and experiments.
Fig. ~.
Schematic of the switch circuit under study
LIST OF SYMBOLS B
Conductance
CL co~ c c:
Storage capacitance Gate-drain overlap capacitance Gate capacitance (excluding overlap Gate capacitance
G
Channel
L
Effective
L~
Lateral
coefficient A/D, D/A converters, and filters (1]. An MOS transistor holds mobile charges in its channel when it is on. When the capacitance)
transistor
turns off, some portion
transferred
per unit area
conductance
the
channel
feedthrough
diffusion
N sub
Substrate
R~
Source resistance
t
Gate-oxide
length (L~,.W, – 2L~)
sampled
source
falling
rate
Signal voltage
the transistor
threshold
with back-gate
this
bias
is not included only
voltage
error
the
overlap
of an MOS switch
As the gate volta~ge
both the source end and
voltage.
switched
The
capacitor
can
‘dm
Absolute
end and by minimizing
very slowly
w
Channel
gate-drain [3] have INTRODUCTION
overlap been
voltage.
analysis), through
continues
to increase
error
be reduced
by
voltage turning
capacitance.
used
However,
to minimize
little
the
the
on off
a the
swing that
the effect of the
Compensation
to reduce
the
to the source
the part of gate voltage voltage
and
During
feedthrough
to allow charges to return
is below the threshold
width.
clock
switch-induced
switch vd~
in our analytical
capacitance
reaches V~
I.
voltage
capacitance
enters the second phase of turnoff.
phase,
gate-drain
voltage at drain end at time t voltage at drain end after gate voltage Of
clock
the drain end. When the gate voltage reaches the threshold voltage, the conduction channel disappears (subthreshold
at the source
voltage
of the transistor.
charges exit through
conduction
value
The overlap
to the error. The turnoff
source to the drain falls, mobile
Gate voltage
‘dn
1).
of the signal voltage
thickness
Gate voltage High value of V~ Low value of V~
Error Error
Fig.
also contributes
;
vd~t )
(see
the gate–drain
consists of two distinct phases. During the first phase, the tr~sistor is on and a conduction channel extends from the
VG VH VL vVT v
Zero-bias
voltage through
charges is
and causes an error in
distance
doping
Threshold
of the mobile
to the storage capacitor
schemes [2],
switch-induced
error
work has been done on the analysis
of this phenomenon.
T
limit
HE MOS
error
voltage
switch
the accuracy
induced
by the turning
is one of the fundamental of switched-capacitor
off
of an
factors
circuits,
that
such as
In this paper,
the switching-off
behavior
of
the MOS switch. An analytical expression for the switchinduced error voltage is derived. Using this expression we explore
Manuscript receivedJuly 6, 1983; revisedJanuary 12, 1984. This work was sup orted in part by Micro Project under the Semiconductor Research (?orporation and in part by DARPA under Contract NOO039-81K-0251. The authors are with the Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA 94720.
we analyze
gate quickly tions
the dependence
voltage predict and
derivation is discussed
0018 -9200/84/0800-0519$01
falling the
error
experiments of
the in
of the error voltage on process a~d
rate.
lumped
Appendix
.00 01984 IEEE
These
voltage. are
used model
I.
results Finally,
to validate from
the
can be used computer the
analysis.
distributed
to
simulaThe model
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 4, AUGUST 19&$
520
When
the transistor
region
( VH > VG > v’s + ‘~),
is operated
in the strong
inversion
i~=Gv~=fl(V&.-Ut)v~
(4)
where
Equation
L
(3) becomes
(a)
The solution
of the differential
equation
is
‘HlvL
Col
“.(’) =-m[co’:.%]e
Col
“)
(-;
TCL
“{erf[m4-erf[G@41
-L.
(b) Fig. 2.
Eqnivafent lumped models for the circuit shown in Fig. 1. (a) VT> VG > V~. This equivalent circuit is derived in Appendix I. VH,> VG > V’ + VT. (b) V’+
II.
We due
assume
to the
is not off,
ANALYTICAL that
significant. all
and
the
in
In
ends. Fig.
end
of
with
value
storage
pumping
other
The
source
charge
charges words,
mobile
the
capacitor
switch and
with
the
exit
is
is used
to for
connected
the drain
to
the
CL.
When amount
analyzed
The
first
overlap
voltage.
error
an exact
model is not arbitrarily analysis
After
continues
voltage
at
this
is
the gate voltage of
V~ = V~
only
to contribute time
capacitor
reaches its final
switch-induced
the
to
th~
is
error
value V~,
voltage
on
a
the
total
switched
is
The voltage
to a
equivalent -&~+V,
-V~).
(8)
chosen but results from
of the distributed
MOSFET
model
as
It is well known
that
shown in the Appendix. From the KCL law
(1
erf(x) c~%=-i’+(c+%)d(v>i”d)
We assume that the gate voltage is a ramp function which begins to fall at time O from the high value V~ toward the low value V~ at a falling rate U
Ut.
if.x>>l
= 1%’(’-~)
‘1)
VG= VH–
(
that
UCL
T
~
lumped models for the circuit during the first and second phases of turnoff are shown in Fig. 2. The configuration of the lumped
is reached
ends.
capacitor
The
r
condition
phase
(7)
turns
end is connected
capacitance
error
source
illustration). a signal
gate-drain
the threshold
the
traps
transistor
be
and
[4]
interface
through
schematic
switch
l+,
the
V~~/U,
+ VT)
Vd(t)=-
phenomenon
by
when
charges
circuit
1 (NMOS
source
OF ERROR VOLTAGE
of channel
channel
drain
shown
the
capture
MODEL
At t’=
therefore,
(8) can be
simplified
ifxu
Under
the condition
ldV~/dtl
c~%=-i’-(cl+%)u
>> du~/dtll,
(1)
simplifies
to
2CL
Col+ +
‘3) Udm
1This assumption is also needed m denvmg the lumped model. See Appendix L
=
CL
)r *
+>(VS+VT– L
VJ
(9)
SHEU AND
HU:
SWITCH-INDUCED
ERROR
VOLTAGE
ON A SWITCHED
521
CAPACITOR
for fast switching-off ‘D M
~S (VOLT)
9
(MV)
~o 8
@I @2
7
@)3 1
6
5 t
4-
@
(lo) 32 -
III.
DEPENDENCE
ON PROCESS
AND
ELECTRICAL I
PARAMETERS
The switch-induced i$ affected interest
by many
source
doping,
resistance
The
parameter
factors
falling
values used in the following L~ = (S.35pm,
= 5.0*
1014
V“ns-l, values
voltage
Fig. 3.
size, and
source.
2 pF, tox= 70
SUBSTRATE 0oPING(CM-3)
76-
discussion
5-
value of this error
and denote it as Udw.
4 -
A. Dependence on Gate Voltage Falling
Rate
3 -’ 2-
Error voltage ud~ is plotted against the gate voltage falling rate ranging from 104 V“ S-l to 1011 V“ s-l for four signal voltage levels, O, 1, 2, and 3 V in Fig. 3. In the case of slow falling rate, most of the channel charges return to the source
when
priniarily overlap
the switch
is on,
due to the clock capacitance
slow fding
RATE (‘/s)
9-
designs. From (8) we notice that the switch-induced error voltage of an NMOS switch is negative, In the following voltage
FA;;NG
‘D M (MV)
and I.L.C; X=25*10”6 A“V-2. These are to be found in the state-of-the-art circuit
we will focus on the absolute
,~o
The error voltage as a function of the gate voltage falling rate for four signal voltage levels.
4
nm,
V~=OV,
~H=5V,
(
8
106
Common
examples are: W=
CL=
p’TO =0.6~,
cm–3,
signal
transistor
voltage
01 I04
capacitor
of the greatest
rate,
oxide thickness,
of the signal
pfn, L = 3.3 pm, fl=l tfiical
factors.
are the gate voltage
level, substrate
N S*
error voltage on a switched
and
the error
feedthrough
voltage
I
2
rate, U& saturates at ( 1“~+ VT – VL ) CO1/CL,
3
4
5
VS(VOLTS)
Fig. 4.
off. At a very
can be seen from (9). In the case of fast falling
I
0
is
of the gate-drain
after the switch is turned
‘t
The error voltage as a function of the signal voltage level for five substrate dopings.
as
rate, nearly
one half of the channel charges are deposited in the storage capacitor and ud~ saturates at VH~(CO1 + C.X/2)/CL +
C. Dependence on Oxide Thickness
(VS + V* – VL)CO1/CL
Advances in silicon technologies continue to make smaller MOS device dimensions possible. As the device size shrinks, the oxide thickness reduces, too. If storage capacitor oxide and gate oxide are scaled by the same factcm,
3, it
is obvious
minimized
that
as can
be
seen
the
dependence
by judiciously
choosing
~. Dependence on Signal
from of
(10).
From
Fig.
V~ may be rate.
Udm on
the falling
Voltage Level and Substrate
(Cl + COX/2)/C~ remains constant. The effect of CL increase due to oxide reduction is exactly balanced by the effect of ~ increase (assuming constant W/L) such that
Doping Error
voltage
five substrate
Udn is dopings
plotted
against
signal
V’ for
voltage
in Fig. 4. As the substrate
doping
increases, body effect increases accordingly, which in turn causes the threshold voltage in (8) to become more sensitive to Vs. The argument of the error function in expression substrate doping. As (8) is smaller for large V~ or heavier long
as the
rates,
ud~
first is
term
a strong
heavy-substrate-doping
in
(8)
function circuits.
dominates, of
V~
e.g., and
at more
fast so
falling in
the
the square root term and the error function unaltered.
Hence, error voltage
D. Dependence on Channel Transistor
term in (8) are
ud~ is not affected.
Width and Length
size is one of the most important
variables
ih
circuit design. Designers have to choose the appropriate combination of transistor sizes in order to achieve optimum circuit performance. Error vohage Udm iS plotted
lMSL JUUKNAL Vk SVLIIJ-STATE
2,2A
CIRCUITS,
VOL.
SC-lY,
NO. 4, AUGUST
1YX4
VDM(MV) 60-
CHANNEL WIOTH(/lJM )
40 -
‘HkL
@
01 50 -
&
@4 @7
@
010
L-J R~
30 -
1
@
20 10 -
—
0 ,
0 2
3
4
6
5
7
CL
“s
8910
Fig, 6.
Schematic of theswitch circuit with source resistor.
CHANNEL LENGTH(PM) Fig.
The error voltage as a function of transistor channel length for four channel widths
5.
—
against
channel
length
ranging
from
1 to 10 pm for four
with
the set of typical
listed at the beginning
circuit
parameter
SIMULATION
A A A
SIMULATION
W
000
SIMULATION
wz IPF
Source impedance The
values 15 -
of this section.
14 -
of the signal voltage
circuit
schematic
which
13 -
affects the error
includes
a source
resistance is shown in Fig. 6. Derivation of the analytical model including source resistance is quite similar to that without source resistance and is attached as Appendix II. Error voltage is plotted against source resistance in Fig. 7.
12 -
As the source resistance
10 -
return
increases,
fewer
to the source end of the transistor
channel
II -
charges
and error voltage
becomes larger.
IV.
9 -
COMPARISON
To validate
0.5PF
OVERLAP OF D, A , 0
16r”xx
E. Effect of Source Impedance
voltage.
a
‘oM(MV)
different channel widths, 1, 4, 7, and 10 pm in Fig, 5. It is clear that smaller transistor size introduces smaller error voltage
ANALYTICAL MODEL u
❑
WITH
the model,
COMPUTER
computer
8~
SIMULATION
simulations
10
using the
* XQC
OF SWITCH-INDUCED
