Switched-Capacitor Converters with Multiphase Interleaving Control
∗ Department
Sitthisak Kiratipongvoot∗ , Siew-Chong Tan∗† , Senior Member, IEEE, and Adrian Ioinovici‡ , Fellow, IEEE
of Electronic and Information Engineering, Hong Kong Polytechnic University, Hong Kong E-mail: enksvolt@polyu,edu.hk;
[email protected] † Experimental Power Grid Centre, A∗ STAR, Singapore E-mail: tan siew
[email protected] ‡ Department of Electrical and Electronic Engineering, Holon Institute of Technology, Holon, Israel E-mail:
[email protected]
Abstract—This paper proposes a configuration of switched-capacitor converters with multiphase interleaving control that can perform conventional switched-capacitor voltage conversions with little electromagnetic interference over a wide range of operating condition. This is achieved by having multiple units of switched-capacitor converter connected in parallel and a unit selection control scheme which works along the interleaving control to vary the number of converters in operation. By having the capacitors of inactive units connected to the output and the converters operating with output interleaving operation, the output capacitor that is typically required in switched-capacitor converters for maintaining a small voltage ripple is made redundant in this configuration.
I. I NTRODUCTION A typical switched-capacitor (SC) converter is a standalone converter made up of one or more circuit phases of capacitors and switches that are controlled by PWM control [1]. An SC converter with PWM control, however, inherits the problem of having a large pulsating input current, which leads to electromagnetic interference (EMI) problems [2]–[6]. By operating the MOSFET switches of the SC converters in their nonsaturation region such that the input current can be regulated as a constant current [2], the converter will not have any pulsation appearing in its input current waveform, making them EMI free. However, it requires a precise voltage control for the gate drive circuit which is a very complicated circuit. Another possible method of alleviating EMI in SC converters is to reconfigure multiple units of SC converters as a parallel converter and to operate the units in interleaving operations applied at both the input and output terminals. Here, one SC converter phase is always turned on precisely at the time when another phase is turned off such that there is continuity in the flow of the input current from the
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input supply, and the output voltage ripple is minimized [3]–[5]. The interleaving methods proposed in [5]–[8], however, work perfectly at steady-state operation, but fail to give the expected results from interleaving as soon as a variation appears in the input voltage or load. Hence, in [9], an adaptive approach which ensures that all units of the parallel SC converter operate together with a variable charging time for maintaining input interleaving, and also at a switching frequency that changes correspondingly to the charging time for maintaining the output regulation and the output interleaving, under a varying load and input voltage, is proposed. However, there is a stringent limit to the range of load and input voltage that can be applied using this method. For a much wider operating range, a different approach of interleaving must be adopted. In this paper, we propose a configuration of SC converter with multiphase interleaving control that is applicable to a much wider operating range. The method incorporates a unit selection scheme which varies the number of active SC converter units in operation based on the level of the operating load, and adopts a variable frequency control to maintain the input and output interleaving operations and voltage regulation. Additionally, in this method, the SC converter is optimally configured such that all the capacitors are always in a charging or discharging process, and never in a holding or idling state. Literature review suggests that this is the first time such a design has been adopted in parallel-SC converter. The advantage is that it allows the maximum amount of energy to be transferred from the input source to the load by the SC converter using the least required capacitance. II. D UAL -P HASES S WITCHED -C APACITOR C ONVERTER A. Circuit Topology and Timing Diagrams Fig. 1(a) shows a simple dual-phase SC converter. Here, 𝑆1 and 𝑆3 are controlled to deliver energy from the source to the flying capacitors 𝐶1 and 𝐶2 , respectively.
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(a) A dual-phase SC converter Fig. 1.
(c) An inactive mode timing diagram
A dual-phase SC converter and its timing diagrams.
(a) State 1 of active mode Fig. 2.
(b) An active mode timing diagram
(b) State 2 of active mode
(c) Inactive mode
Equivalent circuits of the active mode and inactive mode operations of the dual-phase SC converter.
𝑆2 and 𝑆4 are controlled to deliver energy from the flying capacitors 𝐶1 and 𝐶2 , respectively, to the output capacitor 𝐶O and the load 𝑟L . The timing diagram is shown in Fig. 1(b). It can be seen that 𝑇on(S1) = 𝑇on(S3) = 𝑇S /2, where 𝑇S is the switching period. Also, the output voltage can be regulated by adjusting 𝑇S . Note that in the proposed control scheme, the SC converter does not operate in the holding/idling state. B. Operating Modes of Dual-Phase SC converter 1) Active mode: According to the timing diagram given in Fig. 1(b), it can seen that there are two operating states in one switching period. The equivalent circuit of State 1 is shown in Fig. 2(a). Here, the flying capacitor 𝐶1 is in its charging phase, of which during steady state, it is charged with a maximum input current which decays exponentially with a time constant 𝜏𝑐ℎ = 𝑟ch 𝐶1 . Simultaneously, the flying capacitor 𝐶2 is in its discharging phase whereby its energy is discharged to the output 𝑟L . Thus, the discharging time constant is 𝜏dis ≈ (𝐶1 + 𝐶O )𝑟L . In State 2, the role of the two capacitors are interchanged (see in Fig. 2(b)). 2) Inactive mode: Fig. 1(c) shows the timing diagram of inactive mode and Fig. 2(c) shows the equivalent circuit of the SC converter when both 𝑆1 and 𝑆3 are turned off but 𝑆2 and 𝑆4 are turned on. It can be seen that flying capacitors 𝐶1 and 𝐶2 are connected in parallel to the output 𝐶O and 𝑟L . In this mode, the equivalent output capacitance is increased through the parallel connection of 𝐶1 , 𝐶2 , and 𝐶O . Thus, the discharging time constant is 𝜏dis ≈ (𝐶1 + 𝐶2 + 𝐶O ) × 𝑟L .
III. P ROPOSED S WITCHED -C APACITOR C ONVERTER WITH M ULTIPHASE I NTERLEAVING C ONTROL A. Topology and Timing Diagrams
Fig. 3. Timing diagrams of a three-unit configuration of the proposed SC converter.
The proposed multivariable-phase SC converter can be made up of 𝑁 units of the dual-phase SC converters (depending upon the load) connected in parallel. As an illustration, a three-unit configuration (see Fig. 3) is used for the discussion. Since the proposed converter is operated with both input and output interleaving, its
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(a) light load Fig. 4.
(b) medium load
(c) heavy load
Timing diagrams of a three-unit configuration of the proposed SC converter.
output voltage ripple will be automatically minimized by the interleaving process. Therefore, there is no specific need for an output capacitor at the load, which allows us to remove 𝐶O . The converter is designed for three ranges of load, which can be classified as light load (1 active unit and 2 inactive units), medium load (2 active units and 1 inactive unit) and heavy load (all units are active). The timing diagrams are shown in Figs. 4(a), 4(b), and 4(c), respectively. To achieve interleaving, each unit of the converter will operate with a phase delay of duration 𝑇S /2𝑛 from one another, where 𝑛 is the number of active units, which is determined by the load. Flying capacitors of inactive units are all connected to the load to increase the overall equivalent output capacitance. This is important for minimizing the ripple since the reduction in the number of active units leads to poorer output interleaving and a higher ripple.
(a)
(b)
B. Closed-Loop Control Methodology Fig. 5(a) shows an overview of the proposed SC converter with the closed-loop control block diagram. There are two feedback signals, namely the output voltage and the output current. The PI compensator provides the necessary compensation for output voltage regulation. The output of the compensator is fed into the voltagecontrolled oscillator (VCO) to generate the controlled switching frequency 𝑓VCO , which is then decoded by the oscillator decoder into four signals. The charging signals have a switching frequency 𝑓S = 𝑓VCO /12, a duty ratio 𝐷on = 0.5, and an interleaving time delay 𝑇D = 1/(2𝑛𝑓S ). The output current signal is measured by the difference amplifier and is compared to the current reference in the voltage comparator before passing to the active unit selector. The state selection diagram and the
(c) Fig. 5. (a) Closed-loop control block diagram, (b) state selection diagram and (c) unit selection scheme of the proposed converter.
unit selection scheme are shown in Figs. 5(b) and 5(c), respectively. The output signals are the charging signals. The discharging signals are the inverse of the charging signals.
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C. Theoretical Derivations Assuming that the discharging time constant is much larger than the discharging time duration, i.e., 𝜏dis ≫ 𝑇dis = 𝑇on /𝑛, it is reasonable to approximate the change of charges of the capacitor during discharging Δ𝑄out as a linear relationship between its ripple voltage and its capacitance such that Δ𝑄out = 𝐶𝑣C(max) −𝐶𝑣C(min) = 𝑇dis × 𝐼O ,
𝑣C(min)
(1)
where 𝐼O is the average output current and is 𝐼O = 𝑉O /𝑟L . From (1), we can derive 𝑇on 𝑉O . 𝑣C(max) −𝑣C(min) = 𝑛𝑟L 𝐶
2 [𝑟+(2𝑁 −𝑛)(𝑟sen +𝑟L )] 𝑉O (2𝑁 − 𝑛)𝑟L (5) where 𝑟sen is the sensing resistance of the output current. Substituting (4) into (5), we have 𝑣Cdis(max) +𝑣Cdis(min) =
(2)
=
[𝑟+(2𝑁 −𝑛)(𝑟sen +𝑟L )] 𝑉O (2𝑁 −𝑛)𝑟L 𝑇on 𝑉O . − 2(2𝑁 −𝑛)𝑛𝑟L 𝐶
(6)
According to the charging condition, there are 𝑛 flying capacitors which are parallel charged with interleaved time delay (𝑇D ). However, all of the flying capacitors are charging from the source separately. Thus, the equivalent circuit of each flying capacitor is shown in Fig. 7. The charging characteristic of the each flying capacitor can be expressed as ] [ −𝑇on 𝑣C(max) = (𝑣i −𝑣C(min) ) 1−𝑒 𝑟ch 𝐶 +𝑣C(min) . (7)
(a)
Fig. 7. Equivalent circuit of the flying capacitor in the charging duration (0 < 𝑡 ≤ 𝑇on ). (b) Fig. 6. (a) Discharging circuit of one active-unit mode and (b) its equivalent circuit.
Fig. 6(a) shows the discharging circuit of one activeunit condition and Fig. 6(b) shows its equivalent circuit. Here, the minimum voltage of the equivalent discharging capacitor 𝑣Cdis(min) is simply the minimum voltage of capacitor 𝑣C(min) . Using the principle of charge balance, the maximum voltage of the equivalent discharging capacitor 𝑣Cdis(max) can be found in terms of the maximum and minimum voltages of the capacitor as 𝑣Cdis(max) =
𝑣C(max) (2𝑁 −𝑛−1)𝑣C(min) + , (2𝑁 −𝑛) (2𝑁 −𝑛)
(3)
where 𝑁 is the total number of converter units and 𝑛 is the number of active units. From eqns. (2) and (3), the maximum voltage of 𝐶dis can be derived as 𝑣Cdis(max) =
𝑇on 𝑉O +𝑣C(min) . (2𝑁 −𝑛)𝑛𝑟L 𝐶
(4)
Additionally, the average voltage of 𝐶dis can be expressed as
From (2), (6), and (7), the DC conversion ratio can be derived as 2𝑛𝑟L 𝐶 𝑉O = , (8) 𝑣i 𝛼1 +𝛼2 [ ( ) ] 1 on +1− (2𝑁−𝑛) , 𝛼2 = where 𝛼1 = 𝑇on coth 2𝑟𝑇ch 𝐶 [ ] 2𝑛𝑟𝐶 (2𝑁−𝑛) + 2(𝑟sen + 𝑟L )𝐶, 𝑉O is the average value of the output voltage, 𝑣i is the input voltage, 𝐶 is the flying capacitance, 𝑇on is the charging time period, 𝑟ch is the charging resistance, 𝑟 is the turn-on resistance of switches, 𝑁 is the total number of SC units, 𝑛 is the number of active units, 𝑟L is the load resistance, and 𝑟sen is the output current sensing resistance. Eqn. (8) can be alternatively expressed as ) ] [ ( 2𝑁 −𝑛 − 1 𝑇on + = 𝑇on coth 2𝑟ch 𝐶 (2𝑁 −𝑛) ] [ 2𝑛𝑟𝐶 𝑣i −𝑉O −2𝑛𝑟sen 𝐶. (9) − 2𝑛𝑟L 𝐶 (2𝑁 −𝑛) 𝑉O on In Taylor series, when 𝑥 = 2𝑟𝑇ch 𝐶 , 𝑐𝑜𝑡ℎ(𝑥) can be 1 𝑥 approximated by 𝑥 + 3 . Therefore, (9) can be simplified as ]) ( [ √ 2𝑁 −𝑛−1 (10) 𝛼3 − 𝑇on = 3𝑟ch 𝐶 × 2𝑁 −𝑛
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(a) At 𝑛 = 1
(b) At 𝑛 = 2
(c) At 𝑛 = 3
Fig. 8. Plots of the charging time versus the input voltage and the load resistance obtained from theoretical calculations: (a) 𝑛 = 1, (b) 𝑛 = 2, and (c) 𝑛 = 3 for 𝑟ch = 0.49 Ω, 𝑟 = 0.08 Ω, 𝑟sen = 0.01 Ω, 𝑁 = 3 and 𝑛 = {1, 2, 3}. The output voltage is regulated at 9 V.
]2 [ ] [ ] [ 𝑣i−𝑉O 4𝑛𝑟 L − − where 𝛼3 = 2𝑁−𝑛−1 + 4𝑛𝑟 2𝑁−𝑛 3𝑟 3(2𝑁−𝑛)𝑟 ch ch 𝑉O [ ] [ ] 4𝑛𝑟sen − 43 . 3𝑟ch The 3D plots of the charging time versus the input voltage and the load resistance obtained from theoretical calculations using (9) are shown in Figs. 8(a)–8(c) for 𝑛 = 1, 2, and 3, respectively. It can be seen that the charging time decreases as the output current increases, and for the same 𝑇on , the output current increases as 𝑛 increases. According to the discharging characteristic, the output ripple can be derived as 𝑉O(rip) =
𝑇on 𝑉O . [𝑟 + (2𝑁 − 𝑛)(𝑟sen + 𝑟L )]𝑛𝐶
(11)
Fig. 9 shows the range of the input voltage that can sustain the interleaving condition. It can be found by solving (8) for 0 ≤ 𝑇on ≤ 4𝜏ch . The boundary limits of 𝑉in are given as ] [ ] [ 2𝑟ch 𝑉O 𝑟+(2𝑁 −𝑛)(𝑟L +𝑟sen ) (12) 𝑉O ≤ 𝑣 i ≤ 𝛼4 (2𝑁 −𝑛)𝑟L 𝑛𝑟L 𝑛[𝑟+(2𝑁 −𝑛)(𝑟sen +𝑟L )] −𝑛−1 where 𝛼4 = coth (2) + 2𝑁 . (2𝑁 −𝑛) + 2(2𝑁 −𝑛)𝑟ch
45
Input voltage (V)
40 35
high limit where n=1 high limit where n=2 high limit where n=3 lower limit where n={1,2,3}
The specifications of the proposed multivariable-phase SC converter prototype are: 𝑉in = 12𝑉 , 𝑉o = 9𝑉 , and 𝑃o = 20 to 100 W. The charging switches are implemented using IRF9520, and the discharging switches are implemented using IRF5305. The value of the flying capacitors are 47 𝜇F. Figs. 10(a)–10(c) show the total input current, phase currents, flying capacitor voltage and the output voltage ripple when 𝑇on is 9.74 𝜇𝑠. It can be seen that regardless of the turn-on time, perfect interleaving at different loads and active modes can be achieved. Figs. 11(a)–11(c) give the transient response of the proposed multivariable-phase SC converter. For a step load changing between 2.5 A to 6.0 A (see Fig. 11(a)), the settling time for the controlled voltage is around 500 𝜇s for both the step down and step up conditions. For a step load changing between 2.5 A to 10.0 A (see Fig. 11(b)), the settling time for the controlled voltage is around 500 𝜇s and 4 ms for the step down and step up conditions, respectively. For a step load changing between 6.0 A to 10.0 A (see Fig. 11(c)), the settling time for the controlled voltage is around 1 ms and 4 ms for the step down and step up conditions, respectively. Notice that during the load disturbance, the SC converter can still maintain its perfect interleaving operation. V. C ONCLUSIONS
30 25 20 15 10 5 2
IV. E XPERIMENTAL R ESULTS AND D ISCUSSIONS
4
6
8
10
12
14
Output current (A)
Fig. 9. Plots of input voltage boundary limits versus output current for 𝑉O = 9 𝑉 , 𝑟ch = 0.49 Ω, 𝑟 = 0.08 Ω, 𝑁 = 3, 𝑛 = {1, 2, 3}.
A configuration of switched-capacitor converter with multiphase interleaving control is proposed to widen the range of operating condition of existing switchedcapacitor converters. The problem of the pulsatory input current, and hence of the associated large electromagnetic interference, which is the typical characteristic of switched-capacitor converters, is solved for both steadystate and transient operations by using interleaving operation of 𝑁 converters. The merit of the proposed solution is that this is achieved without affecting the line and load regulation capability of the converter, and without
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(a) At 𝑖o = 3.43 A
(b) At 𝑖o = 6.35 A
(c) At 𝑖o = 9.00 A
Fig. 10. Waveforms of the total input current, phase current, flying capacitor voltage and output voltage of the proposed SC converter when (a) output current is 3.43 A, (b) output current is 6.35 A, and (c) output current is 9.00 A, respectively.
(a) Load change: 2.50 A and 6.00 A
(b) Load change: 2.50 A and 10.00 A
(c) Load change: 6.00 A and 10.00 A
Fig. 11. Waveforms of the total input current, output current, and output voltage waveforms with step load change alternating between (a) 2.50 A and 6.00 A, (b) 2.50 A and 10.00 A, and (c) 6.00 A and 10.00 A, respectively.
affecting the output voltage ripple as typically happens in frequency-controlled switched-capacitor converters. A low output voltage ripple is achieved regardless of the frequency, by using a high equivalent output capacitance (𝐶out = (2𝑁 −1)𝐶) when the load is light, and by using a smaller equivalent output capacitance (𝐶out = 𝑁 𝐶) when the load is heavy, along with the output interleaving operation. VI. ACKNOWLEDGMENT This work is supported by an internal competitive research grant from the Hong Kong Polytechnic University (Grant Ref: 4-ZZ7X). R EFERENCES [1] K. Jin, M. Nur, M. Xu, and F. C. Lee, “A switching-capacitor PWM DC–DC converter and its variations,” IEEE Transactions on Power Electronics, vol. 25, no. 1, pp. 24–32, Jan. 2010. [2] H. S. H. Chung, S. Y. R. Hui, S. C. Tang, and A. Wu, “On the use of current control scheme for switched-capacitor DC/DC converters,” IEEE Transactions on Industrial Electronics, vol. 47, no. 2, pp. 238–244, Apr. 2000. [3] J. Han, A. V. Jouanne, and G. C. Temes, “A new approach to reducing output ripple in switched-capacitor-based step-down DC–DC converters,” IEEE Transactions on Power Electronics, vol. 21, no. 6, pp. 1548–1555, Nov. 2006.
[4] M. H. Huang, P. C. Fan, and K. H. Chen, “Low-ripple and dualphase charge pump circuit regulated by switched-capacitor-based bandgap reference,” IEEE Transactions on Power Electronics, vol. 24, no. 5, pp. 1161–1172, May 2009. [5] S. C. Tan, M. Nur, S. Kiratipongvoot, S. Bronstein, Y. M. Lai, A. Ioinovici, and C. K. Tse, “Switched-capacitor converter configuration with low EMI obtained by interleaving and its large-signal modeling,” in Proc. IEEE Int. Symp. on Circuits and Systems 2009 (ISCAS 2009), pp. 1081–1084, May 2009. [6] S. Suzuki, I. Oota, N. Hara, and F. Ueno, “A new serial fix type switched-capacitor DC–DC converter with a low ripple inputcurrent,” in IEEE Power Electronics Specialists Conference 1998 (PESC 98), vol. 2, pp. 1517–1522, May 1998. [7] I. Chowdhury and D. Ma, “Design of reconfigurable and robust integrated SC power converter for self-powered energy-efficient devices,” IEEE Transactions on Industrial Electronics, vol. 56, no. 10, pp. 4018–4028, Oct. 2009. [8] R. Giral, L. Martinez-Salamero, and S. Singer, “Interleaved converters operation based on CMC,” IEEE Transactions on Power Electronics, vol. 14, no. 4, pp. 643–652, Jul. 1999. [9] S. C. Tan, S. Kiratipongvoot, S. Bronstein, A. Ioinovici, Y. M. Lai, and C. K. Tse, “Adaptive mixed on-time and switching frequency control of a system of interleaved switched-capacitor converters,” IEEE Transactions on Power Electronics, vol. 26, no. 2, pp. 364–380, Feb. 2011.
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