capacitors are included into the model. The converter performance functions, i.e. DC voltage ratio, efficiency, output voltage ripple, are expressed in terms of the ...
SWITCHED-CAPACITOR POWER SUPPLIES: DC VOLTAGE RATIO, EFFICIENCY, RIPPLE, REGULATION* Guangyong Zhu and Adrian Ioinovici** Department of Electrical Engineering, Hong Kong Polytechnic University, Hung Hom, Hong Kong **and Institute for Technological Education, 52 Golomb St., Holon 58 102, Israel
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Abstract A comprehensive and accurate steady-state analysis of a step-up DC-DC switched-capacitor power converter is performed. No approximations, such as average techniques, are invoked. Parasitic elements such as diode fonvard voltages, onresistances of transistors and equivalent-series resistances of capacitors are included into the model. The converter performance functions, i.e. DC voltage ratio, efficiency, output voltage ripple, are expressed in terms of the number of switched-capacitor stages, number of capacitors per stage, values of the capacitors and parasitic elements, switching frequency and load. Design criteria aiming at high efficiency, low ripple and achievable output voltage are formulated. Trade-offs between the efficiency requirement and good regulation capability are discussed.
I. MOTIVATION The switched-capacitor(SC)-based power electronic circuits have become very popular in the recent years, particularly for low-power applications [11-[3]. As they contain no magnetic devices (inductors or transformers), the SC converters feature a small size, light weight, give less EM1 problems, and are amenable to monolithic integration. But only a very few number of papers have been devoted to their analysis [4]-[6]. Usually, the available SC-converters have been approximately analyzed by using the average method [2]-[4]. As a result, important design parameters, such as the switching frequency, do not appear in the expressions of the performance functions. For the n-stage SC step-down converter considered in [4], the efficiency was found to be l y , with denoting the average output voltage and J f i the input voltage. The efficiency could not reach loo%, because V, had to be larger than n c for covering voltage drops on the semiconductor devices and ESRs of capacitors. The output voltage ripple could be reduced by increasing the switching frequency or the value of the capacitor placed in parallel with the load. Minimum ripple was obtained for a duty-cycle equal to 1/n. By taking into account the charging stage in which the energy was transferred from line to the capacitors in the SC circuit, the losses were calculated in [ 5 ] . The charge-up losses were calculated as an expression proportional to the difference between the input voltage and the initial capacitor
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voltage. It was erroneously stated that this formula was giving the minimum loss; in reality, if the capacitors are charged below the saturation level, there are less losses. The ideal voltage conversion ratio A4 for an unloaded stepup converter was calculated in [6]. It was shown that for a given number of capacitors k, the maximum step-up ratio was given by the kth Fibonacci number, while the bound on the number of switches required in converter was 3k-2. It was mentioned that the upper limit of the efficiency was decreasing with increasing load current, or decreasing capacitor value or switching frequency. At it can be noticed, the analysis of SC power converters is quite complex, and the first available results in literature do not always converge. Such a situation is expected in a starting stage of a developing theory, and gives motivation for more profound studies. This paper does not aim at accomplishing an exhaustive and general theory of SC converters, but at studying accurately a step-up structure, establishing its performance functions (voltage ratio, efficiency, ripple, regulation) and formulating trade-off design criteria. 11. MAIN ANALYSIS RESULTS, INTERPRETATION AND DESIGN TRADE-OFFS A typical step-up converter, presented in [3], is studied. Its structure and timing diagram of switches is shown in Fig. 1. The main operation phases are: a) charging n capacitors in parallel, from the input voltage V,, for the time dT,, where d is the duty ratio (O
