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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 2, MARCH 2008

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Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters Boris Axelrod, Yefim Berkovich, Member, IEEE, and Adrian Ioinovici, Fellow, IEEE

Abstract—A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: “step-down” and “step-up.” These blocks are inserted in classical converters: buck, boost, ´ uk, Zeta, Sepic. The “step-down” C- or L-switching buck–boost, C ´ uk, structures can be combined with the buck, buck–boost, C Zeta, Sepic converters in order to get a step-down function. When the active switch of the converter is on, the inductors in the L-switching blocks are charged in series or the capacitors in the C-switching blocks are discharged in parallel. When the active switch is off, the inductors in the L-switching blocks are discharged in parallel or the capacitors in the C-switching blocks are charged in series. The “step-up” C- or L-switching structures are combined ´ uk, Zeta, Sepic converters, to get with the boost, buck–boost, C a step-up function. The steady-state analysis of the new hybrid converters allows for determing their dc line-to-output voltage ratio. The gain formula shows that the hybrid converters are able to reduce/increase the line voltage more times than the original, classical converters. The proposed hybrid converters contain the same number of elements as the quadratic converters. Their performances (dc gain, voltage and current stresses on the active switch and diodes, currents through the inductors) are compared to those of the available quadratic converters. The superiority of the new, hybrid converters is mainly based on less energy in the magnetic field, leading to saving in the size and cost of the inductors, and less current stresses in the switching elements, leading to smaller conduction losses. Experimental results confirm the theoretical analysis. Index Terms—DC–DC hybrid converter, switched capacitor, switched inductor, steady-state analysis.

I. INTRODUCTION HE basic dc–dc converters, buck (whose ideal line-tois being the duty output voltage ratio cycle), boost , buck–boost, C´uk, Sepic, and can not provide a steep step-down, Zeta respectively step-up of the line voltage, as required by many modern applications. The today integrated circuits (ICs) are drawing their power from less than 5-V power supplies. It is estimated that the supply voltage for future microprocessors

T

Manuscript received August 15, 2005; revised January 13, 2006. This paper was presented in part at the International Symposium on Circuits and Systems, Kobe, Japan, May 23–26, 2005, and at the International Symposium on Circuits and Systems, Kos Island, Greece, May 21–24, 2006. This paper was recommended by Associate Editor M. K. Kazimierczuk. The authors are with Holon Institute of Technology, Holon 58102, Israel (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2008.916403

will decrease from 3.5 to 1 V, and even lower, in order to decrease the power loss of modern high power consumption CPUs [1]. Power supplies able to reduce the standard voltage of 12 V (or 48 V) to about 1 V are necessary [1]. When using telecom standard equipment for providing Internet services, the 48 V of the dc battery plant has to be boosted to a 380-V intermediate dc bus [3]. The high intensity discharge lamps (HID) for automobile head lamps require at their start-up the increase of the voltage from the battery’s 12 V to more then 100 V, at 35-W power [3]. In order to provide such a high voltage-conversion ratio , the basic converters would have to operate with an extreme value of the duty cycle, smaller than 0.1 in voltage-step-down converters, higher than 0.9 in voltage-step-up converters. An extreme duty cycle impairs the efficiency and imposes obstacles for the transient response [4]. Also, to generate such an extreme duty cycle, the control circuit must incorporate a very fast, expensive comparator. The extreme duty cycle may even cause malfunctions at high switching frequency due to the very short conduction time of the diode (self-driven transistor) in step-up converters, or of the active transistor in step-down converters. An obvious solution would be the use of transformers to get the desired voltage conversion ratio, like in forward or flyback converters. However, if the industrial application does not require for dc isolation, the use of a transformer would only increase the cost, the volume, and the losses. Moreover, a would increase the voltage large transformer turns ratio stress on the primary elements, impossing a heavy penalty on the efficiency. Voltage regulators have recently been developed for getting a sub-1-V supply voltage needed in microprocessors [5]. These converters, purposely designed for high load current and fast dynamics, are still in the development phase for answering the tough requirements. The switched-capacitor converters, proposed in the 1990’s, can provide any steep conversion ratio (a tutorial on these circuits can be found in [6]). However, they operate with a relatively low efficiency, and put challenges in the charging path of the capacitors. Use of cascade of converters for getting the desired voltage ratio is a no-solution in the today’s energy-saving conscious world, as this procedure implies an overall efficiency equal to the product of the efficiencies of each circuit. Quadratic converters can somehow alleviate the efficiency problem of cascade circuits by using a single driven transistor [7], [8], but they may present voltage or current overstresses.

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Starting from the switched-capacitor cells, switched inductorcapacitor circuits have been developed in [9]. A systematic, topological-based way of designing new structures of converters, was proposed for the first time in [10]. Using the duality between a switching-capacitor cell and a switchinginductor cell, as well as the duality between a voltage-driven converters and a current-driven one, new converters have been proposed. General topological formulas allowed for calculating the voltage ratio of each converter. However, [10] limits itself to power supplies containing maximum two switches, and are not necessarily providers of large conversion ratios. One structure allowing only a high step-up of the line, using those switches is given in [11], it contains a capacitor-diode voltage multiplier, similar to the multistage capacitor divider used in [12] for getting large step down voltage ratios. These singular schemes can provide large ratios, but they are accompanied by the inherent disadvantages of the switched-capacitor circuits [6]. A new approach is proposed in this paper: simple switching dual structures, formed by either two capacitors and 2–3 diodes, or two inductors and 2–3 diodes are defined. These circuit blocks can provide either a step-down of the input voltage or a step-up of it. They are inserted in classical buck, boost, buck–boost, C´ uk, Sepic, Zeta converters to provide new power supplies with a steep voltage conversion ratio. As their complexity in terms of circuit elements is comparable to that of the quadratic converters, their performances (voltage ratio, stresses, efficiency) will be compared to that of available quadratic circuits. The step-down and step-up switching-capacitor/switching inductor structures will be presented in Section II. The realization of new hybrid, transformerless dc–dc pulsewidth-modulated (PWM) converters will be aim of Section III, where an approximate dc analysis (losses neglected) will be performed to get the voltage conversion ratio for each new circuit. One of the new converters, the hybrid C´ uk converter, was implemented in the laboratory and the experimental results will be shown in Section IV. Section V will be devoted to a comparison of the new hybrid converters and with the quadratic ones. Conclusions will end the paper.

Fig. 1. Step-down basic switching structures.

II. SWITCHED CAPACITOR/SWITCHED INDUCTOR STEP-DOWN/STEP-UP STRUCTURES Fig. 1 presents three switching blocks formed by either two capacitors , and diodes [Fig. 1(a)] or two inductors , and diodes [Fig. 1 (b) and (c)]. These simple circuits can provide a step-down of the input voltage, and are denoted by and , respectively. Their switching topologies are shown in Fig. 2(a)–(c), respectively. For block , in the switching topology are charged in series from the input voltage, and in switching topology they are discharged in parallel. For blocks and , in topology are charged in series, in topology are discharged in parallel (like in a doubler-type rectifier). Fig. 3 presents there step-up structures. Their switching topologies are given in Fig. 4. Accordingly, for and , are charged in parallel during topology

Fig. 2. Switching topologies of the step-down structures. (a) Dn1. (b) Dn2. (c) Dn3.

and discharged in series during topology . For , during are charged in parallel, and during are discharged in series. It can be noted the duality between and , and respecand (Fig. 5) (the duality between switching-intively ductor and switching-capacitor cells was rigorously studied in [10] by using the graph theory).

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Fig. 3. Step-up basic switching structures. (a) Up1. (b) Up2. (c) Up3.

Fig. 5. Duality of basic switching blocks.

TABLE I POSSIBLE REALIZATIONS OF HYBRID CONVERTERS WITH C-/L-SWITCHING STRUCTURES

Fig. 4. Switching topologies of the step-up structures. (a) Up1. (b) Up2. (c) Up3.

For Fig. 6(c) and (d), voltage-second balances on can be written as

and

III. NEW HYBRID TRANSFORMERLESS DC–DC PWM CONVERTERS The proposed -switching and -switching circuits are in´ uk, Sepic, and Zeta serted in the basic buck, boost, buck–boost, C converters according to Table I.

giving (1)

A. Hybrid Buck Converter. By inserting the blocks and in a buck converter and, for adding an input inductor, , in order to diminish the input current ripple, the hybrid step-down converters shown in Figs. 6 and 7, respectively, are obtained. Their switching and are shown in topologies, Fig. 6(c) and (d) and Fig. 7(c) and (d), respectively.

where . For Fig. 7(c) and (d), a voltage-second balance on can be written as

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(or

)

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Fig. 6. Hybrid dc–dc PWM step-down converter with switching structure Dn1. (a) Block diagram (buck + Dn1 + L ). (b) Converter diagram. (c) Switching topology t (C ; C charged in series). (d) Switching topology t (C ; C discharged in parallel).

Fig. 7. Hybrid dc–dc PWM step-down converter with switching structure Dn2. (a) Block diagram (buck + Dn2). (b) Converter diagram. (c) Switching topology t . (d) Switching topology t .

giving the same conversion ratio as in (1), i.e., for both hybrid converters, the line is reduced times more than in a classical buck converter. It is worth noting that in the circuit in Fig. 7, the output inductor and diode of a classical buck are just replaced by the two inductors and diodes of , thus keeping the number of elements at a minimum. B. Hybrid Boost Converter The switching blocks and are inserted in a classical boost converter to give the hybrid step-up power supplies shown in Figs. 8 and 9, respectively. For reducing the output current ripple, an output inductor is inserted after . Voltagesecond balance on the inductors lead to

(2)

Fig. 8. Hybrid step-up converter with switching structure Up1.

i.e., a dc gain times bigger than that of a classical boost converter is obtained. The circuit in Fig. 8 was studied in detail in [13], where experimental results proved the expected performances. The input inductor in a classical boost converter was just replaced by the two inductors of in the new hybrid converter in Fig. 9.

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Fig. 12. Hybrid buck–boost converter in step-up mode using Up3. Fig. 9. Hybrid step-up converter with switching structure Up3.

´ uk converter in step-down mode using Dn1. Fig. 13. Hybrid C Fig. 10. Hybrid buck–boost converter in step-down mode.

´ uk converter in step-down mode using Dn2. Fig. 14. Hybrid C Fig. 11. Hybrid buck–boost converter in step-up mode using Up1.

C. Hybrid Buck–Boost Converter As shown in Table I, three buck–boost type hybrid converters can be obtained: for a step-down operation, is inserted as in Fig. 10. An input inductor is added to smooth the input current ripple (i.e., together with the capacitors of the block act as a low-pass filter). For a step-up operation, the switching , are inserted as in Figs. 11 and 12, respectively. blocks From the switching topologies of the converter shown in Fig. 10, one gets the voltage balance equations on and , which lead to

(3)

i.e., the double of the conversion ratio of the classical buck–boost converter. In the hybrid converter shown in Fig. 12, the inductor of a classical buck–boost converter is just replaced by the two inductors, of , thus minimizing the number of elements. D. Hybrid C´uk Converter Four new converters can be constructed by inserting either the step-down switching blocks , , or step-up switching structures , in a classical C´ uk converter (Figs. 13–16). In the converter shown in Fig. 13, the input capacitor of the classical C´ uk converter is not necessary, and in Fig. 14 the ´ uk converter are not output diode and inductor in a classical C necessary. The voltage-second balance equations on the inductors lead to

times more than i.e., the line-to-load ratio is reduced in a classical buck–boost converter. Similarly, for the converters in Figs. 11 and 12, one gets

(5)

(4)

i.e., a step-down two times steeper than that provided by the classical C´ uk converter is obtained.

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´ uk converter in step-up mode, using Up2. (a) block diagram Fig. 15. Hybrid C (C´ uk+Up2). (b) Converter diagram. (c) Switching topology t (L charged, C ;C discharged in series). (d) Switching topology t (L discharged, C ; C charged in parallel).

For the step-up converters, the input capacitor of a classical C´ uk converter becomes redundant if block is used (Fig. 15) and the input inductor becomes unnecessary if block is used (Fig. 16), thus saving one passive element. The voltage balances on and in Fig. 15 (c) and (d) gives

´ uk converter in step-up mode using Up3. (a) block diagram Fig. 16. Hybrid C ´ uk+Up3). (b) Converter diagram. (c) Switching topology t ; (L ; L (C charged in parallel, L charged). (d) Switching topology t ((L ; L discharged in series, L discharged).

The voltage balance on

and

in Fig. 16 (c) and (d) gives

resulting in

giving

(7)

(6)

i.e., a step-up verter is obtained.

´ uk contimes more than in a classical C

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Fig. 17. Hybrid Sepic converter in step-down mode using Dn1.

Fig. 18. Hybrid Sepic converter in step-down mode using Dn3.

The converters shown in Figs. 13 and 15 have been in detail analyzed, simulated and built as prototypes ([14] and [15], respectively). E. Hybrid Sepic Converter The step-down operation is obtained by inserting either (Fig. 17) or (Fig. 18) in a Sepic converter. In the circuit in Fig. 17, the input capacitor of a Sepic is unnecessary. In the circuit in Fig. 18, the output inductor and diode become unnecessary. For the first one, the input-to-output voltage ratio can be found as (8) i.e., one gets a step-down of the line times steeper than in a classical Sepic converter. For the second step-down hybrid Sepic converter, the voltageand written for the two switching second balances on stages are

Fig. 19. Hybrid Sepic converter in step-up mode using Up3. (a) block diagram (Sepic + Up3). (b) Converter diagram. (c) Switching topology t ; (L ; L charged in parallel, L charged). (d) Switching topology t ((L ; L discharged in series, L discharged).

that results in

(10)

giving (9) i.e., a step-down of the line voltage two times more pronounced than in a classical Sepic converter is obtained. The hybrid Sepic converter in the step-up mode is obtained (Fig. 19), the input inductor of a classical Sepic by using and gives becoming unnecessary. The voltage balance on

i.e., in a times more dc gain than that provided by a classical Sepic converter. The hybrid circuit shown in Fig. 17 was analyzed in detail in [14].

F. Hybrid Zeta Converter , one gets the stepAccordingly to Table I, by using down version, shown in Fig. 20. The output inductor and diode of a classical Zeta converter become superfluous in the new

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Fig. 20. Hybrid Zeta converter in step-down mode using Dn2.

Fig. 23. Experimental voltage waveforms of the hybrid C´ uk converter with

Dn1.

Fig. 21. Hybrid Zeta converter in step-up mode using Up2.

Fig. 24. Experimental voltage waveforms of the hybrid C´ uk converter with Up2.

IV. EXPERIMENTAL RESULTS The hybrid C´ uk converter with the step-down switching block (Fig. 13) was implemented in the laboratory. The experimental results are given in Fig. 23. The circuit parameters were as follows:

Fig. 22. Hybrid Zeta converter in step-up mode using Up3.

power supply. From the voltage balance equations on written for the two switching stages, one gets

and

(11) which shows a two times steeper reduction of the line compared with the performance of a classical Zeta converter. Two step-up hybrid Zeta power supplies are obtained by inserting (Fig. 21), in which case the input capacitor of a Zeta (Fig. 22), in which case converter becomes unnecessary, or the input inductor of a Zeta converter becomes superfluous. For the two converters, one gets, respectively (12) (13) Therefore, the new power supplies offer an output voltage double, and respectively times larger than that provided by a Zeta converter for the same line.

V

W

H

H

kHz. The switch was a MOSFET IRF 540 and , were diodes MBR 1640. The hybrid C´ uk converter with the step-up switching block Up2 (Fig. 15) and with the same circuit parameters and was also built and tested. The experimental results are given in Fig. 24, they agree with the theoretical analysis. V. COMPARISON OF PROPOSED CONVERTERS WITH QUADRATIC CONVERTERS I [7] As the number of elements and voltage stresses across the transistor and diodes are similar for the two types of converters, the comparison is focused on the total energy in the magnetic field of the inductors. For the same value of the inductors (i.e., the same current ripple), the currents through the inductors in the proposed converters are significantly lower than in the quadratic converters. In Fig. 25, the total (normalized) energy in inductors in the quadratic, classical and proposed hybrid converters is given. For all the proposed converters, the total energy in the magnetic field of the inductors is lower than that

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Fig. 25. Comparison of energies in inductors (normalized data): (a) between quadratic buck and boost converters, classical buck, boost, and buck–boost converters, ´ uk, Sepic, and Zeta and proposed hybrid buck, boost, and buck–boost converters, and (b) between quadratic converter with M = D =(1 D) [7] classical C converters, and hybrid proposed Cuk, Sepic, and Zeta converters.

0

in quadratic converters, and only slightly higher than that in classical converters. Regarding the current through the transistor (normalized with respect to the input current), , in the quadratic converters [7]: in the proposed hybrid converters, for example, ´ uk converter with or Sepic converter, with , or for C Zeta converter with for C´ uk converter with . The currents through the diodes are also smaller in the proposed converters than in the quadratic ones. The result is less conduction losses. For example, for the total conduction power loss in the switches of the quadratic converter Fig. 2, [7] is 8.88 W. In the corresponding converter in this paper in Fig. 7, the total conduction power loss is 2.96 W. VI. CONCLUSION A unified method for developing hybrid converters with a high step-down/up conversion voltage ratio was proposed. The topologies and formulas of the dc gain have been deducted, a detailed analysis and discussion of practical aspects of every one of the new converters being left for other papers. The new hybrid converters present a similar complexity with available quadratic converters (or one element less for some of the new converters), similar voltage stresses on the transistors and diodes, and similar conversion ratio as the quadratic converters (for some values of the duty cycle, some of the quadratic converters have the edge, for other values, the new hybrid converters have a steeper step-down/up dc voltage ratio). The main advantage of the new converters is their lower energy in the magnetic elements, what leads to weight, size and

cost saving for the inductors, and thus for the power supply, and less conduction losses, what leads to a better efficiency. REFERENCES [1] Intel Technology Symposium, Tech. Rep, Intel Corporation, Hillsboro, OR, 2001. [2] J. Wei, P. Xu, H. Wu, F. C. Jee, K. Yao, and M. Ye, “Comparison of three topology candidates for 12 V VRM,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), 2001, pp. 245–251. [3] L. Huber and M. M. Jovanovic´ , “A design approach for server power supplies for networking,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), 2000, vol. 2, pp. 1163–1169. [4] J. Wei, K. Yao, M. Xu, and F. C. Lee, “Applying transformer concept to nonisolated voltage regulators significantly improves the efficiency and transient response,” in Proc. IEEE Power Electron. Specialist Conf. (PESC), 2003, pp. 1599–1604. [5] J. Wie and F. C. Lee, “Two novel soft-switched high-frequency, highefficiency, non-isolated voltage regulators-the phase-shift buck converter and the matrix-transformer phase-buck converter,” IEEE Trans. Power Electron., vol. 20, no. 2, pp. 292–299, Mar. 2005. [6] A. Ioinovici, “Switched-capacitor power electronics circuits,” IEEE Circuits Syst. Mag., vol. 1, no. 1, pp. 37–42, Jan. 2001. ´ uk, “Switching converters with wide dc con[7] D. Maksimovic´ and S. C version range,” IEEE Trans. Power Electron., vol. 6, pp. 149–157, Jan. 1991. [8] V. Paceco, A. Nascimento, V. Farias, J. Viera, and L. Freitas, “A quadratic buck converter with lossless commutation,” IEEE Trans. Ind. Electron., vol. 47, pp. 264–271, Apr. 2001. [9] K. Kuwabara, E. Miyachika, and M. Kohsaka, “New switching regulators derived from switched-capacitor dc–dc converters,” IEICE, Tokyo, Japan, Tech. Report IEICE, PE88-5, 1988, pp. 31–37. [10] M. S. Makowski, “On topological assumptions on PWM converters—a reexamination,” in Proc. IEEE Power Electron. Specialist Conf. (PESC), 1993, pp. 141–147. ´ uk, “A three-switch high voltage con[11] P. Zhou, A. Pietkiewicz, and S. C verter,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), 1995, pp. 283–289.

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[12] R. D. Middlebrook, “Transformerless dc-to-dc converters with large conversion ratios,” IEEE Trans. Power Electron., vol. 3, no. 4, pp. 484–488, Oct. 1988. [13] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Transformerless dc–dc converters with a very high dc line-to-load voltage ratio,” J. Circuits, Syst. Comput., vol. 13, no. 3, pp. 467–475, Jun. 2004. [14] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Switched -capacitor (SC) switched-inductor (SL) structures for getting hybrid step-down ´ uk/Zeta/Sepic converters,” in Proc. IEEE Int. Symp. Circuits Syst. C (ISCAS), Kos Island, Greece, May 21–24, 2006, pp. 5063–5066. [15] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Hybrid switched-ca´ uk/Zeta/Sepic converters in step-up mode,” in Proc. IEEE pacitor C Int. Symp. Circuits Syst. (ISCAS), Kobe, Japan, May 23–26, 2005, pp. 1310–1313. Boris Axelrod was born in Ukraine in 1949. He received the M.S. and Ph.D. degrees in electrical engineering from the Technological Institute, Dnepropetrovsk, Ukraine, in 1972 and 1981, respectively. Until his emigration to Israel in 1990, he was a Senior Scientific Officer and a Docent of the Electrical Faculty, Technological Institute. In 1991 he joined the Department of Electrical and Electronics Engineering Holon Academic Institute of Technology, Holon, Israel, as a Researcher and Lecturer in Electronics. He has authored more than 30 published papers.

Yefim Berkovich (M’01) was born in Ukraine in 1937. He received the electrical engineer diploma from the Lvov Polytechnic Institute, Lvov, U.S.S.R., in 1959, the Candidate of Technical Sciences degree from the All-Union Electrotechnical Institute, Moscow, U.S.S.R., in 1975, and the Doctor of Technical Sciences degree from the Institute of Electrodynamics, Kiev, U.S.S.R., in 1990. During the period 1959–1966 he worked at the Special Design Bureau of Power Electronics, Mordovia, U.S.S.R., and during the period 1966–1996, with the Electrotechnical Works of Power Electronics, Tallinn, Estonia. From 1995 to 1996, he was also as Professor at Tallinn Polytechnic University, Tallinn, Estonia. Since 1997, he has been with in Academic Institute of Technology, Holon, Israel. His research interests include power electronics systems such a dc–dc, ac–dc and ac–ac converters. He has published over 100 papers in electrical engineering.

Adrian Ioinovici (M’84–SM’85–F’04) received the degree in electrical engineering and the DoctorEngineer degree from Polytechnic University, Iasi, Romania, in 1974 and 1981, respectively. In 1982, he joined the Holon Institute of Technology, Holon, Israel, where he is currently a Professor in the Electrical and Electronics Engineering Department. During 1990–1995 he was a Reader and then a Professor in the Electrical Engineering Department, Hong Kong Polytechnic University. His research interests are in simulation of power electronics circuits, switched-capacitor-based converters and inverters, soft-switching dc power supplies, and three-level converters. He is the author of the book Computer-Aided Analysis of Active Circuits (Marcel Dekker, 1990) and of the chapter “Power Electronics” in the Encyclopedia of Physical Science and Technology (Academic, 2001). He has published more than 100 papers in circuit theory and power electronics. Prof. Ioinovici has served a few terms as Chairman of the Technical Committee on Power Systems and Power Electronics of the IEEE Circuits and Systems Society (CAS-S). He served repetitive terms as an Associate Editor for Power Electronics of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS and presently serves as an Associate Editor for Power Electronics of the Journal of Circuits, Systems, and Computers. He has been an Overseas Advisor of the IEICE Transactions, Japan. He was chairman of the Israeli chapter of the IEEE CAS-S between 1985 and 1990. and served as General Chairman of the Conferences ISCSC’86, ISCSC’88 (Herzlya, Israel), SPEC’94 (Hong Kong), organized and chaired special sessions in Power Electronics at ISCAS’91, ISCAS’92, ISCAS’95, ISCAS’2000, and was a member of the Technical Program Committee at the Conferences ISCAS’91–ISCAS’95, ISCAS’06, PESC’92–PESC’95, track chairman at ISCAS’96, ISCAS’99- ISCAS’2005, co-chairman of the Special Session’s Committee at ISCAS’97, co-chairman of the Tutorial Committee at ISCAS’06, and designed co-chair, Special Session Committee at ISCAS’10,Paris. He was a Guest Editor of special issues of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS (August 1997 and August 2003) and a special issue on Power Electronics of Journal of Circuits, System and Computers (August 2003).

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