Pt/ZrO,/p-Si with a CET of 15.81% By comparing the lMHz C-V curve with theoretical C-V, an interface state density of less than. 10'1cm-2eV-' can be estimated.
Temperature Effect on the Reliability of Zr02 Gate Dielectric Deposited Directly on Silicon Wen-Jie Qi, Renee Nieh, Katsunori Onishi, Byoung Hun Lee, Laegu Kang, Yongjoo Jeon, Sundar Gopalan, and Jack C. Lee Microelectronics Research Center, The University of Texas at Austin, 10100 Bumet Road, Austin, TX 78758
AsSTRACT Temperature effect on the reliability of Zr02 gate dielectric has been presented. High effective voltage-ramp breakdown field was observed. The activation energy of temperature accelerated voltage-ramp breakdown calculated from Arrhenius plot indicates that the breakdown of ZrO2 is less sensitive to temperature than thermal oxide of similar electrical thickness. Zr02 films exhibit excellent TDDB characteristics with low charge trapping and no stress induced leakage current. The field and temperature acceleration for TDDB for the 15.8A capacitance equivalent oxide thickness (CET) Zr02 shows that the activation energy for TDDB falls into the range reported for oxide from 39A to I50A. It was found that the extrapolated 10-year lifetime operating voltage can be as high as -1.9V even at 15OOC based on the “log(tBD) vs E extrapolation model for a film with a CET of 15.8A.
INTRODUCTION As the scaling down process continues, the gate oxide thickness has to be scaled down accordingly in order to achieve adequate performance. Conventional thermal oxide will be phased out due to the excess leakage and reliability concerns. Moreover, it has been reported that even for 28A oxide, the temperature acceleration effect was severe enough to raise concem over the further scaling down of thermal oxide [l]. High dielectric constant (high-k) materials have been studied recently as promising replacements for thermal oxide as the gate dielectric in future ULSI devices. Superior electrical and reliability characteristics have been demonstrated for high-k materials such as Ti02 [2-31, Taz05 [4-51, ZrOz [6], and HfOz [7]. Because of the thermodynamic stability in contact with Si, Zr02 and HfD2 can be deposited directly on Si without the use of barrier layers. Temperature-accelerated dielectric breakdown has been reported for ultra thin gate oxides, showing that thinner oxides have a higher sensitivity to temperature [I$]. Although high-k films have exhibited excellent reliability at room temperature, the reliability at higher temperatures and the temperature acceleration effect may still be concems. Regarding TDDB, there are also some uncertainties on how to extrapolate the lifetime for high-k dielectric materials 191. In this paper, we will present our experimental results on the temperature effect on the reliability of Zr02 dielectric. Although temperature accelerated dielectric breakdown can also be seen with Zr02, the extrapolated 10 year-lifetime operating voltage can be as high as -1.9V, even at 150°C based on the “E-model”[lO-111 for a film with a capacitance equivalent oxide thickness (CET) of 15.8A. No enhanced trap generation occurred at high temperatures and no significant charge trapping occurred at both room temperature and high temperatures after constant voltage stressing conditions. The temperature acceleration study for TDDB and voltage-ramp breakdown indicates that the reliability of Zr02 is less sensitive to temperature than thermal oxide of similar electrical thickness.
RESULTS AND DISCUSSIONS It should be mentioned that in this study, we have concentrated on intrinsic reliability properties on small areas (5x 10’cm’). Defects and area effects are certainly other factors that need to be investigated. The voltage-ramp and time to breakdown were measured with the substrate in accumulation region (gate injection polarity for p-Si). Fig.1 illustrates high frequency C-V curves of the Pt/ZrO,/p-Si with a CET of 15.81% By comparing the lMHz C-V curve with theoretical C-V, an interface state density of less than 10’1cm-2eV-’can be estimated. Fig.2 shows J-V curve of this structure with the substrate in accumulation, very low leakage can be observed. The leakage is orders of magnitude lower than conventional oxide (-10‘zA/cm2 at -lV for an 18A SO2) with polysilicon gate [12]. However, this comparison is not strictly valid, since our gate stack uses Pt gate and the work function difference needs to be accounted for. 120,
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pt/Zr02/p-Si capacitors with an area of 5x10-’ cm2 were fabricated. P-type Si (100) 4 inch wafers with a resistivity of 0-7803-5860-0/00/$10.00 02000 IEEE
5-250cm were used as the substrate. The base vacuum of the sputtering chamber was about 2xlO”Torr. The target was a metal Zr (99.7% pure) of 4 inch diameter dimension. Zr02 films of about 65A were deposited using reactive magnetron sputtering at 3OOOC in an Ar + O2 ambient. The sputtering pressure was 4OmTorr with the O2 flow rate of 2sccm. The sputtering power was 400W with the target to substrate distance of around 30cm. This condition will give a dense film with low CET and leakage [6]. AAer sputtering, the films were annealed in a fumace in N2 ambient for 5min at 55OOC. Annealing in N2 can minimize the growth of interfacial layer by limiting the oxygen diffusion through the film. Pt was sputterdeposited and pattemed by lithography to form the top electrode. Pt was etched by aqua regia solution (HC1:H202:HN03=7:5:1at 75OC). AI was sputtered on the backside of the wafers to ensure a low contact resistance. Capacitance-Voltage (C-V) characteristics were measured using an HP 4194, and the CET was calculated from the accumulation capacitance of high-frequency C-V without accounting for the quantum mechanical effects. The leakage, voltage-ramp breakdown, time to breakdown, and charge-trapping characteristics were measured using an HF’4156 at temperatures from 25’C to 15OOC.
72
IEEE 00CH37059. 38mAnnualInternationalReliability Physics Symposium, San Jose, Califomia,2000
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Fig. 5. The effective dielectric voltage-ramp breakdown vs 100OlT. The activation energy determined from the slope of the curve is 17.1meV.
Fig.3 shows the typical effective voltage-ramp breakdown field (VBD/CET) distribution for Zr02 with a CET of 15.84 measured at 25OC and 150OC. The effective breakdown fields for these films are very high (>22MV/cm). A clear reduction in breakdown field at high temperature can be observed.
The temperature dependence of leakage current and reliability for Zr02 film has been characterized. Fig.6 shows the gate leakage dependence on operating temperatures. Weak temperature dependence of the leakage current can be seen for the whole voltage range. This trend suggests a tunneling-like mechanism. However, interestingly, a slightly higher temperature dependence of leakage at low voltage (-2V) can also be observed. TEM pictures reveal that for these structures, there is a thin interfacial layer between ZrOl and Si, possibly a silicate layer [6].This silicate layer is formed due to the excess oxygen in the film or the annealing furnace, and not by the reaction between Zr02 and Si. The silicate layer is important in reducing the interface state density. The physical thickness of the Zr02 film is about 65A. Given the wide bandgap of Zr02 (5.leV to 7.leV)[13-14], this low temperature coefficient of leakage indicates that the leakage current may be dominated by the Fowler-Nordheim tunneling mechanism. The reason why at low voltages (-2V) is still not clear. Fig.7 shows the charge trapping properties of Zr02 under constant voltage stress for both 25OC and 150°C. The leakage currents are fairly stable and a clear breakdown occurred for the device stressed at 15OOC in this time scale.
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The temperature effects on the reliability of Zr02 films have been studied. No enhanced trap generation is observed at elevated temperatures, and the conduction mechanism is tunnelinglike for this Zr02film. Low charge trapping and no significant stress induced leakage were observed for the Zr02 gate dielectric. Calculated from the effective voltage-ramp breakdown vs 1OOOK curve, the activation energy for ZrOz is much lower than thermal oxide of similar electrical thickness. The temperature and field acceleration of TDDB were also investigated. The thermal activation energy extrapolated from the Arrhenius plot of intrinsic tgD vs lOOO/T is about 0.8eV for the film with a CET of 15.8% which falls into the range reported for the thermal oxide from 39A to 150A. No obvious field dependence of the activation energy can be seen. "E model" was used to extrapolate the lifetime. Since the reliability of ZrOz is less sensitive to temperature than thermal oxide of similar electrical thickness, the extrapolated 10-year lifetime operating voltage can be as high as -1.95V, even at 15OOC based on the E model for Zr02film with a CET of 15.8A.
3.2
Fig. 11. Arrhenius plot of intrinsic time-to-breakdown for negative gate stress fields at different temperatures. The activation energy does not exhibit obvious electric field dependence for the range studied. Activation energy of 0.8eV can be calculated, which falls into the range reported for oxide from 39A to 150A. There have been controversies regarding accurate reliability projection in the ultra-thin oxide regime due to debate on the definition of breakdown, stress methods (e.g. constant current versus constant voltage stress), and lifetime extrapolation technique [10,18-191. But it is generally accepted that at low stress field E 75
ACKNOWLEDGEMENT This work is partially supported by SRCISEMATECH through the front-end research center.
REFERENCES
[16]
u71
R. Degraeve, N. Pangon, B. Kaczer, T. Nigam, G. Groesenken, A. Naem, “Temperature acceleration of oxide breakdown and its impact on ultra-thin oxide reliability”, 1999 Symposium on VLSI Technology of Technical Paper, p. 59. X. Guo, T. P. Ma, T. Tamagawa, and B. L. Halpem, “High quality ultra-thin Ti02/Si3N4gate dielectric for giga scale MOS technology”, IEDM Tech. Digest, p377, 1998 H. -S. Kim, S. A. Campbell, D. C. Gilmer, “Electrical reliability of metal-organic chemical vapor deposited high permittivity Ti02 dielectric metal-oxide-semiconductor field effect transistors”, Proceedings of IEEE IRPS, 1997, p. 90. H. F. Luan, B. Z . Wu, L. G. Kang, B. Y. Kim, R. Vrtis, D. Roberts, and D. L. Kwong, “Ultra thin high quality TazOS gate dielectric prepared by in-situ rapid thermal processing”, IEDM Tech. Digest, p.609, 1998 H. F. Luan, S. J. Lee, S. C. Song, Y. L. Mao, Y. Senzaki, D. Roberts, and D. L. Kwong, “High quality Ta205 gate dielectrics with T,,,,
