2010 International Conference On Computer Design And Appliations (ICCDA 2010)
The Design of USB Communication Interface System Based on TMS320F2812
Dong Wu, Lu Likun, Li Yeli, Liu Xiaoqing College of Information and Mechanical Engineering Beijing Institute of Graphic communication Beijing, China e-mail:
[email protected] Abstract-Control System needs high data communication with PC, but transfer speed of traditional serial port protocol RS232, RS485 is slow. A communication system is proposed, which uses high speed digital signal processor TMS320F2812 of TI as control and process core, and uses CY7C68001 of CYPRESS as USB2.0 interface chip, and uses FPGA chip XC3S400
of
XILINX
as
assistant
control
chip.
Detailed
hardware interface circuit principle graph and software design
Figure 1 Hardware Structure Block Diagram
method, program flow chart of TMS320F2812 are given.
[1 manufactured by TI company J, which is appropriative
Driver program and application program of PC are discussed,
fixed point digital signal processor in control domain. And
and high data communication is implemented.
its feathers have clock frequency of 150MHz, low power
Keywords-USB2.0; high speed communication; CY7C68001; TMS320F2812
accumulation operation mode, JTAG boundary scan support
INTRODUCTION
With control systems applied in various complicated industry domain, a great deal of signals and data need to be processed and calculated, so digital signal processors with high performance are used widely. Digital signal processors often need to transfer a great deal of data to personal computer, which will store, process further and analyze data. signal
protocols and
processor
needs
high-speed
transport
communication hardware for high-speed
communication with personal computer. RS232 protocol and RS485 protocol are often used in control system, but their speed commonly is 0.1152M b/ s, and this speed is very low. Design scheme proposed in this paper uses digital signal processor TMS320F2812 whose clock frequency is 150MHz, USB2.0
and
3.3V TMS320F2812 adopts harvard bus architecture, and has separate program space and data space, multiplication
I.
Digital
consumption, core voltage of 1.8V, 10 interface voltage of
communication
transport
protocol
chip
whose
CY7C68001, the
most
and
speed
is
to set breakpoints for online debugging and downloading program, 128Kx 16 bits flash and 18Kx 16 bits SARAM, math operation table, external memory interface, forty five peripheral interrupts and three external interrupts, and many advanced peripherals, such as two event managers(EVA, EV B), twelve bits ADC of 16 channels, three CPU timersof 32 bits, two serial communications interfaces (SCIs), one serial peripheral interface (SPI), one enhanced controller area network(eCAN), one multi-channel buffered serial port (McBSP) with SPI mode, up to fifty six programmable and multiplexed general purpose input/output (GPIO) pins. This control processor chip has strong operation and control ability, many peripherals and it can satisfY the demand of digital signal process in control system domain. B.
480Mb/ s. This scheme can completely satisfY the demand of control system communicating with personal computer at high speed. II.
of EX-FX2
series manufactured by Cypress company. CY7C6800 I chip is compliant totally with Universal Serial Bus Specification [3J , and can work at high speed mode (480 Mbps) or full
speed mode(12 Mbps). It integrates USB2.0 transceiver,
This scheme uses CY7C68001 as USB2.0 interface chip, with
[2J
2.0
HARDWARE DESIGN OF SYSTEM
and digital signal processor TMS320F2812
USB 2. 0 Inteiface Chip CY7C68001
USB interface chip uses CY7C68001
high
which implements physical layer protocol of USB 2.0, and USB2.0 serial interface engine which implements link layer protocol of USB 2.0. So it only needs external controller to
performance as main control chip. TMS320F2812 configures and controls CY7C68001 to
implement the application layer protocol of USB 2.0, which
transfer data with personal computer at high speed. FPGA
simplifies difficulty of software development. This chip
chip X3S400 is used as assistant control chip to help
adopts operation voltage of 3.3V, and its input and output
TMS320F2812 control CY7C68001, which is beneficial for
can be tolerant to 5V, and its package adopts SSOP package
system to expand further and add new functions. The
of 56 pins. It can support control endpoint 0 used to handle
hardware structure of this system is shown in Figure 1. A. Digital Signal Processor TMS320F2812
This system uses DSP chip TMS320F2812
978-1-4244-7164-51$26.00 © 2010 IEEE
requests of USB transfer. The endpointO operation registers mainly include EPOBUF, SETUP, and EPOBe. This chip has FIFO of 4K bytes, phase-locked loop, and FIFO interface. It has standard 8 bits or 16 bits external master
V4-420
Volume 4
2010 International Conference On Computer Design And Appliations (ICCDA 2010)
interface, which is synchronous or asynchronous. This
CY7C68001
interface is glueless to most standard microprocessors:
WAKEUP
DSPs, ASICs, and FPGAs. CY7C68001
has
two
external
interfaces,
READY
f--J f--+ FLAGB � FLAGC �
namely
FLAGA
command interface and FIFO data interface. Command interface is used to access internal registers of CY7C68001, endpoint buffer, descriptor, and configure, inquire work state of USB. Data interface of FIFO is used to access data of
four
FIFOs
of
lK
bytes.
The
USB
SLOE
transfers, interrupt data transfers, isochronous data transfers
SLRD
and control transfers. Bulk data transfer is used to transfer
FIFOADR[2 0
relatively large data quickly. Interrupt data transfer is used
XC3S400 chip is manufactured by Xilinx
XD[ 1 50] IXWE
�
XINT2_ADC
D[15 0]
Figure 2 Circuit Connection Block Diagram of TMS320F28 1 2, XC3S400 and CY7C6800 1
thousand system gates and up to 141 II 0s with the lowest cost per gate and lowest cost per 11 0 of any FPGA. The chip
XA[2 0] D[70]
INT#
[4l , and it uses
90nm process technology and staggered 1/0 pads up to 400
this
IXRD
SLWR
FPGA Chip XC3S400
of
FPGA XC3S400
;--
FD[15 0]
for timely but reliable delivery of data.
features
DSP TMS320F2812 IXZCSOANDI
FLAGD/CS
architecture
comprehends four basic types of data transfers: bulk data
C.
�
have
up
to
326MHz
operation
frequency, 56K bits of total distributed RAM, 288K bits of
IXRD, write control signal I WR, external interrupt 2 signal XINT2
of
TMS320F2812,
respectively
connect
chip
selection signal FLAGD/CS#, data bus FD[15:0], address
total block RAM, 16 multiplexers, up to 4 digital clock
bus FIFOADR[2:0], read signal SLRD, write signal SLWR,
managers. PROM chip XCF02S is used as configuration
interrupt signal INT# of CY7C68001, which is shown in
chip of XC3S400. It can endure 20,000 program and erase
figure 3. In this system, personal computer is designed as
cycles, and IEEE Standard 1149.11 1532 Boundary-Scan
USB host, and accordingly CY7C68001 is designed as USB
(JTAG) is supported for programming, prototyping, and
function device.
testing. D. Principle Diagram a/Circuit
In this system, power supply voltage needed by all chips is complex. TMS320F2812 needs two power voltages: 3.3V, 1.8V, and XC3S400 needs three power voltage: 3.3V, 2.5V, 1.2V, and CY7C68001 needs 3.3V power voltage. So, four types power voltages 3.3V, 2.5V, 1.8V, 1.2V are needed in this system. In this system switch supply is used to switch AC 220V to DC 5V TPS767D318 chip is used to switch 5V to 3.3V and 1.8V AMS1117-2.5V chip is used to switch 5V to 2.5V, and AMS1117-ADJ chip is used to switch 5V to 1.2V Circuit
connection
diagram
of
TMS320F2812,
XC3S400 and CY7C68001 is shown in Figure 2. In XC3S400, operation state signs READY, FLAGA, FLAGB, FLAGC of CY7C68001 forms a 8 bits state register. TMS320F2812 has 16 bits data bus, and only the lowest 8 bits data lines D[7:0] is used to connectXC3S400. The lowest three bits address bus, chip selection signal
IMPLEMENTATION AND DESIGN OF SYSTEM
III.
XZCSOANDl, read signal IXRD of TMS320F2812 are connected with XC3S400,
together for address decoding of this register. This register uses
one
address
of
SOFTWARE
and these signals are used
external
memory
zone
0
of
Soft design of this system includes C program of TMS320F2812, verilog program ofXC3S400, and program
TMS320fL812. Awakening pin WAKEUP of CY7C68001 is
of personal computer.
directly connected withXC3S400. Suspend work mode and
A. C Program o/TMS320F2812
normal work mode are controlled by XC3S400. Internal registers of CY7C68001 use five addresses of external memory zone 0 of TMS320F2812. XINTF zoneO and zonel chip selection signal IXZCSOANDl, data busXD[15:0], the lowest three address bus XA[2:0], read control signal
CCS3.1 software is adopted to develop program of TMS320F2812, and C language is adopted as program language.
C
initialization initialization
V4-42 I
program program program
of of of
TMS320F2812
includes
TMS320F2812
oneself,
CY7C68001,
sending
Volume 4
and
2010 International Conference On Computer Design And Appliations (ICCDA 2010)
personal computer through USB connecter line, personal
receiving data program of CY7C68001. 1) Initialization ofTMS320F28I2: Initialization program flow diagram of TMS320F2812 oneself is shown in figure 4.
system
sends
TMS320F2812
standard writes
request
to
descriptor
device,
into
then
CY7C68001.
CY7C68001 has 500 bytes of descriptor RAM used to store descriptor, and register DESC used to store length of descriptor. Firstly, descriptor
TMS320F2812
length
into
writes two bytes of
register
DESC;
secondly,
TMS320F2812 writes descriptor table into descriptor RAM through
command
port.
information (Vendor
ID
CY7C68001 and
Product
sends
ID)
device
to
personal
computer, and then personal computer loads relevant device driver program according to device information. After CY7C68001
Initialize External Memory Interface
receives
SET_CONFIGURATION
request
sent by personal computer, enumeration finishes, which will trigger ENUMOK interrupt of CY7C68001. 3) Sending and Receiving Data Program ofCY7C68001: In this system, all communication is initiated by personal computer,
and
bulk
data
transfer
mode
is
adopted.
CY7C68001 has total six interrupt sources, and when interrupt event occurs, CY7C68001 will trigger. external interrupt
2
of
TMS320F2812
through
INT
signal
TMS320F2812 reads command port and judges interrupt sources in interrupt service program of external interrupt 2,
Figure 4 Initialization Flow Diagram of TMS320F28 1 2
On circuit board, in-line crystal which has 4 pins i s used. The
clock
sign
generated
by
this
crystal
is
sent
and sets relevant interrupt flag. When
to
personal
computer
initiates
communication,
TMS320F2812 and then internal PLL of TMS320F2812
namely reading or writing data to CY7C68001, SETUP
multiplies this frequency to generate 150M clock signal,
interrupt of CY7C68001 will be triggered. TMS320F2812
which is used by TMS320F2812 CPU core.
judges and processes according to information of SETUP
External interrupt initialization flow of TMS320F2812
data packet, and data will be delivered into FIFO, or data
includes configurating XINT2CR register, enabling external
will be read from FIFO, to finish communication with
interrupt 2, configurating external interrupt 2 triggered on a
personal computer.
falling edge (high-to-low transition); setting interrupt service function name of external interrupt 2 asXINT2 ISR; setting IER register to enable PIE interrupt 1. TMS320F2812 uses peripheral interrupt expansion (PIE) block
to multiplex numerous interrupt sources into a
smaller set of interrupt inputs. All interrupts are divided into twelve groups, and external interrupt 2 is the fifth interrupt of first group. For
registers
addresses
of
of
CY7C68001
external
memory
and XC3S400
0
of
use
B.
ISE8.2
uses
FIF08,
and
command
interface
register
of
to
develop
program
is
as
used
of
program
address
Ox2005
of
external
memory
zone
0
of
bits of this register are shown in table 1. TABLE I MEANING OF ALL BITS OF STATE REGISTER OF XC3S400
I�
ADY
I �tA
GC
I ��A I ��A I GB
GA
c. Program of Personal Computer
multiplexed by GPIOE1, external interrupt 2 and starting
FIF06,
used
language
CY7C68001: READY, FLAGA, FLAGB, and FLAGC. All
many peripherals, and ports used by peripherals and GPIO
2) Initialization Program of CY7C68001:FIF02, FIF04,
is
verilog
TMS320F2812. This register includes state information of
appropriate read and write speed. TMS320F2812 integrates
of external interrupt 2 in this system.
and
language. In the FPGA, one register is established, and it
XTIMINGO register needs to be configured to assure
conversion of ADC, so this pin needs to be set as input pin
software
XC3S400,
TMS320F2812,
pins are multiplexed. The 151-th pin of TMS320F2812 is
Verilog Program ofXC3S400
Program of personal computer includes driver program of CY7C68001 and USB application program. WindowsXP operation system is used in personal computer, and driver program may adopt driver program example provided by Cypress Company. But this driver program example should
CY7C68001 respectively use addresses of TMS320F812:
be modified to assure that V ID and PID of driver program
Ox2000,
file are consistent to V ID and PID of CY7C68001 loaded
Ox2001,
Enumeration
of
Ox2002,
CY7C68001
Ox2003, has
two
and
Ox2004.
loading
modes:
automatic boot load mode through EEPROM and manual load mode through external master. This system adopts manual load mode through TMS320F2812. After this communication system is connected with
by TMS320F2812. Expansion name of driver program file is info Visual C++ 6.0 software is adopted to develop USB application program. The application program is based on single document structure to display and process data received from CY7C68001.
V4-422
Volume 4
2010 International Conference On Computer Design And Appliations (ICCDA 2010)
IV This
system
uses
RESULT
CY7C68001
REFERENCES
chip
as
USB
2.0
[I ]
Texas Instruments. TMS320F28 1 O, TMS320F28 1 1 , TMS320F28 1 2, TMS320C28 1 O, TMS320C28 1 1 ,TMS320C28 1 2 Digital Signal Processors Data Manual [EB/OLl [2009- 1 1 -ll http://focus.ti.Co m.cn/cn/litlds/symlink/tms320c28 1 2.pdf.
[2]
Cypress Semiconductor Corporation.CY7C6800 1 EZ-USB SX2™ High Speed USB Interface Device[EB/OL]. [2009-7-7]. http://ww w .cypress.com / ?doclD=1 7537.
[3]
USB Implementers Forum, Inc. USB 2.0 specification [EB/OLl [2009-7-7l http://www.usb.orgldevelopers/docs/usb20052709.zip. .
[4]
Xilinx Increment.Spartan-3 FPGA Family: Complete Data Sheet [EB/OLl [2006-5-26]. http://china.xilinx.com/supportldocumentatio n/data sheets/ds099.pdf
peripheral interface of TMS320F2812, and uses XC3S400 as expansion chip to make control system communicate with personal computer at very high speed. It overcomes shortcoming of slow speed of RS232 and RS485 protocol. This system has been
applied
successfully in control
equipment of high voltage frequency conversion. The result shows that this system can implement stable data transfer at high speed, and satisfying effect is gained. ACKNOWLEDGMENT
_
The authors would like to thank "Funding Project for Academic Human Resources Development in Institutions of Highter
Learning
Municipality
Under
the
Jurisdiction
(PXM2010_014223_09555
"Scientific
Research
Municipal
Commission
18000110027)"
for
Common of
Program
Education
sustentation
fund
of
Beijing and
7)" of
Beijing
(Grant
throughout
No. this
research project.
V4-423
Volume 4
