The electrical-interface quality of as-grown atomic-layer-deposited

CE: KR INSTITUTE OF PHYSICS PUBLISHING

SEMICONDUCTOR SCIENCE AND TECHNOLOGY

Semicond. Sci. Technol. 19 (2004) 1–8

PII: S0268-1242(04)78595-8

The electrical-interface quality of as-grown atomic-layer-deposited disordered HfO2 on p- and n-type silicon ˜ 1, H Cast´an1, H Garc´ıa1, J Barbolla1, K Kukli2, J Aarik3 S Duenas and A Aidla3 1

Departamento de Electricidad y Electr´onica, E.T.S.I. Telecomunicaci´on, Universidad de Valladolid, Campus Miguel Delibes, 47011 Valladolid, Spain 2 Institute of Experimental Physics and Technology, University of Tartu, T¨ahe 4, 51010 Tartu, Estonia 3 Institute of Physics, University of Tartu, T¨ahe 4, 51010 Tartu, Estonia E-mail: [email protected]

Received 31 March 2004 Published DD MMM 2004 Online at stacks.iop.org/SST/19/1 doi:10.1088/0268-1242/19/0/000

Abstract HfO2 thin films were atomic-layer deposited using different-precursor partial pressures and at different growth temperatures on n- and p-type silicon substrates. The effect of processing parameters and film thickness on the electrical quality of the oxide–semiconductor interface was studied. Deep-level-transient spectroscopy and conductance-transient techniques revealed 3–10 × 1011 cm−2 eV−1 interface trap densities, somewhat dependent on the processing conditions. Charge trapping took place mainly between the semiconductor and defects located at energies close to the majority-carrier-semiconductor-band edge.

1. Introduction The continuous scaling down of semiconductor integratedcircuit technology has forced the channel length and gatedielectric thickness of metal–oxide–semiconductor field-effect transistors (MOSFET) to shrink rapidly. The key element enabling this scaling down is the use of amorphous and thermally grown SiO2 as the gate dielectric. However, ultrathin SiO2 presents severe scaling limits, including issues such as band offset, interfacial structure, boron penetration and reliability [1–9]. Incorporating nitrogen into the oxide can greatly reduce boron diffusion. The concerns regarding high leakage currents, boron penetration and reliability of ultrathin SiO2 have led to materials’ structures such as oxynitrides and oxide/nitride stacks for near-term gatedielectric alternatives. These structures provide a slightly higher k value than SiO2 (pure Si3N4 has k ∼ 7) for reduced leakage, reduced boron penetration and better reliability characteristics [10–12]. Besides the encouraging results from a variety of deposition and growth techniques, scaling with oxynitrides/nitrides appears to be limited to an equivalent 0268-1242/04/000001+08$30.00

˚ [13]. In silicon-dioxide thickness, teq, of about 13 A fact, oxynitrides and oxide/nitride stack dielectrics represent current 3 year near-term solutions for scaling complementarymetal–oxide–semiconductor (CMOS) transistors [14]. High-k dielectric films are anticipated to be required as early as 2005 for certain applications with low-power and leakage-current specifications [15]. Many materials’ systems are currently under consideration as potential replacements for SiO2 as the gate-dielectric material for sub-0.1 µm CMOS technology. A substantial amount of investigation has gone into the group IVB metal oxides, specifically TiO2, ZrO2 and HfO2, because these systems have shown much promise in overall materials’ properties as candidates to replace SiO2. Work on ZrO2 and HfO2 was reported [16, 17] in the 1970 and 1980s for the purpose of optical coatings and dynamicrandom-access-memory (DRAM) applications. Both HfO2 and ZrO2 have high dielectric constants (20–25) and are thermally stable on Si, and therefore are potential gate dielectrics, but there are several concerns associated with these metal oxides. These oxides are ionic conductors, where O ions can diffuse through the oxides and leave vacancies

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behind, which then can act as traps and reliability concerns. Furthermore, both ZrO2 and HfO2 tend to crystallize at low temperatures [16], leading to polycrystalline films, with highleakage paths along grain boundaries and nonuniformities in the k value and in the film thickness. Low-temperature deposition and processing may be used in an attempt to prevent crystallization [18], but it is likely that the thermal cycles required in fabricating a transistor would cause the films to crystallize. The heterointerface formed between the ZrO2 or HfO2 and Si may also lead to a large amount of channelelectron-mobility degradation, which may be manifested only in transistors and not in capacitor structures. The results obtained on the ZrO2 and HfO2 metal–oxide systems widely described in the literature are important demonstrations of the ability to achieve low teq values with lower leakage currents than would be achieved using comparable SiO2 films [15]. The interface quality of these systems remains a critical issue, however, because as mentioned earlier, these materials are extremely susceptible to O diffusion and reaction at the channel interface. The ultimate device performance will depend heavily on the channel-carrier mobility, which in turn can easily be degraded by high interface-trap levels. A large hysteresis or shift in flat-band voltage for any gate dielectric will also result in unacceptable transistor-threshold-voltage shifts. Finally, these metal oxides have not yet demonstrated the required stability under the high temperatures required for CMOS processing, including dopant activation anneals up to 1050 ◦ C. Until this stability occurs, it should be considered a critical requirement for high-k dielectrics to withstand such high-temperature anneals. Among many possible deposition techniques for preparing ultrathin metal–oxide films, atomic-layer deposition (ALD) [19–22] is very promising because owing to its adsorption-controlled deposition mechanism, it can produce high-quality films with precise thickness control and nearperfect conformability. The ALD method enables one to obtain films of uniform thickness even in cases when substrates have very complex shape and the precursor fluxes vary significantly. At present, ALD-grown HfO2 is drawing significant attention for high permittivity gate-dielectric applications because it has been reported that HfO2 is compatible with conventional poly-Si without needing a barrier layer. The high-dielectric constant (>20) and the stability of its interface with silicon make HfO2 a promising candidate to replace SiO2 as a gate dielectric. It can still be suggested that crystallization processes [23], which take place when increasing film thickness and temperature, could influence the interface properties. In this work, we study the interface quality of ‘as fabricated’ HfO2 films grown by ALD at 300 ◦ C on p-type and at 450 ◦ C on n-type silicon substrates. As is known, in the case of the HfO2/Si interface there is a phase change during annealing of the as-deposited HfO2 in which an amorphous phase transforms to a polycrystalline film in the monoclinic phase. The samples studied here have not undergone any thermal annealing, so what we study here is the quality of strongly disordered HfO2/Si interfaces. Our results and conclusions could be compared with those obtained for annealed, and therefore, recrystallized HfO2 films on silicon. 2

Table 1. ALD process parameters and crystallinity of as-grown HfO2 films on Si substrates.

Sample

Deposition temperature (◦ C)

Number of cycles

H2O pressure (Pa)

P-87 P-83 P-41 P-37 N-220 N-77 N-26

300 300 300 300 450 450 450

100 100 50 50 200 100 50

12 3 12 3 6 6 6

Crystallinity Crystalline Crystalline Amorphous Amorphous Crystalline Crystalline Amorphous with traces of crystalline phase

Different thicknesses have been used in order to determine the physical location of defects. We use capacitance–voltage (C–V) and deep-level-transient spectroscopy (DLTS) to study the traps distribution at the interface and the conductance transient (G (t)) technique to determine the energy and geometrical profiles of electrically active defects at the insulator bulk.

2. Experimental details 2.1. Sample preparation The films were deposited on n- and p-type Si (100) in a flowtype ALD reactor. Before deposition, the substrates were etched in fluorhidric acid (HF) to remove the native oxide, and then rinsed in deionized water. The deposition process consisted of periodic exposures of the substrates to the vapour of HfCl4, with each of those exposures followed by purging with pure nitrogen (AGA, 99.999%), an exposure to the vapour H2O, and then another purging with the nitrogen gas. The exposure and purging periods each lasted 2 s. HfCl4 (Aldrich, 98%) was evaporated from a cell that was kept in the flow of the carrier gas (N2). The evaporation temperature was 140 ◦ C. The H2O vapour was generated from distilled and deionized water kept in an external vessel at room temperature. The water vapour was led to the reactor through a needle valve and a solenoid valve. The valves determined the flow rate and pulse times of the precursor. During the whole process, the partial pressure of the carrier (and purging) gas was 250 Pa in the reaction zone. Other parameters of the deposition processes used for growing the films are depicted in table 1. The extent of crystallization in the samples was checked using a reflection-high-energy electron-diffraction (RHEED) apparatus. Thickness of the samples was obtained by x-ray reflectivity (XRR) measurements, using either a Siemens D5000 x-ray diffractometer or a Bruker D8 Advance x-ray diffractometer. Reference films with 50–150 nm thickness were grown for elemental analysis using processing parameters identical to the samples subjected to electrical measurements. The composition was determined by timeof-flight elastic-recoil detection analysis (TOF-ERDA), where a 53 MeV 127I10+ beam was obtained from a 5 MV tandem accelerator (EGP-10-II).

ALD HfO2 on p- and n-type silicon Insulator

en = ω a en = ω b

C

Semiconductor

(b)

e n = ωc E F’

Q P B

Conductance

(a)

A

EF

2 ∆ω x

x c (t)

0

C B A “x C ” or “log(t)”

Figure 1. (a) Schematic band diagram of an insulator–semiconductor interface illustrating the capture of electrons by DIGS continuum states during a conductance transient. (b) General shape of the conductance transient.

2.2. Electrical-characterization set-up 2.2.1. Capacitance–voltage. One of the most-frequentlyused techniques to study the electrical properties of oxidesemiconductor interfaces is the capacitance–voltage (C–V) measurement. This has been carried out in order to determine insulator thickness, flat-band and threshold voltages, and fixed charge and interface-state density. The C–V measurements were carried out at room temperature and at 77 K, putting the sample in a light-tight, electrically shielded box. The measurement set-up involved a 1 MHz Boonton 72B capacitance meter and a Keithley 617 programmable electrometer. 2.2.2. DLTS. As for interface-trap measurement, it is well known that the C–V measurements tend to overestimate the interface-state density due to the influence of contributions such as charge and discharge of defects in the oxide during the C–V voltage ramps, band bending at the interface, influence of the interface at the gate side of the dielectric, contact resistances, and so on. Because a change of the Fermi-level position at the interface is induced by use of a voltage pulse, deep-level-transient spectroscopy must supply information regarding the interface states in the metal– insulator–semiconductor (MIS) type structures. Because this technique is time sensitive, it allows us to separate contributions with different time constants. In particular, this technique is more adequate to separate the fast contributions of interface states from the slow ones corresponding to defects in the dielectric bulk. DLTS measurements, between 77 and 300 K, were carried out using a 1 MHz Boonton 72B capacitance meter and a Hewlett-Packard HP54501 digital oscilloscope to record the capacitance transients. A Keithley 617 programmable electrometer is used together with a Hewlett-Packard HP214B pulse generator to introduce the quiescent bias and the filling pulse, respectively. To obtain the interface-trap distribution within the band gap, the bias voltage was chosen so that the MIS capacitor is just at the limit between depletion and weak inversion. Also, a 200 µs-wide-pulse large enough to drive the capacitors into accumulation is applied in order to fill all interface traps. The use of a digital oscilloscope allows us to record all the capacitance transients and, in this way, we can process the entire energy spectrum with only one temperature scan.

2.2.3. Conductance transients. C–V and DLTS techniques do not provide information about the defect spatial distribution. Recently, we have carried out conductance transient (G(t)) measurements to obtain quantitative information about the disordered induced gap states (DIGS) in atomic-layerdeposited hafnium and zirconium oxide thin films [24, 25]. In fact, from the experimental conductance transients we can obtain the DIGS state density as a function of the spatial distance to the interface and of the energy position in the band gap. The basis of this technique (shown in figure 1) is explained in our earlier paper [26]. From the experimental conductance transients, G(t), we can obtain the DIGS state density (NDIGS) as a function of the spatial distance to the interface (xc) and of the energy position, as follows [27]: NDIGS =


G/ω 0.4qA

(1)

xc (t) = xon ln(σ0 vth ns t) (2) 
xc (t) σ0 vth Nc − kT E  − E(xc , t) = Heff + kT ln (3) ω/1.98 xon  √ ¯ 2 2meff Heff is the tunnelling decay length, where xon = h σ0 is the carrier capture cross-section value for x = 0, vth is the carrier thermal velocity in the semiconductor, and ns is the free carrier density at the interface. Finally, Heff is the insulator–semiconductor energy barrier for minority carriers, and E means the carrier energy band edge at the insulator (Ec for electrons and Ev for holes). The experimental set-up of the conductance transient technique consists of an HP 33120A. Arbitrary waveform generator to apply the bias pulses and an EG&G 5206 two phase lock-in analyser to measure the conductance. An HP 54501A digitizing oscilloscope records the complete conductance transient. Samples were cooled in darkness from room temperature to 77 K at 0 bias in an Oxford DN1710 cryostat. An Oxford ITC 502 controller was used to keep constant temperature during the measurements.

3. Experimental results and discussion 3.1. Structure and composition RHEED measurements revealed no traces of crystallization in ˚ (P-41) thick films grown at 300 ◦ C, the 37 (P-37) and 41 A regardless of the water partial pressure applied. These films ˚ can be considered as amorphous. In the 83 (P-83) and 86.5 A 3

S Due˜nas et al

Table 2. Experimental results for Al/HfO2/p-Si, HfO2 grown at 300 ◦ C. Sample

Dielectric ˚ thickness (A)

Dit (×1010 cm−2 eV−1)

Maximum DIGS (×1010 cm−2 eV−1)

VFB 77 K (V)

VFB 300 K (V)

P-87 P-83 P-41 P-37

86.5 83 40.8 37.2

3–7 10 10 10–30

9 3 Not detected Not detected

−0.58 −0.88 −0.83 −0.92

−0.31 −0.56 −0.47 −0.51

(P-87) thick films grown using H2O partial pressure of 3 and 12 Pa, respectively, reflections from the electron diffraction appeared while the reflection to background intensity ratio was higher for the film grown using higher H2O pressure. The broad reflections did not allow the exact calculation of the plane distances and lattice parameters, which makes the estimation of the extent of crystallization only qualitative. However, the increased water pressure during the deposition slightly favoured the crystal growth. The phase identified was monoclinic with already distinguishable (−111) and (111) reflections. In addition, (001) orientation has appeared. In the films grown at 450 ◦ C using medium water pressure, the phase identified was also monoclinic with reflections sharpened (crystallites larger) due to the higher growth temperature and growing film thickness. TOF-ERDA has shown that reference films grown using identical process parameters at 300 ◦ C contained 65 ± 2 at.% oxygen, 32 ± 2 at.% hafnium, 0.4–0.6 ± 0.1 at.% chlorine, 2.3–1.9 ± 0.5 at.% hydrogen, 0.18–0.24 ± 0.05 at.% zirconium and 0.18–0.22 ± 0.05 at.% carbon. Thus the films were stoichiometric dioxides in the precision limits of ion beam analysis. The measurements in reference films have indicated the tendency for chlorine and hydrogen impurities to appear in higher (peak) amounts at the very oxide/substrate interface and film surfaces. The higher impurity concentrations at interfaces have earlier been also confirmed by SIMS measurements [28–30]. One can always expect somewhat higher impurity contents at interfaces either due to the incomplete surface reactions or migration of impurities to the substrate, naturally increasing the defect density. Our measurements also revealed that the impurity concentrations did not systematically depend on the water pressure varied between 3 and 12 Pa. Further, analysis on the films grown in the temperature range of 400–500 ◦ C has shown that such films contain 64– 65 ± 2 at.% oxygen, 34–35 ± 2 at.% hafnium, 0.22–0.26 ± 0.02 at.% zirconium and 0.13–0.30 ± 0.05 at.% carbon. Compared to the films grown at 300 ◦ C, the amount of chlorine has decreased close to the detection limits,