The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length J.M. Hergenrother', D. Monroe, F.P. Klemens, A. Kornblit, G.R. Weber, W.M. Mansfield, M.R. Baker, F.H. Baumann, K.J. Bolan, J.E. Bower, N.A. Ciampa, R.A. Cirelli, J.I. Colonell, D.J. Eaglesham, J. Frackoviak, H.J. Gossmann, M.L. Green, S.J. Hillenius, C.A. King, R.N. Kleiman, W.Y-C. Lai, J.T-C. Lee, R.C. Liu, H.L. Maynard, M.D. Morris, S-H.Oh2, C-S. Pai, C.S. Rafferty, J.M. Rosamilia, T.W. Sorsch, H-H. Vuong Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA Abstract
Device Fabrication
We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET. This is the first MOSFET ever built that combines 1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and 2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S / D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S / D capacitances. The drive current per pm of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. AN of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths ( L 3 have been demonstrated without advanced lithography.
The VRG process is outlined in Fig. 1. Arsenic was implanted into an epi Si wafer to form the device drain and a thin oxide diffusion barrier was deposited. A PSG/nitridel undoped oxide/nitride/PSG/nitride stack was deposited and a trench (or window) with nearly vertical sidewalls was etched through the entire stack (Fig. 2). The boron-doped epitaxial Si device channel was grown selectively in this trench (Fig.3) and the channel was planarized to the top nitride layer by CMP (Fig. 4). The undoped oxide film in the stack was a sacrificial layer whose thickness defined LG, the two phosphosilicate glass (PSG) layers were dopant sources used to form low-resistance, shallow, self-aligned S / D extensions by SSD of phosphorus, and the thin nitride layers between the undoped oxide and the dopant sources functioned as etch stops and as precision offset spacers. A polysilicon source landing pad was deposited, implanted with arsenic, and patterned. After this landing pad and the top PSG dopant source had been encased in nitride via spacer formation, the sacrificial oxide layer was removed selectively to expose the vertical Si channel (Fig. 5). A thin gate oxide was grown on the channel, and a phosphorous-doped, highly conformal a-Si gate was deposited and recrystallized. The TEM images of Fig. 6 show that the nearly perfect conformality of the a-Si deposition allowed it to fill the space underneath the top of the device without forming voids in the gate. The gate was patterned and backend processing was carried out.
Introduction The possible benefits of building vertical MOSFETs on the sidewalls of trenches or Si pillars have been recognized for at least a quarter century (1). Prominent among these benefits is a higher drive current per unit area of Si, the stacking of transistors and storage capacitors, and control of the gate or channel length without lithography. Many approaches (1-7) have been used to build these devices, but all vertical MOSFETs have lacked at least one of the following essential characteristics of the advanced planar transistor: high-quality gate oxide, sufficient gate length control, self-aligned S / D , and low parasitic capacitances. In this paper, we demonstrate a new device called the Vertical Replacement-Gate (VRG) MOSFET. This unique device retains these important planar MOSFET features, and in addition, provides precise gate length control without lithography, enhanced performance, and promising new opportunities for device design and continued scaling. In contrast to most vertical MOSFETs, the VRG-MOSFET is aimed not only ai memory applications but also at high-performance random logic applications.
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The VRG-nMOSFET doping geometry was measured by scanning capacitance microscopy (8). The vertical, selfaligned S / D extensions formed by SSD are clearly visible in the images of Figs. 7 and 8. The measured channel length (LcH) is 0 to 10 nm smaller than LG, suggesting very small gate overlaps. In the VRG process, the S / D extension lengths, as well as their overlaps with the gate, are controlled by film thicknesses. This allows one to precisely tune the overlap capacitances, and consequently, the capacitancelseries resistance tradeoff can be optimized asymmetrically for the S / D extensions. In certain applications, it may be advantageous to designate the top electrode as the device drain because of its very low substrate capacitance.
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0 1999 IEEE
IEDM 99-75
VRG Process and Device Features The key enabling element of the VRG process is its replacement-gate approach - this allows for the fabrication of high-quality gate oxides on a vertical { 100) Si surface whose length is defined by a film thickness. This flow should be mechanically scalable to sub-30 nm gate lengths with excellent control. Table 1 summarizes the important features of the VRG process along with some of the promising device design opportunities that it creates.
Table 1. VRG Process and Device Features Gate length controlled by film thickness High-quality gate oxide grown on epi Si channel Self-aligned S/D extensions formed by SSD Small parasitic capacitances Replacement-gateenables alternativegate stacks Device free from substrate - increases design flexibility Epi channel plus CMP opens door to 3D integration Vertical design enables graded channel doping Offset spacers, S / D exts. controlled by film thicknesses Short-channel performance independent of S/D depths Self-aligned top contact
VGS= VT- 0.4 V. The high channel doping (NA= 3.5e18/cm3) for the 100-nm and 50-nm devices limits their drive currents to 280 pA/pm and 180 pNpm, respectively. Fig. 13 shows data for a cylindrical, L G = 200 nm VRG-MOSFET. With a drive current per unit circumference of 440 pNpm, this device packs a lot of dnve into a small area of Si while maintaining excellent short-channel performance. In Figs. 10-13, floating body effects are minimal because the device body is tied to the source via a leaky junction; this junction is leaky because its depletion region extends to the polysilicordepi Si interface. Fig. 14 illustrates that the gate leakage current density for a VRG-MOSFET yield tester ( WC= 9060 pm) is comparable to that of a planar MOSFET with the same tox. This suggests that in terms of the gate leakage current, VRG-MOSFET gate oxides can be shrunk well below 28 A, and should be as scalable as those of planar MOSFETs.
Conclusions
M a d e with production tools, methods, materials
Device Electrical Performance In addition to providing precise gate length control and new device design opportunities,the VRG process improves upon the performance of advanced planar MOSFETs. The subthreshold and Io- VDs characteristics for a "rectangular" VRG-nMOSFET (see Fig. 9) with LG = 200 nm are shown in Fig.*lO.This device is a high-performance MOSFET with a 28 A physical gate oxide thickness and VT = 0.25 V. At an operating voltage of 2.5 V, the drive current of this device normalized by its coded width W, is 1.1 mA/pm - about 20% higher than that obtained at 2.5 V for a planar MOSFET with the same LCH,tox, and IOFF= 11 pNpm at VGS= VT- 0.5 V. The subthreshold swing s = 76 mV/decade, which is close to the ideal value (74 mV/decade) for a partially-depleted device with tox = 28 A and NA = 5e17/cm3. The saturation transconductance g,,,,,= 540 pS/pm, and at low VDS,p e p250 cm2Ns. CV measurements on very wide devices (yield testers with Wc = 20560 pm) indicate that the interface trap density at midgap is less than 5e10/cm2eV. Straightforward improvements in series resistance and oxide processing should allow us to approach the ideal two-fold drive enhancement obtained from having MOSFETs on both sides of the pillar. The 100-nm device of Fig. 11 exhibits excellent shortchannel performance at 1.5 V operation with DIBL = 30 mV, s = 90 mV/decade, and IOFF= 27 pNpm at VGS= VT- 0.5 V. The 50-nm VRG-MOSFET of Fig. 12 also exhibits respectable short-channel performance at .1.5 V with DIBL = 90 mV, s = 105 mvldecade, and IOFF= 13 &pm at
We have demonstrated a new MOSFET intended for hghperformance logic and memory applications in which 1) the gate length is controlled precisely through a film thickness, 2) the channel is self-alignedto the gate, and 3) a hgh-quality gate oxide is grown on a single-crystal Si channel. Our 200-nm devices drive 1.1 mA/pm at IOFF= 11 pA/pm, outperfonning advanced planar MOSFETs. The VRG process creates new opportunities for the continued scaling of the Si MOSFET. Using current manufacturing methods, materials, and tools, and without advanced lithography, the VRG process enables the fabrication of 50-nm devices that have excellent DC characteristics,small parasitic capacitances,and low-leakage gate oxides.
References T.J.Rodgm and J.D. Meindl, "VMOS:High-speed 7TL compatible MOS logic," J. Solid-State Circuits, vol. SC-9, p. 239, 1974. H. Takato er al., "High-performance CMOS surroundinggate transistor (SGT)for ultra high density LSIs," IEDM Tech. Dig., p. 222, 1988. S.Ma& et al., "Impact of a vertical @-shape transistor (V@T) cell for 1 Gbit DRAM and beyond," IEEE Trans. Elect. Dev., vol. 42, p. 21 17, 1995. H. Gossner, F. Wittmann, I. Eisele, T. Grabolla, and D. Behammer, "Vertical MOS technology with sub-0.1 pm channel lengths," Electron. Lett., vol. 31, p. 1394, 1995. C.P. Auth and J.D. Plummer, "Vertical, fully-depleted, sumunding gate MOSFETs on sub-0.1 pm thick silicon pillars," 54" Annual Device Research Con$ Tech. Dig., p. 108, 1996. K. De Meyer, M. Caymax, N. Collaert, R. Loo, and P. Verheyen, "The vertical heterojunction MOSFET," Thin Solid Film, vol. 336, p. 299, 1998. D. Klaes et al., "Selectively grown vertical Si MOS transistor with reduced overlap capacitances," Thin Solid Film, vol. 336, p. 306, 1998. R.N. Kleiman, M.L. OMalley, F.H. Baumann, J.P. Gamo, and G.L. Timp, "Junction delineation of 0.15 pm MOS devices using scanning capacitancemicroscopy," IEDM Tech. Dig., p. 691,1997.
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+ Implant Drain
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Fig. 1. Outline of the vertical replacement-gate(VRG) MOSFET front-end process flow.
Fig. 2. SEM image of a 0.24 pm trench etched in the oxidehitride stack.
Fig. 5. SEM image of an LC = 200 nm device immediately after the sacrificial gate layer has been removed by buffered HF.
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Fig. 3. SEM image of selective epitaxial growth of device channel (not yet complete).
Fig. 6. TEM image of a 100-nm VRG-MOSFET just before gate etch and a blow-up of the c@el region showing the polysilicon gate, the two nitride etch stops/offset spacers, and a conservative60 A gate oxide.
Fie. 7. Scannine cauacitance imaee of an Lr: = 200 nm VRGnMOSFET showing self-aligned source and drain extensions. "
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Fig. 4. TEM image of a 100-nm VRGMOSFET after channel growth and CMP.
Fig. 8. Scanning capacitance imaee of an LC = 50 nm device. The two sides of the Si pillar drive in parallel. I
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Fig. 12. Subthreshold and I r V m characteristics of a rectangular, LG = 50 nm VRG-nMOSFET with a 28 A gate oxide. This device was fabricated without advanced lithography using production tools, techniques,and materials.
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