Electrothermal Reduced Equivalents of Highly Integrated Electronic Systems with Multi-Port Positive Fraction Foster Expansion ( 2) (l) , Massimiliano de Magistris , Alessandro Magnani , l 3 ( ) ( ) Niccolo Rinaldi , Salvatore RUSSO
Vincenzo d' Alessandro
(ll
. . 2 D'lpart'lment 0 d'1 Ingegnena B'lOmed'lca, Elettromca e delle Telecomunicazioni, ( ) Dipartimento di Ingegneria Elettrica 3 Universita di Napoli FEDERICO II - Via Claudio 21, 80125 Napoli, Italy. ( ) Meridiana Italia S.r.l., via Sicilia 50, 00187 Roma. (1)
E-mails: {vindales.m.demagistris.alessandro.magnani.nirinald}@
[email protected] Abstract An effective strategy is proposed for the extraction of reduced electrical equivalents of dynamic thennal models for electronic systems, based on well-established electrical macro modeling techniques. Properly defined self-heating and mutual thermal impedances of the embedded active elements - preliminarily evaluated via 3-D thennal simulations - are reduced with passive identification methods, and equivalent electrical models are generated with a Foster multi-port synthesis. The technique is devised to detennine a compact thermal feedback network, in a fonn well suited for commercial circuit simulation environments, thus allowing for a coupled electrothermal analysis. Introduction Management of thermal issues is becoming crucial in modern electronics design, as long as high integration of components and sub-systems is pursued. It is indeed well recognized that over-heating adversely impacts both perfonnance and reliability of electronic systems, and it has to be faced at early design stage [1], [2]. Moreover, thennal modeling at system level involves different granularity levels, namely, component, chip, package, PCB. Hence, various methods have been proposed to derive efficient multi-scale and multi-source thermal dynamic models of devices and systems. An approach to electrothennal analysis is based on coupling a 3-D thermal FEM tool to a circuit simulator at each iteration point of the electrical simulation. On the other hand, it is a well-established result that any heat diffusion problem, once discretized, can be interpreted by means of an equivalent electrical network. The electrical equivalent is usually obtained through two main approaches, namely, (i) direct, yet computationally onerous, translation of the thermal problem, and (ii) low-order fitting of the behavior at the tenninals of interest with a simple pre-defined RC network [3]-[5]. The aforementioned strategies represent the extremes in the trade off between complexity and accuracy. For a system-level electrothermal simulation it is highly advisable that the considered models are reduced to minimum complexity for a prescribed accuracy, and easily integrated into standard circuit simulation tools. This goal can be pursued by classical order-reduction techniques. Discretized thermal equations can be indeed directly reduced in different ways [6], and again emphasis is given on the complete integration of the obtained model into the merely electrical problem. In this paper it is shown that, once an accurate thennal characterization of the system is available, a compact thennal
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equivalent multi-port network can be easily obtained through standard electrical macro-modeling techniques. In particular, it is found that the approach introduced in [7], based on convex constrained identification of positive real fractions for the extraction of guaranteed passive reduced electrical models, is very well suited for the extraction of electrical equivalents for the thennal feedback networks. The positive real fractions expansion reveals to be a complete representation of the thermal problem, due to the basic properties of the Fourier heat transfer equation. Therefore it represents a general alternative to other modeling techniques. Moreover, the properties of such an approach provide straightforward passive realizations as additional benefit, which turns into the direct possibility of integration into standard circuit simulation environments like SPICE as fully described in [8]. As a feasibility demonstration and case study, the proposed strategy is successfully applied to generate the thennal feedback network corresponding to an electronic system realized in a newly-developed ultra-compact stacking technology. '
Thermal impedances in electronic systems State-of-the-art electronic systems are often manufactured by integrating several chips within one package. When a chip is active, it dissipates power, which in turn entails a temperature rise. Besides, the individual chips (i.e., the heat sources) embedded in the module are thermally coupled, which means that the power generated by a given chip heats up also the surrounding ones. The concept of thermal impedance was introduced to model the dynamic thermal behavior (e.g., under pulse applications) of semiconductor elements (i.e., elementary cells in a complex transistor or chips embedded in a power module) [9]. In particular, the self-heating thermal impedance of a devicelchip at a given time instant t is defined as
ZTH () t
T (t) -TAMB
=
(1)
PD
where T(t) and TAMB are the device/Chip and ambient temperatures, respectively, and PD is the amplitude of the applied power step. The mutual thermal impedance between two deviceslchips designated as #1 and #2 is given by
11 ZTHm () t _
(t) -TAMB Pm
_
-
T2 (t) -TAMB
(2)
Pm
i.e., it represents the temperature rise over ambient of a heat source due to the activation of the other one, normalized to the power dissipated by the latter. It must be remarked that, in
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spite of the (unfortunate) nomenclature, the mutual impedance must be considered as an indicator of the thermal coupling degree between the devices/chips. Apart from the definition and its physical meaning, the concept of thermal impedance can be directly adopted as a basis for a description at the terminals of interest of the thermal problem, and can be easily regarded in terms of electrical equivalents. Thermal reduced equivalents extraction The extraction of an accurate reduced equivalent is crucial for any affordable system-level simulation. In our case, after the proper definition of self and mutual impedances of the most relevant regions for the thermal problem, it is performed by determining accurate (passive) rational approximations of the thermal impedance matrix, and its subsequent circuit synthesis. It is well known that RC networks suffice to represent the electrical equivalent network of diffusive (linear) thermal problems [4]. This is due to the parabolic nature of the Fourier heat transfer equation, whose eigenvalues are all real, and therefore the time constants in the dynamics are real as well. As a consequence, the transfer function can be modeled with an equivalent Foster network. For the general multi-port case, a complete frequency domain passive representation can be obtained from the Foster matrix expansion Np
Z(s}=
__ ... '1'__ '1'______ I
Np
= L� L �A" s s n=l - Pn n=l - Pn
(3)
where s is the complex variable, Np is the number of (necessarily real) poles, and the corresponding residues Rn=rrAn are MxM matrices that must be real, symmetric positive definite with the term al1=(An)l1 that can be fixed to 1 in the factorization of rn. In particular, due to thermal passivity properties, Z(s) is a Positive Real (PR) matrix. As long as each term of the expansion is assumed PR as well, all the above mentioned properties follow directly. As concerns the case of thermal impedance matrices, the identification of expansion (3) can be successfully pursued with standard passive identification techniques. To this purpose, we adopt the technique proposed in [8], which relies on a two-step process that can be described as follows. First, poles in (3) are identified via vector fitting (VF), and then the residues are obtained by formulating a convex optimization problem as (4) Rn � O where i denotes the thermal impedance data, and Rn?O is the passivity constraint for each term in (3) (� meaning "positive semi definite "). In our procedure the optimal solution is found with CVX software [10] that automatically transforms (4) into a semi definite programming problem and calls the relevant solution routines. The proposed technique is very accurate for the described problem because the expansion on which it is based is complete (being the dynamics described with real poles
26
only) and it guarantees the optimal residue evaluation for fixed poles. After determining the reduced thermal impedance matrix in the form of (3), a further diagonalization process (described in detail in [11]) can be applied to matrices Am leading to express each term in (3) as a sum of sub-terms of rank-l matrices. Those degenerate multi-ports correspond to elementary RC impedances blocks that, properly connected to ideal transformers of appropriate ratio, generate the original multi-port, thus leading to the generalized Foster compact scheme shown in figure 1, where N is the number of elementary blocks and M the number of ports [8].
1
l'
•
2
2'
,....
I I I I I I I I
.J�
M M'
FIGURE 1: Basic synthesis stamp for the Z matrix in the case of real poles (Re impedances).
Implementation and case study Multichip technology strategies are conceived and developed to significantly increase the integration density of semiconductor systems, thereby giving rise to smaller, lighter, and cheaper products. Nowadays, extremely dense modules are fabricated in ultra-thin chip stacking (UTCS) technology, which exploits the recent advances in thinning and attachment techniques. In UTCS systems, silicon chips thinned up to lO!lm are vertically integrated on the same (inactive) host silicon substrate, being the electrical insulation among them warranted by layers of benzocyclobutene (BCB), which benefits from good planarization properties [12], [13]. A 2chip UTCS module is sketched in figure 2, which illustrates (from the top): the thinned silicon chips containing the circuitry vertically insulated by BCB; an adhesive BCB layer to attach the buried (1 sl-level) thinned chip to the host silicon substrate; a Pb/Sn conductive grease that solders the substrate backside to the AIN package. In UTCS structures, the role played by thermal effects is exacerbated due to the low thermal conductivity of BCB (equal to 0.18 W/mK, about 800 times lower than that of silicon), which effectively counteracts the downward heat propagation from the power-dissipating circuitry regions to the board, assumed to be at ambient temperature. An extensive analysis of the thermal behavior of typical UTCS modules has been carried out in [14] by resorting to the heat transfer module of the commercial software package Comsol [15], which relies on the finite-element method (FEM).
rc1 2 -level active thinned silioon chip BGB
BGB
heat source
lt 1 _level active thinned silicon chip
FEM simulation
5 6.5x10 elements 5 9x10 degrees of freedom
BGB
adhesive BGB layer
host silicon substrate
!
PbISn
Thermal impedance vs. frequency
!
AIN PGA header
Np-650
vector fitting
FIGURE 2: Cross-section of a 2-chip module in UTCS technology.
(order reduction)
!
Np=11
positive definite residue matrices identification and synthesis
!
SPICE realization of generalized Foster equivalents
FIGURE 3: Comsol mesh of a 2-chip UTCS module.
The identification/synthesis procedure addressed in the previous sections was successfully applied to a 2-chip UTCS module. In this case, the self-heating and mutual thermal impedances associated to the active silicon chips are defined as in (1) and (2) where Tj and T2 were determined by averaging the temperature fields over the circuitry areas. The thermal impedances vs. time ZTHjI. ZTH22, and ZTHm were evaluated via 3-D thermal-only Comsol simulations by alternately activating the stacked silicon chips. Figure 3 shows the mesh of the 2-chip module, generated by exploiting the smart refinement strategies available in the recent software releases. The inherent system symmetries allowed considering only one quarter of the real structure, thus reducing the CPU/memory requirements needed to achieve a high level of accuracy; adiabatic conditions were employed to virtually restore the missing module portions. The mesh comprises about 6.5x105 elements (i.e., tetrahedra) and involves 9x105 degrees of freedom. The numerical simulation of a transient thermal impedance over 2000 logarithmically-spaced time instants was found to last nearly 7 hours on a workstation equipped with 2 hexacore 2.43 GHz CPUs and a 100 GB RAM. The full time-constant spectrum of the thermal impedances was then achieved by adopting the network identification by deconvolution approach [16], [17]. In particular, -650 RC time constants were evaluated at this stage. Subsequently, the considered model order reduction approach was adopted. After a reduced set of poles was identified with VF (11 poles were demonstrated to be enough to achieve a very good accuracy), the further step of passive residue matrices identification for the Foster expansion was taken. Lastly, with the final synthesis step, a dynamic thermal feedback circuit was determined for the structure under analysis. The whole procedure is schematically illustrated in figure 4.
FIGURE 4: Procedure adopted in this work.
Figure 5 depicts the time evolution of the thermal impedances, as obtained by (i) FEM simulations, (ii) the 11pole synthesis procedure described in this work, and (iii) a single-time-constant representation. An excellent agreement is achieved between numerical and II-pole data. It is noteworthy that the thermal impedance of the top (2nd) chip is higher than that of the buried (1 SI) one, which is closer to the board kept at ambient temperature.
2.5 ········
�
en Q) C) c ctl '0 Q) c..
2.0 1.5
E
1.0
Q;
0.5
Cii E ..c
I-
FEM
--- 1-pole fitting -- 11-pole fitting
.... ....- ...J 0.0�-��d:.�.......L-,,..........uL-=-,","",,""""""'L. 10-6 10-5 10-4 10-3 10-2 10-1 10° Time [sl FIGURE 5: Thermal impedances ZTHll, ZTH22, and ZTHm vs. time, as obtained by Comsol simulations (dotted lines), I-pole fitting (dashed), and ll-pole synthesized network (solid).
Figure 6 shows the results of a PSPICE [18] simulation performed on the synthesized feedback network; in particular, two power pulses with different durations and values were applied to the stacked thin silicon chips and the resulting temperature rises over ambient were determined.
27
�
14
10
"E 1 2 Q)
, .. "\
:0 E 10 ell
Qj
> 0 VI Q) VI ·c
�
:::J
Cil Qj
a.
E
Q)
I-
--
-p' ,
8
---
6
------------ -.
4
8 6
1s'-Ievel chip
------- 2nd-level chip "
4
\
2
"',
2
:s:
�
Q)
;:
0 a.
""0
�
a.
.(ij VI
.......
0
2
3
4
5
6
7
8
9
10
[9]
(5
.. .. _--.
0
[8]
0
[10]
Time [ms] FIGURE 6: Temperature rises over ambient and dissipated power pulses against time for the two stacked silicon chips, as obtained through a PSPICE simulation of the II-pole synthesized network.
Conclusion and perspectives In this work, we have shown an automated procedure suited to extract an accurate, yet compact thermal feedback network for electronic systems. The presented technique relies on (i) vector fitting and positive fraction identification for complexity order reduction and (ii) a generalized multi-port Foster synthesis with a limited number of components that lends itself to a direct implementation in standard circuit simulators. The proposed procedure has been successfully applied to describe the dynamic thermal behavior of a highly integrated multichip module. The use of the feedback network for a complete dynamic electrothermal simulation of complex circuits will be object of future and more extended work. References [1] M. Pedram and S. Nazarian, "Thermal modeling, analysis, and management in VLSI circuits: Principles and methods, " Proceedings of the IEEE, vol. 94, no. 8, pp. 1487-1501, 2006. [2] Y. Zhan, S. V. Kumar, and S. S. Sapatnekar, "Thermally aware design, " Foundations and Trends in Electronic Design Automation, vol. 2, no. 3, pp. 255-370, 2007. [3] D. T. Zweidinger, R. M. Fox, I. S. Brodsky, T. lung, and S.-G. Lee, "Thermal impedance extraction for bipolar transistors, " IEEE Trans. Electron Devices, vol. 43, no. 2, pp. 342-346, 1996. [4] L. Codecasa, "Canonical forms of one-port passive distributed thermal networks, " IEEE Trans. Components and Packaging Technologies, vol. 28, no. 1, pp. 5-13, 2005. [5] L. Codecasa, "Compact models of dynamic thermal networks with many heat sources, " IEEE Trans. Components and Packaging Technologies, vol. 30, no. 4, pp. 653-659, 2007. [6] D. Celo, Xiaoming Guo; P. K. Gunupudi, R. Khazaka, D. I. Walkey, T. Smy, and M. S. Nakhla, "The creation of compact thermal models of electronic components using model reduction, " IEEE Trans. Advanced Packaging, vol. 28, no. 2, pp. 240- 251, 2005. [7] L. De Tommasi, M. de Magistris, D. Deschrijver, and T. Dhaene, "An algorithm for direct identification of
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[11]
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[18]
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