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ABSTRACT. This study reports a new thermal management scheme for vertical Gallium Nitride (GaN) nanowire (NW) arrays. A new cooling design for.

THERMAL MANAGEMENT OF VERTICAL GALLIUM NITRIDE NANOWIRE ARRAYS: COOLING DESIGN AND TIP TEMPERATURE MEASUREMENT Jen-Hau Cheng, Dragos Seghete, Steven M. George, Ronggui Yang and Y.C. Lee University of Colorado at Boulder, Boulder, Colorado, USA Packaging has been studied for vertical nanowires, described in other publications. [3,4] So far, no one has ever addressed their thermal management issues. For effective cooling, we have found out that vertical NWs in fact provide us with a unique opportunity to access each hot device directly; such a direct access is beyond what we can accomplish with current semiconductor devices fabricated on substrates. As shown in figure 1, vertical GaN nanowire array offers an extremely high surface-to-volume ratio of each nanowire and a large space among the wires. A high thermal conductivity material can fill the space and provides an effective, direct cooling contact to each nanowire.

ABSTRACT This study reports a new thermal management scheme for vertical Gallium Nitride (GaN) nanowire (NW) arrays. A new cooling design for vertical NWs is developed by encapsulating NWs with electroplated copper. Numerical simulations show that the thermal performance of NW array could be significantly enhanced when encapsulated with high thermal conductivity materials. We have also developed a tip temperature measurement technique to characterize the tip temperature of vertical GaN NWs by using steady-state photoluminescence (PL) system. The cooling design and tip temperature measurement technique can be applied to various NW-based nanoelectronic and nanophotonic applications.


INTRODUCTION Thermal management has become a technical bottleneck in electronic and optoelectronic devices as the need for higher device integration density and power consumption have increased. Active devices, such as LEDs or ICs, were fabricated on a substrate by semiconductor manufacturing and usually thermal engineers were not allowed to design cooling solutions in it. After heat has spread from heat dissipation regions to the substrate, a variety of cooling solutions were carefully chosen to conduct heat from the substrate to environment and to the next cooling stage. Applying direct cooling to a hot spot or heat source is known to be the most effective cooling solution; however, in current planar device configurations it is a challenge to implement any cooling solution on hot devices directly.

GaN matrix Silicon

GaN matrix

Figure 1: c-axis-oriented GaN nanowire array grown by catalyst-free MBE on Silicon (111), inset: cross-sectional view of NW array. Scale bar: 1um for both.

COOLING DESIGN Finite element numerical simulation was conducted to study the heat spreading effect of a planar heat source on a substrate (case A), and a vertical GaN NW heat source on the substrate with/without encapsulations (case B-F). We assumed constant temperature boundary condition (BC) on the bottom side of the substrate and adiabatic BC to the rest. To make an equal heat source condition in both planar and NW configurations in simulation, heat source area is 4x106 (nm2) in all simulation cases. Detailed simulation conditions and results are listed in Table 1. Let’s consider a planar GaN LED and its P/N junction heat source with an area of 2 um × 2

Nanowires are promising fundamental building blocks for next-generation nanoelectronic and nanophotonic devices due to their extremely small dimensions and extraordinary electrical, optical properties. [1,2] Vertical nanowire arrays, compared to horizontal configuration, are desirable because they can reach an ultrahigh integration density at a device level without the need of additional wire rearrangement and assembly. With high integration density in a device, however, a much higher power density than that in the conventional planar devices is also expected.

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Table 1: Numerical simulation results to study heat spreading performance of planar/NW configurations Simulation case A. Heat source on GaN substrate (KGaN=130 W/mK) B. GaN NW on silicon substrate (KGaN NW= KSilicon=130 W/mK)

Cross-sectional schematic drawing (not to scale)

Thermal resistance (x104, K/W)

Temperature difference (ºC) Power: 50mW








Cu Si



Heat flux source GaN GaN NW heat source Si

C. BCB-encapsulated NW (KBCB=0.29 W/mK) D. Cu-encapsulatd NW without ALDs (KCu=400 W/mK) E. Cu-encapsulated NW with ALDs (one Al2O3 and one W) (KAl203=25, KW= 174 W/mK) F. Diamond-encapsulated NW with ALDs (one Al2O3 and one W) (KDiamond=1000 W/mK)

ALDs Cu Si

10nm each



20nm each



ALDs Diamond Si

10nm each



20nm each



deposition (ALD) process [3,6] was employed in our study to deposit high quality nano-scale electrical/dielectric interconnects. Assuming a thickness of 40 nm of ALD-alumina and W layer on a NW with copper encapsulation (case E), the thermal resistance can be only 0.09x104 (K/W). Most importantly, the thermal performance of Cuencapsulated NW with ALDs (20nm each in case E) is even 2 times better than the conventional planar configuration (case A). If CVD diamond is used (case F), we can reduce the thermal resistance further to 0.065x104 (K/W). With huge reduction in thermal resistance by filling high thermal conductivity materials, temperature difference between junction and substrate can substantially be reduced. Nano-scaled ALD multilayer enables us to encapsulate NW-based devices for effective electrical and dielectric interconnections while achieving excellent thermal contact with heat spreading copper. Overall device performance and efficiency can be enhanced while device is operating at low junction temperatures by the direct access to cool the active power dissipation region of vertical NW devices.

um (case A), fabricated at the center of a GaN substrate with a volume of 200 um x 200 um x 200 um (LxWxH). A heat flux source was uniformly applied to the P/N junction region and we obtained a junction-to-substrate thermal resistance of 0.18x104 (K/W). When a vertical GaN NW (200 nm x 200nm x 5um, LxWxH) without any encapsulation (case B) is used as the P/N junction and heat source of the LED on a silicon substrate same volume to GaN substrate, its thermal resistance, 62x104 (K/W), is 344 times higher than planar device configuration. Such a high resistance in a NW device without encapsulation is detrimental to device operation and limits its performance. If polymer such as Benzocyclobutene (BCB) is used as the filling material to encapsulate NW (case C), the thermal resistance drops from 62x104 to 29x104 (K/W). If copper is used (case D), the thermal resistance is reduced further to 0.068x104 (K/W). When filling the space with high thermal conductivity materials, the junction temperature and thermal resistance can be reduced by the merit of huge surface-to-volume ratio and effective heat spreading area of vertical NW. In device applications, however, interconnects are needed. High quality interconnects are important to provide reliable electrical connection and dielectric isolation for NW devices and it is important to study the thermal performance of NWs with interconnects and encapsulations. Atomic layer

COPPER-ENCAPSULATED NWS Copper encapsulation process has been developed to provide effective cooling for vertical GaN NW arrays. Our processing steps are illustrated as follows. It starts with c-axis GaN NWs grown on a silicon substrate using molecular beam epitaxy (MBE) method [6] (Fig.1). Examining by FESEM,


the averaged diameter and length of GaN NWs are 200nm and 5um, respectively. Each wire had to be electrically isolated but thermally conducted to copper. An extremely thin ALD-alumina (50nm) covered each wire with a pinhole free dielectric layer. This layer was then covered by ALDtungsten (40nm) for a good copper contact (Fig. 2a). Adhesion (Ti:30nm) and electroplating seed layers (Cu:250nm), were deposited on NWs by evaporation process as shown in Fig. 2b. At the end, the GaN NWs were fully encapsulated by copper after an electroplating process (Fig. 2c). Tips of NWs were exposed for the interconnect or other functional integration after copper etching process. (Fig. 2d). In addition, we noted that our lab can deposit a thin polymer layer by molecular layer deposition (MLD) [7] in between NW and encapsulation material for releasing the stress due to lattice or coefficient of thermal expansion (CTE) mismatch. W a b Al2O3 Ti/Cu


NWs with ALD-Al2O3 & W

very challenging to prove its effectiveness since there is no means to measure the temperatures of the nanowires. We have developed a tip temperature measurement technique for vertical GaN NWs using steady-state PL system. The semiconductor bandgap and its corresponding photoluminescence wavelength change with temperature as described by the well-known Varshni expression. [8] Our tip temperature measurement is based on this principle by measuring temperature dependence of PL peak wavelength. To obtain the temperature dependence of PL peak wavelength, copper-encapsulated NW sample was placed on a thermoelectric cooler (TEC) and excited with a continuous-wave (CW) HeCd laser operating at 325 nm (3.815eV). We changed the input power of the TEC (functioning as a heater) and recorded PL signals at different TEC temperatures. Surface temperatures of TEC were recorded by a K-type thermocouple (TC). The laser spot diameter is around 13um and average number of NWs shined by laser is 10. The schematic drawing of experimental setup is shown in figure 3. Thermocouple

Evaporation of Ti/Cu

Focus len

Mirrors 325 nm He-Cd Laser (3.815eV) Filter





Copper electroplating

NW sample


Wet etching to expose NWs 250nm




Figure 3: Experimental setup of steady-state PL measurement on copper-encapsulated NWs for tip temperature measurement.





Figure 2: Schematic drawings and corresponding experimental results of copper encapsulation process

TEMPERATURE MEASUREMENT The copper-encapsulated thermal management scheme is expected to be effective. However, it is


Figure 4 shows the temperature dependence of PL peak wavelength and data were fitted by a linear equation. Above 300K, temperature dependence of the energy bandgap in semiconductors is a linear relation and our results follow this relation. The fitted linear equation is used as a calibration equation for NW temperature measurement. Tip temperature of NWs can be determined by measuring its PL peak wavelength. Figure 5 shows the real-time PL measurements of copperencapsulated NWs. We recorded PL peak spectra with time intervals of 10 and 6 seconds when TEC was operated from 0V to 7.5 and 9V, respectively. After temperature equilibrium, we compared temperatures calibrated from the fitted linear equation and final temperature readings recorded by TC. Temperature differences of 1.9ºC and 1.8ºC were obtained when TEC was operated at 9V and 7.5V, respectively. To investigate the

temperature difference, we measured the temperature difference between one TC on TEC and another on NW sample at input voltage of TEC from 0 to 9V. We obtained an averaged temperature difference of 1.3 ºC, which is close to the temperature difference obtained from real-time PL measurements. In addition, we also had to know the location of the temperature measured. Since only tips of NWs without electroplated copper, PL and temperatures measured were solely from the NW tip regions.

that with the use of high thermal conductivity filling materials between NWs, thermal resistance is significantly reduced, and even lower than that in the conventional planar configuration. Nanoscaled ALD layers not only can provide reliable interconnects, but also is thermally effective. In addition, a novel tip temperature measurement technique has been developed successfully to characterize the thermal performance of vertical GaN NWs.

PL Peak Wavelength (nm)

ACKNOWLEDGEMENTS The studies conducted by the authors from the University of Colorado-Boulder are supported by the DARPA Center on Nanoscale Science and Technology for Integrated Micro/NanoElectromechanical Transducers (iMINT) funded by DARPAN/MEMS S&T Fundamentals Program (HR0011-06-1-0048)(Dr. D. L. Polla, Program Manager) and another DARPA grant for “Enabling System Integration Technologies for NW-Enabled LED Microsystems” (W31P4Q-08-1-0014). The authors also thank Dr. Kris Bertness for GaN nanowire samples, and Dr. John Schlager and Dr. Norman Sanford for the support on PL measurements.

Y=0.083*X + 360.6




362 20





Temperature (oC)

Figure 4: Temperature dependence of PL peak wavelength.

Calibrated Temperature (oC)


REFERENCES [1] Yu Huang et al., “Gallium Nitride Nanowire Nanodevices”, Nano Lett., 2002, 2 (2), 101-104. [2] E. Lai et al., “Vertical Nanowire Array-Based Light Emitting Diodes”, Nano Res (2008) 1: 123 128. [3] J. H. Cheng et al., “Atomic Layer Deposition Enabled Interconnect Technology for Vertical Nanowire Arrays”, submitted to Sensors and Actuators A. [4] E Latu-Romain et al., “A Generic Approach for Vertical Integration of Nanowires”, IEEE Nanotechnology 19 (2008) 345304. [5] S. M. George et al., “Surface Chemistry for Atomic Layer Growth,” Journal of Physical Chemistry, 100 (1996), pp. 13121-13131. [6] K. A. Bertness et al., “Catalyst-free growth of GaN nanowires”, Journal of Electronic Material, Vol. 35, No. 4, 2006.K. A. Bertness et al., J. Electronic Materials, 35 , (2006): 576-80. [7] Byunghoon Yoon et al., "Molecular Layer Deposition of Hybrid Organic!Inorganic Alucone Polymer Films Using a Three-Step ABC Reaction Sequence", Chem. Mater., 2009, 21 (22), pp 5365– 5374. [8] Y. P. Varshni, “Temperature dependence of the energy gap in semiconductors”, Physica 34 (1967) 149.



80.7ºC 60

Final readings of thermocouple: 90.7 (9V) and 78.9 ºC (7.5V)


0V, TEC is off. 20 0




Time (second)



Figure 5: Real-time PL measurement at TEC input voltage of 7.5 (diamond in black) and 9V (square in blue).

CONCLUSIONS This study has demonstrated a new thermal management scheme for vertical GaN NWs. Effective cooling by copper encapsulation for NWs has been developed. Simulation results show


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