Three-Level NPC-based Bidirectional PWM Converter Operation for High Availability/Power Quality Bipolar Dc Distribution Networks Joabel Moia, Marcelo Lobo Heldwein FEDERAL UNIVERSITY OF SANTA CATARINA (UFSC) Electrical Engineering Department, Power Electronics Institute (INEP) P.O. box: 5119 Florianopolis, SC, 88040-970, Brazil Phone: +55(48)3721-9204 Fax: +55(48)3234-5422 Email: [email protected] ; [email protected] URL: http//www.inep.ufsc.br

Acknowledgments The authors would like to thank Joselito Heerdt for the three-phase prototype employed in the experimental results.

Keywords , , , , .

Abstract This work proposes an operation strategy for a four-legs neutral point clamped converter (NPC) to be used in future bipolar dc distribution networks. The operation of the fourth leg with a three-level modulation is proposed to reduce the required inductance and switching losses. In addition, a proper control scheme based on a state space averaged model for the fourth NPC leg is introduced. This provides ripple free and balanced NPC partial dc-link voltages. The system is able to provide increased redundancy and improved dc voltage quality. Simulation and experimental results are presented to illustrate the operation of the 4-legs NPC with the proposed control and modulation scheme.

Introduction Modern power electronics applications related to electricity distribution typically demand technical characteristics such as low losses, volume, weight and electromagnetic (EM) emissions. However, aerospace [1], military [2] and premium energy quality industrial applications [3] especially require high energy availability. In this sense, power converters robustness and failure rate are of great concern. Direct current (dc) electricity distribution [4] can be used in such systems to improve operational aspects related to efficiency, copper mass and power quality. Power is typically available from alternating current (ac) sources, e.g. ac distribution networks and ac generators. Thus, solid state ac to dc conversion is used. Rectifiers are typically less reliable than their ac counterparts, i.e. power transformers. Therefore, power converters designed for high reliability are to be applied whenever high energy availability is sought. Redundancy is one of the main options to increase reliability and is considered in this work. Bipolar dc distribution networks [4, 5] can also be used to increase power delivery availability and efficiency, while maintaining voltage to earth under appropriate levels with the earthing of the intermediate conductor. Such networks require not only the ac to dc conversion, but also the regulation of the dc network voltages whenever unbalanced dc loads or distributed energy resources are present. Thus, bidirectional rectifiers that provide such features are the preferred option [6]. In this context, three-level topologies are well suited for applications where the dc-side unbalances are within specified boundaries

F S1

S2

vb

L ia L ib

Cb1

vc

L

Cc1

va N

ic

F

F

p

isp

F

DS1

DS2

S41 D1

Cs1

S42

L4

Ca1

iL4 C4

i cs1

Zlp

Pp

v p0

ilp

is0

S3

DS3

S4

DS4

D2

0

S43

Cs2

F

vDC

S44 F

F Ca2

isn

i cs2

Zln

Pn

iln

F

Fourth Leg

Cb2

v 0n

n Loads Distributed Generation

Cc2

Figure 1: NPC converter with an additional leg (fourth leg) including devices to reconfigure in case an NPC leg fails. The system is aimed at the generation of symmetrical dc bipolar distribution network voltages (v p0 and v0n ) in case of unbalanced loads (Zl p and Zln ) and/or distributed energy resources (Pp and Pn ). Sinusoidal ac grid currents (ia , ib and ic ) are sought. The fourth leg provides the balancing of the average levels of v p0 and v0n and also virtually eliminates their voltage ripple during normal operation.

[7]. The Neutral Point Clamped converter (NPC) is well accepted in industrial applications and is considered for the application at hand. However, many carrier-based modulation strategies for the NPC make use of zero axis signals to improve features such as losses and EM emissions. Such strategies typically generate low frequency components to flow in the dc-link intermediate point current is0 . The result is that the partial dc-link voltages v p0 and v0n present low frequency ripple. Large capacitors can be used to reduce voltage ripple. Another option is to employ modulation or control strategies that virtually eliminate the low voltage components [8]. However, most of these strategies do not generally apply when the following features are simultaneously required: bidirectional power flow, variable power factor, low implementation complexity and dc side power unbalance. The NPC is also intrinsically limited regarding unbalanced dc-link power and the generation of distortion free ac-side currents [6, 8]. Thus, the addition of a converter to the NPC dc-link can be advantageously used to reduce the limitations. This work uses the circuit configuration shown in Figure 1 to achieve the aimed high power quality operation with a redundant NPC leg (fourth leg) to improve reliability. This converter configuration was proposed in [9] to provide redundancy and reduce dc-link capacitors low frequency ripple. One limitation of the operation proposed in [9] is that the fourth leg is driven as a two-level inverter during normal operation. This increases switching losses and the current ripple in inductor L4 and, thus, leads to an increased inductor. Other circuit variations where proposed in [10] to reduce the switching losses associated with the two-level operation through soft-switching. However, this increases circuit complexity and components count. Another limitation within the control approach in [9] is that the variable used to control the fourth leg is the current iL4 . However, if a three-level scheme is adopted there will be current flowing through the clamping diodes of the fourth leg, which presents low frequency (LF) components. Thus, the elimination of the low frequency ripple across the dc-link capacitors is difficult to achieve. This work proposes the use of the estimated current for the complete fourth leg, i.e. including the clamping diodes LF current components, and the operation of the fourth leg with a three-level modulation strategy to reduce the required L4 inductance. Additionally, reducing iL4 leads to improved dynamics to eliminate the dc-link voltage ripple. Regarding fault operation, i.e. whenever one of the three-phase NPC legs fails, it is considered that the fourth NPC leg replaces the faulted leg. In this case, the use of a modulation strategy that is able to eliminate the dc-link voltage ripple is proposed to provide LF ripple free partial dc-link voltages.

NPC Fourth Leg Control Oriented Modeling The simplified schematic depicted in Figure 2(a) is used to analyse the NPC fourth leg circuit. From where, i4 = iL4 + iS04 .

(1)

Current iS04 is the switched current that flows through the fourth leg clamping diodes. It is defined as iS04 = −s04 iL4 ,

(2)

ia

isp

L4 iL4

Sp4 vb

L ia L ib

vc

L ic

va N

Three-Phase Three-Level is0 NPC Converter

S04 is04

p da

Cs1 vp0 ics1

ib *

Pp db

i4

Cs2

S n4

dc

Pn

isn

Ci4

ic

iln

*

abs

vDC

0 v0n

ics2

abs

ilp

4th Leg PWM

d p4

abs

d n4

v0n

n

d4

vp0

(a)

iL4 Cvp,n

i *4,avg

(b)

Figure 2: (a) Simplified schematic for the analysis of the NPC fourth leg operation; and, (b) proposed NPC 4th leg control block diagram for normal operation.

where s04 is the switching function (s04 =1 when S04 conducts or s04 =0 when it is switched off). The local average value of iS04 is defined with hiS04 i = −d04 iL4 ,

(3)

where d04 is S04 duty-cycle. It follows that hi4 i = iL4 (1 − d04 ) .

(4)

Finally, considering that d p4 +dn4 +d04 =1, hi4 i = iL4 (d p4 + dn4 ) .

(5)

Therefore, the estimation of hi4 i (hiˆ4 i) can be made with the duty-cycles of the fourth leg and the sensing of iL4 . This is used to balance and reduce the ripple on v p0 and v0n . Considering that the load currents are dc, i.e. il p = I¯l p and iln = I¯ln , the reference current for zero LF dc-link ripple and balanced voltages is hi4 i∗ = − his0 i − I¯l p + I¯ln = ia |da | + ib |db | + ic |dc | − I¯l p + I¯ln

(6)

where da , db , and dc are the NPC phase-legs modulation functions.

Dc-link Voltage Balance Control and Fourth Leg Redundant Operation Considering iL4 as the state to control, it follows that 1 d iL4 = (s p4 v p0 − sn4 v0n ) dt L4

(7)

Assuming v p0 = v0n = vDC /2 and Cs1 = Cs2 = Cs and only the local average values leads to d 1 vDC hiL i = (d p4 − dn4 ) dt 4 L4 2

(8)

Finally, defining d p4 = d4 − d04 /2 and dn4 = 1 − d4 − d04 /2 , vDC d hiL4 i = (2d4 − 1) dt 2L4

(9)

It is assumed that the average value of is0 within a mains period is null in the following. From the converter dc-side the currents at node 0 are dv0n dv p0 il p − iln = Cs − (10) dt dt

3-phase NPC modulation Clears fault signal

Dc-link voltage balance and ripple control

Yes

No

4 th NPC leg modulation No

3-phase NPC special modulation

No 4th NPC leg?

No

3-phase NPC leg?

Yes

Switch fails?

Waits for NPC leg maintenance

Maintenance ready?

Yes

Clears faulted leg

Yes

Figure 3: Four legs NPC operation flow diagram.

The average value of i4 (i4,avg ) also contributes to the definition of the dc-link voltages. Thus, d 1 v p0 = − i4,avg dt 2Cs

(11)

Assuming that currents is0 and the dc-side currents present slow dynamics, equation (11) can be used to design a dc-link voltage balance controller, while (9) to design the fourth leg current controller. The control block diagram in Figure 2(b) is, thus, proposed for normal operation, i.e., no fault condition. The redundant operation flow diagram is seen in Figure 3. During normal operation, the three legs of the NPC converter connected to the ac-side of the converter operate with any type of appropriate modulation. For instance, a discontinuous PWM scheme [11] can be advantageously used to reduce losses or a space vector modulation can be used to reduce common mode (CM) or differential mode (DM) emissions [11]. The fourth leg is driven with the scheme introduced in Figure 2(b). As soon as a semiconductor failure is sensed [12], that leg is cleared from the circuit. For instance, using the schemes introduced in [13]. The three-phase NPC is recomposed and the modulation scheme is changed to the one proposed in [8]. This operation guarantees sinusoidal currents and zero dc-link ripple under limited power unbalance conditions. Large unbalance will lead to distorted ac-side currents. Finally, after maintenance of the faulted leg, the conversion system can be restored to its normal operation with four NPC legs.

Simulation Results This section presents simulation results for a conversion system with the following parameters: 0.84 0.84

0.91 0.91

0.6 0.6

0.74 0.74

0.42 0.42

80

Imaginary axis (s-1)

60

0.22 0.22

vp0-v 0n 0.96 0.96

40 0.99 0.99

20 0

200

175

150

125

100

75

50

X X

25

-20

vp0+v0n

0.99 0.99

-40 -60

0.96 0.96

-80 0.84 0.84

0.91 0.91

-200

-150

0.74 0.74

-100 Real axis (s -1)

0.6 0.6

0.42 0.42

-50

0.22 0.22

0

Figure 4: Root locus plot of the designed control loops for the differential part of the dc-link partial voltages (v p0 − v0n ) and the common part (v p0 + v0n ).

• • • • • • • •

Rated power: S = 10 kVA; NPC switching frequency: fs,NPC = 30 kHz; 4th leg switching frequency: fs,4L = 30 kHz; Inductor L4 = 250 µH; Dc-link capacitors (each): Cs = 1 mF; Parcial dc-link voltages: v p0 = v0n = 380 V; Ac RMS Line voltage: vac,rms = 380 V; Mains frequency: fg = 50 Hz. (a)

30 20 10 [A] 0 -10 -20 -30

ia

ib

ic

(b)

30 20 10 [A] 0 -10 -20 -30

ib

ia

385

[A] 0

-5 (g)

v 0n

385

vp0

[V]

385 380

375

375

375

370

370 ics1

10

20

[A] 0

(h)

40 ics1

370 (k)

40

[A] 0

-20

-20

vp0

v 0n

20 ics1

[A] 0

-10

(l)

390

380

(d)

-10

380

20

5

390 [V]

-400 (j)

10

-40

v 0n

0 [V] -200

-40 (f)

400 200

-20

-20

vp0

ia

[A] 0

[A] 0

(c)

va

20

20

(i)

40

ic

40

is0

390 [V]

(e)

30 20 10 [A] 0 -10 -20 -30

-20

-40 0,02 s

-40 0,02 s

0,02 s

Figure 5: Simulation results: (a), (b), (c) and (d) show waveforms for a conventional 3-legs NPC with balanced dc loads. (e), (f), (g) and (h) show simulation results for the proposed system under completely unbalanced dc loads. (i), (j), (k) and (l) illustrate a purely reactive operation of the proposed system. (a)

6

400

(c)

vL4

200

4 [A]

[V] 0 2 -200 0 0

200

400 600 Frequency (Hz)

800

1000 (b)

6

-400 (d)

15 10

iL4

5

4

[A] 0

[A]

-5

2

-10 -15

0 0

200

400 600 Frequency (Hz)

800

1000

66,67us

Figure 6: FFT of the current flowing through capacitor Cs1 for rated power (10 kW): (a) conventional 3-legs NPC with balanced loads and sinusoidal PWM; (b) 4-legs NPC with the proposed operation strategy under complete dclink loads unbalance and unit power factor. The graphs show peak values. Voltage (c) and current (d) waveforms at the fourth NPC leg inductor L4 . These results are for balanced dc-link load power and without the voltage ripple compensation.

The fourth leg and dc-link voltage balance controllers are designed to provide a stable operation according to Figure 4. Two open loop root loci are shown, one where the differential part of the dc-link partial voltages is plotted and the second with the common part. The closed loop poles are placed at 4.0 Hz and 6.4 Hz for the differential control loop portion of the dc-link partial voltages and 182.0 Hz and 14.3 Hz for the common part. Figure 5 leftmost column shows simulation results for a conventional three legs NPC converter operating at unit power factor and feeding balanced dc loads using sinusoidal PWM. High quality ac currents are achieved, but high dc-link partial voltages ripple is observed due to the injection of a third harmonic current into the dc-link intermediate point. The central column Figure 5 presents the results for a conversion system according to the propositions of this work. The complete load, i.e. 10 kW is connected to one of the dc buses. The dc-link partial voltages are balanced and present very low ripple, while sinusoidal ac currents are achieved. Finally, the rightmost column in Figure 5 shows the waveforms for purely reactive operation of the proposed system, i.e., the system emulates a 10 kvar inductive three-phase balanced load. A comparison of the achieved results regarding the current spectrum in one of the dc-link capacitors is shown in Figure 6. Figure 6(a) presents the LF current spectrum for a dc-link capacitor for the conditions of Figure 5(a), i.e., conventional NPC operation without dc load unbalance. A high current value at the third harmonic frequency is observed. Figure 6(b) show the LF current components for the proposed 4-legs system under complete dc-link power unbalance. The LF components are virtually eliminated.

30 20

(a) ia

ilp

10 [A] 0 -10 -20 -30 (b) 10 0 [A] -10 -20

-30

-40

(c)

390 v 0n

385 [V] 380 375

vp0

370 (d)

40

ics1

20 [A] 0 -20 -40 0.40

0.45

0.50

0.55

0.60

0.65

0.70

Time(s)

Figure 7: Transient conditions simulation results: (a) phase a current ia and load current at the upper dc-link link il p ; (b) is0 and i4 local average values; (c) partial dc-link voltages; and (d) dc-link capacitor Cs1 current and its local average value. The proposed system operation starts at 0.5 s and a complete dc-link unbalance step is applied at 0.6 s.

(a)

100

500

va 250

50 [A] 0 -50 ia

-100 450

[A] 0

-250

-50

-500

-100 450 400

[V] 350

300 0.80

va

50

0 [V]

v 0n

400

(c)

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ia

v 0n

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vp0

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Time(s) (b)

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va

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v 0n

ia

v 0n

[V]

[V] 350

300 0.80

1.20

Time(s)

1.00

vp0

350

vp0

1.20

Time(s)

1.40

1.60

300 0.80

1.00

1.20

1.40

1.60

Time(s)

Figure 8: Simulation results for a symmetrical load steps transient behavior for phase a current ia , voltage va and partial dc-link voltages v p0 and v0n ; without the fourth leg operation: (a) 100% to 50%, (b) 50% to 100% and with the fourth leg operation: (c) 100% to 50%, (d) 50% to 100%.

The advantages of the three-level modulation scheme for the fourth NPC leg are observed on Figure 6. Figure 6(c) shows the voltage across L4 during two switching periods, where the three-level voltage is applied. The resulting current (cf. Figure 6(d)) presents lower ripple for a given local average value when compared to a two-level modulation scheme. Thus, lower inductance is necessary for a given current ripple specification. A second benefit is that the switching losses are reduced since the voltage transitions present half the value of the dc-link voltage. The optimal choice of the duty-cycle for the three-level NPC fourth leg operation should be made based on an adaptive scheme. In such an scheme, the following logic should be applied. The lower the unbalance and disturbance currents, the lower the duty-cycle. This leads to reduced fourth leg rms current values and ripple. For instance, at zero unbalance and disturbance currents, the duty-cycle could be 1/2 and, thus, no switching frequency ripple current would occur. In case of large disturbance or unbalance currents the limitation of the fourth leg duty-cycle would, in its turn, limits the achievable i4 current and its dynamic behavior. The transient behavior of the proposed conversion system operation is presented in Figure 7 for normal operation, i.e. with four legs. From 0.4 s to 0.5 s the fourth leg is off and there is no dc-link power unbalance. The converter operates with sinusoidal PWM and the dc-link voltage balance control is performed by the three-legs NPC. The local average value of is0 is high and not compensated. Thus, 10 V peak-to-peak is the resulting voltage ripple at the partial dc-link voltages. The dc-link capacitor Cs1 current presents, both, high and low (3rd harmonic) frequency components. From 0.5 s to 0.6 s the control system of the 4th leg starts and the four-legs system is able to minimize the low frequency components of the voltage across the dc-link capacitors. Slightly increased high frequency capacitor currents are observed. Finally, a 5 kW power step is applied to the dc-link causing a complete unbalance, i.e., one of the dc-link buses assumes the full load (10 kW). The proposed system is able to balance the dc-link partial voltages and keep the voltage ripple at negligible levels.

The Figure 8 show the simulation results for a symmetrical load steps transient behavior without the fourth leg operation (cf. Figure 8(a) and Figure 8(b)) and with the fourth leg operation (cf. Figure 8(c) and Figure 8(d)). Figure 8(a) and Figure 8(c) show 100% to 50% symmetrical load steps. Figure 8(b) and Figure 8(d) show 50% to 100% symmetrical load steps. The partial dc-link ripple cancellation achieves the same transient behavior applying the fourth leg comparing to the operation of three legs NPC transient behavior.

Experimental Results A lab prototype with the same specifications as given in simulation results section is currently being built to verify the proposed system operation. Preliminary results are presented from a three-phase three-level three-legs T-Type converter prototype according to Figure 9 [8] . The results shown in Figure 10 were obtained with the operation of only three-legs. Figure 10(a) employs a conventional SPWM scheme, while Figure 10(b) uses the modulation strategy introduced in [8], i.e., partial dc-link ripple cancellation emulating the operation under one faulted leg. The dc-link ripple cancellation modulation is able to drastically reduce the partial dc-link voltage ripple. In addition, the acside inductor current at phase a maximum ripple is lower for the dc-link cancellation scheme. Load steps transient behavior are shown in Figure 11 for a conventional SPWM scheme (cf. Figure 11(a) and Figure 11(b)) and for the employed partial dc-link cancellation scheme (cf. Figure 11(c) and Figure 11(d)). Figure 11(a) and Figure 11(c) show 100% to 50% symmetrical load steps. Figure 11(b) and Figure 11(d) show 50% to 100% symmetrical load steps. The partial dc-link ripple cancellation achieves the same transient behavior as the conventional SPWM one. Load disturbance rejection with the ripple cancellation scheme is appropriate for both, differential v p0 − v0n and common v p0 + v0n parts of the dc-link voltages. Ac-side inductors

Ac-side inductor Gate drivers

Bus Capacitor

Bus Capacitor

Heatsink 30.0 cm

Figure 9: Three legs three-level converter prototype. A T-Type converter is implemented [8].

va

va

ia

ia

vp0

v 0n

(a)

v 0n

vp0

(b)

Figure 10: Experimental results for the three-legs NPC operation without the special modulation (a) and with it (b). Load power: (2.1 + 2.1) kW and operation as a three-phase unit power factor rectifier.

v 0n vp0

v 0n vp0

va

va

ia

ia

(a)

(c)

v 0n vp0

v 0n vp0

va

va

ia

ia

(b)

(d)

Figure 11: Experimental results for a symmetrical load steps transient behavior operation for phase a current ia , voltage va and partial dc-link voltages v p0 and v0n ; without the special modulation: (a) shows 100% to 50%, (b) shows 50% to 100% and employed partial dc-link cancellation scheme [8]: (c) shows 100% to 50%, (d) shows 50% to 100%.

Conclusions This work presented a novel operation strategy for a four-legs NPC converter to be applied in future high quality bipolar dc distribution networks. The fourth leg is used to reduce voltage ripple and balance the partial dc-link voltages in the presence of load unbalance during normal converter operation. The proposed strategy is based on the three-level modulation of the fourth leg and an appropriate control strategy, which considers the control of the complete fourth leg current. The control oriented modeling of the fourth leg was presented in order to provide the means for the current control. The three-level operation leads to the reduction of switching losses and required inductance value when compared to state-of-the-art strategies. Simulation and experimental results verify the feasibility of the proposed strategy.

References [1] J. A. Rosero, J. A. Ortega, E. Aldabas, and L. Romeral, ”Moving towards a more electric aircraft,” IEEE Aerospace and Electronic Systems Magazine, vol. 22, pp. 3-9, 2007. [2] J. G. Ciezki and R. W. Ashton, ”Selection and stability issues associated with a navy shipboard DC zonal electric distribution system,” IEEE Transactions on Power Delivery, vol. 15, pp. 665-669, 2000.

[3] A. Domijan, Jr., A. Montenegro, A. J. F. Keri, and K. E. Mattern, ”Simulation study of the world’s first distributed premium power quality park,” IEEE Transactions on Power Delivery, vol. 20, pp. 1483-1492, 2005. [4] H. Kakigano, Y. Miura, T. Ise, and R. Uchida, ”DC Micro-grid for Super High Quality Distribution: System Configuration and Control of Distributed Generations and Energy Storage Devices,” in 37th IEEE Power Electronics Specialists Conference, 2006, pp. 1-7. [5] J. Lago, J. Moia, and M. L. Heldwein, ”Evaluation of power converters to implement bipolar DC active distribution networks: DC-DC converters,” in IEEE Energy Conversion Congress and Exposition (ECCE), 2011, pp. 985-990. [6] J. Moia, J. Lago, A. J. Perin, and M. L. Heldwein, ”Comparison of three-phase PWM rectifiers to interface Ac grids and bipolar Dc active distribution networks,” in 3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG), 2012, pp. 221-228. [7] N. Celanovic and D. Boroyevich, ”A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters,” IEEE Transactions on Power Electronics, vol. 15, pp. 242-249, 2000. [8] J. Moia, A. J. Perin, and M. L. Heldwein, ”Three-level/-phase PWM converters DC-link voltages ripple reduction technique in the alpha/beta reference frame,” in 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2012, pp. 740-747. [9] S. Ceballos, J. Pou, E. Robles, J. Zaragoza, P. Ibanez, and J. L. Martin, ”Fault-tolerant hybrid four-leg multilevel converter,” in European Conference on Power Electronics and Applications, 2007, pp. 1-9. [10] S. Ceballos, J. Pou, J. Zaragoza, E. Robles, J. L. Villate, and J. L. Martin, ”Fault-Tolerant Neutral-PointClamped Converter Solutions Based on Including a Fourth Resonant Leg,” IEEE Transactions on Industrial Electronics, vol. 58, pp. 2293-2303, 2011. [11] T. Bruckner and D. G. Holmes, ”Optimal pulse-width modulation for three-level inverters,” IEEE Transactions on Power Electronics, vol. 20, pp. 82-89, 2005. [12] P. Fazio, G. Maragliano, M. Marchesoni, and G. Parodi, ”A new fault detection method for NPC converters,” in Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on, 2011, pp. 1-10. [13] E. R. da Silva, W. S. Lima, A. S. de Oliveira, C. B. Jacobina, and H. Razik, ”Detection and compensation of switch faults in a three level inverter,” in Power Electronics Specialists Conference, 2006. PESC ’06. 37th IEEE, 2006, pp. 1-7.

Acknowledgments The authors would like to thank Joselito Heerdt for the three-phase prototype employed in the experimental results.

Keywords , , , , .

Abstract This work proposes an operation strategy for a four-legs neutral point clamped converter (NPC) to be used in future bipolar dc distribution networks. The operation of the fourth leg with a three-level modulation is proposed to reduce the required inductance and switching losses. In addition, a proper control scheme based on a state space averaged model for the fourth NPC leg is introduced. This provides ripple free and balanced NPC partial dc-link voltages. The system is able to provide increased redundancy and improved dc voltage quality. Simulation and experimental results are presented to illustrate the operation of the 4-legs NPC with the proposed control and modulation scheme.

Introduction Modern power electronics applications related to electricity distribution typically demand technical characteristics such as low losses, volume, weight and electromagnetic (EM) emissions. However, aerospace [1], military [2] and premium energy quality industrial applications [3] especially require high energy availability. In this sense, power converters robustness and failure rate are of great concern. Direct current (dc) electricity distribution [4] can be used in such systems to improve operational aspects related to efficiency, copper mass and power quality. Power is typically available from alternating current (ac) sources, e.g. ac distribution networks and ac generators. Thus, solid state ac to dc conversion is used. Rectifiers are typically less reliable than their ac counterparts, i.e. power transformers. Therefore, power converters designed for high reliability are to be applied whenever high energy availability is sought. Redundancy is one of the main options to increase reliability and is considered in this work. Bipolar dc distribution networks [4, 5] can also be used to increase power delivery availability and efficiency, while maintaining voltage to earth under appropriate levels with the earthing of the intermediate conductor. Such networks require not only the ac to dc conversion, but also the regulation of the dc network voltages whenever unbalanced dc loads or distributed energy resources are present. Thus, bidirectional rectifiers that provide such features are the preferred option [6]. In this context, three-level topologies are well suited for applications where the dc-side unbalances are within specified boundaries

F S1

S2

vb

L ia L ib

Cb1

vc

L

Cc1

va N

ic

F

F

p

isp

F

DS1

DS2

S41 D1

Cs1

S42

L4

Ca1

iL4 C4

i cs1

Zlp

Pp

v p0

ilp

is0

S3

DS3

S4

DS4

D2

0

S43

Cs2

F

vDC

S44 F

F Ca2

isn

i cs2

Zln

Pn

iln

F

Fourth Leg

Cb2

v 0n

n Loads Distributed Generation

Cc2

Figure 1: NPC converter with an additional leg (fourth leg) including devices to reconfigure in case an NPC leg fails. The system is aimed at the generation of symmetrical dc bipolar distribution network voltages (v p0 and v0n ) in case of unbalanced loads (Zl p and Zln ) and/or distributed energy resources (Pp and Pn ). Sinusoidal ac grid currents (ia , ib and ic ) are sought. The fourth leg provides the balancing of the average levels of v p0 and v0n and also virtually eliminates their voltage ripple during normal operation.

[7]. The Neutral Point Clamped converter (NPC) is well accepted in industrial applications and is considered for the application at hand. However, many carrier-based modulation strategies for the NPC make use of zero axis signals to improve features such as losses and EM emissions. Such strategies typically generate low frequency components to flow in the dc-link intermediate point current is0 . The result is that the partial dc-link voltages v p0 and v0n present low frequency ripple. Large capacitors can be used to reduce voltage ripple. Another option is to employ modulation or control strategies that virtually eliminate the low voltage components [8]. However, most of these strategies do not generally apply when the following features are simultaneously required: bidirectional power flow, variable power factor, low implementation complexity and dc side power unbalance. The NPC is also intrinsically limited regarding unbalanced dc-link power and the generation of distortion free ac-side currents [6, 8]. Thus, the addition of a converter to the NPC dc-link can be advantageously used to reduce the limitations. This work uses the circuit configuration shown in Figure 1 to achieve the aimed high power quality operation with a redundant NPC leg (fourth leg) to improve reliability. This converter configuration was proposed in [9] to provide redundancy and reduce dc-link capacitors low frequency ripple. One limitation of the operation proposed in [9] is that the fourth leg is driven as a two-level inverter during normal operation. This increases switching losses and the current ripple in inductor L4 and, thus, leads to an increased inductor. Other circuit variations where proposed in [10] to reduce the switching losses associated with the two-level operation through soft-switching. However, this increases circuit complexity and components count. Another limitation within the control approach in [9] is that the variable used to control the fourth leg is the current iL4 . However, if a three-level scheme is adopted there will be current flowing through the clamping diodes of the fourth leg, which presents low frequency (LF) components. Thus, the elimination of the low frequency ripple across the dc-link capacitors is difficult to achieve. This work proposes the use of the estimated current for the complete fourth leg, i.e. including the clamping diodes LF current components, and the operation of the fourth leg with a three-level modulation strategy to reduce the required L4 inductance. Additionally, reducing iL4 leads to improved dynamics to eliminate the dc-link voltage ripple. Regarding fault operation, i.e. whenever one of the three-phase NPC legs fails, it is considered that the fourth NPC leg replaces the faulted leg. In this case, the use of a modulation strategy that is able to eliminate the dc-link voltage ripple is proposed to provide LF ripple free partial dc-link voltages.

NPC Fourth Leg Control Oriented Modeling The simplified schematic depicted in Figure 2(a) is used to analyse the NPC fourth leg circuit. From where, i4 = iL4 + iS04 .

(1)

Current iS04 is the switched current that flows through the fourth leg clamping diodes. It is defined as iS04 = −s04 iL4 ,

(2)

ia

isp

L4 iL4

Sp4 vb

L ia L ib

vc

L ic

va N

Three-Phase Three-Level is0 NPC Converter

S04 is04

p da

Cs1 vp0 ics1

ib *

Pp db

i4

Cs2

S n4

dc

Pn

isn

Ci4

ic

iln

*

abs

vDC

0 v0n

ics2

abs

ilp

4th Leg PWM

d p4

abs

d n4

v0n

n

d4

vp0

(a)

iL4 Cvp,n

i *4,avg

(b)

Figure 2: (a) Simplified schematic for the analysis of the NPC fourth leg operation; and, (b) proposed NPC 4th leg control block diagram for normal operation.

where s04 is the switching function (s04 =1 when S04 conducts or s04 =0 when it is switched off). The local average value of iS04 is defined with hiS04 i = −d04 iL4 ,

(3)

where d04 is S04 duty-cycle. It follows that hi4 i = iL4 (1 − d04 ) .

(4)

Finally, considering that d p4 +dn4 +d04 =1, hi4 i = iL4 (d p4 + dn4 ) .

(5)

Therefore, the estimation of hi4 i (hiˆ4 i) can be made with the duty-cycles of the fourth leg and the sensing of iL4 . This is used to balance and reduce the ripple on v p0 and v0n . Considering that the load currents are dc, i.e. il p = I¯l p and iln = I¯ln , the reference current for zero LF dc-link ripple and balanced voltages is hi4 i∗ = − his0 i − I¯l p + I¯ln = ia |da | + ib |db | + ic |dc | − I¯l p + I¯ln

(6)

where da , db , and dc are the NPC phase-legs modulation functions.

Dc-link Voltage Balance Control and Fourth Leg Redundant Operation Considering iL4 as the state to control, it follows that 1 d iL4 = (s p4 v p0 − sn4 v0n ) dt L4

(7)

Assuming v p0 = v0n = vDC /2 and Cs1 = Cs2 = Cs and only the local average values leads to d 1 vDC hiL i = (d p4 − dn4 ) dt 4 L4 2

(8)

Finally, defining d p4 = d4 − d04 /2 and dn4 = 1 − d4 − d04 /2 , vDC d hiL4 i = (2d4 − 1) dt 2L4

(9)

It is assumed that the average value of is0 within a mains period is null in the following. From the converter dc-side the currents at node 0 are dv0n dv p0 il p − iln = Cs − (10) dt dt

3-phase NPC modulation Clears fault signal

Dc-link voltage balance and ripple control

Yes

No

4 th NPC leg modulation No

3-phase NPC special modulation

No 4th NPC leg?

No

3-phase NPC leg?

Yes

Switch fails?

Waits for NPC leg maintenance

Maintenance ready?

Yes

Clears faulted leg

Yes

Figure 3: Four legs NPC operation flow diagram.

The average value of i4 (i4,avg ) also contributes to the definition of the dc-link voltages. Thus, d 1 v p0 = − i4,avg dt 2Cs

(11)

Assuming that currents is0 and the dc-side currents present slow dynamics, equation (11) can be used to design a dc-link voltage balance controller, while (9) to design the fourth leg current controller. The control block diagram in Figure 2(b) is, thus, proposed for normal operation, i.e., no fault condition. The redundant operation flow diagram is seen in Figure 3. During normal operation, the three legs of the NPC converter connected to the ac-side of the converter operate with any type of appropriate modulation. For instance, a discontinuous PWM scheme [11] can be advantageously used to reduce losses or a space vector modulation can be used to reduce common mode (CM) or differential mode (DM) emissions [11]. The fourth leg is driven with the scheme introduced in Figure 2(b). As soon as a semiconductor failure is sensed [12], that leg is cleared from the circuit. For instance, using the schemes introduced in [13]. The three-phase NPC is recomposed and the modulation scheme is changed to the one proposed in [8]. This operation guarantees sinusoidal currents and zero dc-link ripple under limited power unbalance conditions. Large unbalance will lead to distorted ac-side currents. Finally, after maintenance of the faulted leg, the conversion system can be restored to its normal operation with four NPC legs.

Simulation Results This section presents simulation results for a conversion system with the following parameters: 0.84 0.84

0.91 0.91

0.6 0.6

0.74 0.74

0.42 0.42

80

Imaginary axis (s-1)

60

0.22 0.22

vp0-v 0n 0.96 0.96

40 0.99 0.99

20 0

200

175

150

125

100

75

50

X X

25

-20

vp0+v0n

0.99 0.99

-40 -60

0.96 0.96

-80 0.84 0.84

0.91 0.91

-200

-150

0.74 0.74

-100 Real axis (s -1)

0.6 0.6

0.42 0.42

-50

0.22 0.22

0

Figure 4: Root locus plot of the designed control loops for the differential part of the dc-link partial voltages (v p0 − v0n ) and the common part (v p0 + v0n ).

• • • • • • • •

Rated power: S = 10 kVA; NPC switching frequency: fs,NPC = 30 kHz; 4th leg switching frequency: fs,4L = 30 kHz; Inductor L4 = 250 µH; Dc-link capacitors (each): Cs = 1 mF; Parcial dc-link voltages: v p0 = v0n = 380 V; Ac RMS Line voltage: vac,rms = 380 V; Mains frequency: fg = 50 Hz. (a)

30 20 10 [A] 0 -10 -20 -30

ia

ib

ic

(b)

30 20 10 [A] 0 -10 -20 -30

ib

ia

385

[A] 0

-5 (g)

v 0n

385

vp0

[V]

385 380

375

375

375

370

370 ics1

10

20

[A] 0

(h)

40 ics1

370 (k)

40

[A] 0

-20

-20

vp0

v 0n

20 ics1

[A] 0

-10

(l)

390

380

(d)

-10

380

20

5

390 [V]

-400 (j)

10

-40

v 0n

0 [V] -200

-40 (f)

400 200

-20

-20

vp0

ia

[A] 0

[A] 0

(c)

va

20

20

(i)

40

ic

40

is0

390 [V]

(e)

30 20 10 [A] 0 -10 -20 -30

-20

-40 0,02 s

-40 0,02 s

0,02 s

Figure 5: Simulation results: (a), (b), (c) and (d) show waveforms for a conventional 3-legs NPC with balanced dc loads. (e), (f), (g) and (h) show simulation results for the proposed system under completely unbalanced dc loads. (i), (j), (k) and (l) illustrate a purely reactive operation of the proposed system. (a)

6

400

(c)

vL4

200

4 [A]

[V] 0 2 -200 0 0

200

400 600 Frequency (Hz)

800

1000 (b)

6

-400 (d)

15 10

iL4

5

4

[A] 0

[A]

-5

2

-10 -15

0 0

200

400 600 Frequency (Hz)

800

1000

66,67us

Figure 6: FFT of the current flowing through capacitor Cs1 for rated power (10 kW): (a) conventional 3-legs NPC with balanced loads and sinusoidal PWM; (b) 4-legs NPC with the proposed operation strategy under complete dclink loads unbalance and unit power factor. The graphs show peak values. Voltage (c) and current (d) waveforms at the fourth NPC leg inductor L4 . These results are for balanced dc-link load power and without the voltage ripple compensation.

The fourth leg and dc-link voltage balance controllers are designed to provide a stable operation according to Figure 4. Two open loop root loci are shown, one where the differential part of the dc-link partial voltages is plotted and the second with the common part. The closed loop poles are placed at 4.0 Hz and 6.4 Hz for the differential control loop portion of the dc-link partial voltages and 182.0 Hz and 14.3 Hz for the common part. Figure 5 leftmost column shows simulation results for a conventional three legs NPC converter operating at unit power factor and feeding balanced dc loads using sinusoidal PWM. High quality ac currents are achieved, but high dc-link partial voltages ripple is observed due to the injection of a third harmonic current into the dc-link intermediate point. The central column Figure 5 presents the results for a conversion system according to the propositions of this work. The complete load, i.e. 10 kW is connected to one of the dc buses. The dc-link partial voltages are balanced and present very low ripple, while sinusoidal ac currents are achieved. Finally, the rightmost column in Figure 5 shows the waveforms for purely reactive operation of the proposed system, i.e., the system emulates a 10 kvar inductive three-phase balanced load. A comparison of the achieved results regarding the current spectrum in one of the dc-link capacitors is shown in Figure 6. Figure 6(a) presents the LF current spectrum for a dc-link capacitor for the conditions of Figure 5(a), i.e., conventional NPC operation without dc load unbalance. A high current value at the third harmonic frequency is observed. Figure 6(b) show the LF current components for the proposed 4-legs system under complete dc-link power unbalance. The LF components are virtually eliminated.

30 20

(a) ia

ilp

10 [A] 0 -10 -20 -30 (b) 10 0 [A] -10 -20

-30

-40

(c)

390 v 0n

385 [V] 380 375

vp0

370 (d)

40

ics1

20 [A] 0 -20 -40 0.40

0.45

0.50

0.55

0.60

0.65

0.70

Time(s)

Figure 7: Transient conditions simulation results: (a) phase a current ia and load current at the upper dc-link link il p ; (b) is0 and i4 local average values; (c) partial dc-link voltages; and (d) dc-link capacitor Cs1 current and its local average value. The proposed system operation starts at 0.5 s and a complete dc-link unbalance step is applied at 0.6 s.

(a)

100

500

va 250

50 [A] 0 -50 ia

-100 450

[A] 0

-250

-50

-500

-100 450 400

[V] 350

300 0.80

va

50

0 [V]

v 0n

400

(c)

100

ia

v 0n

[V] vp0

vp0

350

1.00

1.20

1.40

1.60

300 0.80

1.00

Time(s) (b)

100

1.40

500

100

250

50

0 [V]

[A] 0 -50 ia

-100 450 400

1.60 (d)

va

va

50

[A] 0

-250

-50

-500

-100 450 400

v 0n

ia

v 0n

[V]

[V] 350

300 0.80

1.20

Time(s)

1.00

vp0

350

vp0

1.20

Time(s)

1.40

1.60

300 0.80

1.00

1.20

1.40

1.60

Time(s)

Figure 8: Simulation results for a symmetrical load steps transient behavior for phase a current ia , voltage va and partial dc-link voltages v p0 and v0n ; without the fourth leg operation: (a) 100% to 50%, (b) 50% to 100% and with the fourth leg operation: (c) 100% to 50%, (d) 50% to 100%.

The advantages of the three-level modulation scheme for the fourth NPC leg are observed on Figure 6. Figure 6(c) shows the voltage across L4 during two switching periods, where the three-level voltage is applied. The resulting current (cf. Figure 6(d)) presents lower ripple for a given local average value when compared to a two-level modulation scheme. Thus, lower inductance is necessary for a given current ripple specification. A second benefit is that the switching losses are reduced since the voltage transitions present half the value of the dc-link voltage. The optimal choice of the duty-cycle for the three-level NPC fourth leg operation should be made based on an adaptive scheme. In such an scheme, the following logic should be applied. The lower the unbalance and disturbance currents, the lower the duty-cycle. This leads to reduced fourth leg rms current values and ripple. For instance, at zero unbalance and disturbance currents, the duty-cycle could be 1/2 and, thus, no switching frequency ripple current would occur. In case of large disturbance or unbalance currents the limitation of the fourth leg duty-cycle would, in its turn, limits the achievable i4 current and its dynamic behavior. The transient behavior of the proposed conversion system operation is presented in Figure 7 for normal operation, i.e. with four legs. From 0.4 s to 0.5 s the fourth leg is off and there is no dc-link power unbalance. The converter operates with sinusoidal PWM and the dc-link voltage balance control is performed by the three-legs NPC. The local average value of is0 is high and not compensated. Thus, 10 V peak-to-peak is the resulting voltage ripple at the partial dc-link voltages. The dc-link capacitor Cs1 current presents, both, high and low (3rd harmonic) frequency components. From 0.5 s to 0.6 s the control system of the 4th leg starts and the four-legs system is able to minimize the low frequency components of the voltage across the dc-link capacitors. Slightly increased high frequency capacitor currents are observed. Finally, a 5 kW power step is applied to the dc-link causing a complete unbalance, i.e., one of the dc-link buses assumes the full load (10 kW). The proposed system is able to balance the dc-link partial voltages and keep the voltage ripple at negligible levels.

The Figure 8 show the simulation results for a symmetrical load steps transient behavior without the fourth leg operation (cf. Figure 8(a) and Figure 8(b)) and with the fourth leg operation (cf. Figure 8(c) and Figure 8(d)). Figure 8(a) and Figure 8(c) show 100% to 50% symmetrical load steps. Figure 8(b) and Figure 8(d) show 50% to 100% symmetrical load steps. The partial dc-link ripple cancellation achieves the same transient behavior applying the fourth leg comparing to the operation of three legs NPC transient behavior.

Experimental Results A lab prototype with the same specifications as given in simulation results section is currently being built to verify the proposed system operation. Preliminary results are presented from a three-phase three-level three-legs T-Type converter prototype according to Figure 9 [8] . The results shown in Figure 10 were obtained with the operation of only three-legs. Figure 10(a) employs a conventional SPWM scheme, while Figure 10(b) uses the modulation strategy introduced in [8], i.e., partial dc-link ripple cancellation emulating the operation under one faulted leg. The dc-link ripple cancellation modulation is able to drastically reduce the partial dc-link voltage ripple. In addition, the acside inductor current at phase a maximum ripple is lower for the dc-link cancellation scheme. Load steps transient behavior are shown in Figure 11 for a conventional SPWM scheme (cf. Figure 11(a) and Figure 11(b)) and for the employed partial dc-link cancellation scheme (cf. Figure 11(c) and Figure 11(d)). Figure 11(a) and Figure 11(c) show 100% to 50% symmetrical load steps. Figure 11(b) and Figure 11(d) show 50% to 100% symmetrical load steps. The partial dc-link ripple cancellation achieves the same transient behavior as the conventional SPWM one. Load disturbance rejection with the ripple cancellation scheme is appropriate for both, differential v p0 − v0n and common v p0 + v0n parts of the dc-link voltages. Ac-side inductors

Ac-side inductor Gate drivers

Bus Capacitor

Bus Capacitor

Heatsink 30.0 cm

Figure 9: Three legs three-level converter prototype. A T-Type converter is implemented [8].

va

va

ia

ia

vp0

v 0n

(a)

v 0n

vp0

(b)

Figure 10: Experimental results for the three-legs NPC operation without the special modulation (a) and with it (b). Load power: (2.1 + 2.1) kW and operation as a three-phase unit power factor rectifier.

v 0n vp0

v 0n vp0

va

va

ia

ia

(a)

(c)

v 0n vp0

v 0n vp0

va

va

ia

ia

(b)

(d)

Figure 11: Experimental results for a symmetrical load steps transient behavior operation for phase a current ia , voltage va and partial dc-link voltages v p0 and v0n ; without the special modulation: (a) shows 100% to 50%, (b) shows 50% to 100% and employed partial dc-link cancellation scheme [8]: (c) shows 100% to 50%, (d) shows 50% to 100%.

Conclusions This work presented a novel operation strategy for a four-legs NPC converter to be applied in future high quality bipolar dc distribution networks. The fourth leg is used to reduce voltage ripple and balance the partial dc-link voltages in the presence of load unbalance during normal converter operation. The proposed strategy is based on the three-level modulation of the fourth leg and an appropriate control strategy, which considers the control of the complete fourth leg current. The control oriented modeling of the fourth leg was presented in order to provide the means for the current control. The three-level operation leads to the reduction of switching losses and required inductance value when compared to state-of-the-art strategies. Simulation and experimental results verify the feasibility of the proposed strategy.

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[3] A. Domijan, Jr., A. Montenegro, A. J. F. Keri, and K. E. Mattern, ”Simulation study of the world’s first distributed premium power quality park,” IEEE Transactions on Power Delivery, vol. 20, pp. 1483-1492, 2005. [4] H. Kakigano, Y. Miura, T. Ise, and R. Uchida, ”DC Micro-grid for Super High Quality Distribution: System Configuration and Control of Distributed Generations and Energy Storage Devices,” in 37th IEEE Power Electronics Specialists Conference, 2006, pp. 1-7. [5] J. Lago, J. Moia, and M. L. Heldwein, ”Evaluation of power converters to implement bipolar DC active distribution networks: DC-DC converters,” in IEEE Energy Conversion Congress and Exposition (ECCE), 2011, pp. 985-990. [6] J. Moia, J. Lago, A. J. Perin, and M. L. Heldwein, ”Comparison of three-phase PWM rectifiers to interface Ac grids and bipolar Dc active distribution networks,” in 3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG), 2012, pp. 221-228. [7] N. Celanovic and D. Boroyevich, ”A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters,” IEEE Transactions on Power Electronics, vol. 15, pp. 242-249, 2000. [8] J. Moia, A. J. Perin, and M. L. Heldwein, ”Three-level/-phase PWM converters DC-link voltages ripple reduction technique in the alpha/beta reference frame,” in 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2012, pp. 740-747. [9] S. Ceballos, J. Pou, E. Robles, J. Zaragoza, P. Ibanez, and J. L. Martin, ”Fault-tolerant hybrid four-leg multilevel converter,” in European Conference on Power Electronics and Applications, 2007, pp. 1-9. [10] S. Ceballos, J. Pou, J. Zaragoza, E. Robles, J. L. Villate, and J. L. Martin, ”Fault-Tolerant Neutral-PointClamped Converter Solutions Based on Including a Fourth Resonant Leg,” IEEE Transactions on Industrial Electronics, vol. 58, pp. 2293-2303, 2011. [11] T. Bruckner and D. G. Holmes, ”Optimal pulse-width modulation for three-level inverters,” IEEE Transactions on Power Electronics, vol. 20, pp. 82-89, 2005. [12] P. Fazio, G. Maragliano, M. Marchesoni, and G. Parodi, ”A new fault detection method for NPC converters,” in Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on, 2011, pp. 1-10. [13] E. R. da Silva, W. S. Lima, A. S. de Oliveira, C. B. Jacobina, and H. Razik, ”Detection and compensation of switch faults in a three level inverter,” in Power Electronics Specialists Conference, 2006. PESC ’06. 37th IEEE, 2006, pp. 1-7.