Three-phase Voltage Doubler Rectifier Based on Three-state Switching Cell for Uninterruptible Power Supply Applications Using FPGA Raphael A. da Câmara, P.P. Praça, C.M.T. Cruz, R.P. Torrico-Bascopé, C.E.A. Silva, D.S.Oliveira Jr., L.H.S.C. Barreto Energy Processsing and Control Group, Electrical Engineering Department Universidade Federal do Ceará Fortaleza-CE, Brazil
[email protected] transformer for proper operation of the bypass circuit. This isolation transformer, when operating at the grid frequency, both size and cost are considerable.
Abstract— This paper presents a three-phase voltage doubler rectifier based on three-state switching cells for Uninterruptible Power Supply (UPS) applications using FPGA. Its main features are: high power factor, reduced conduction losses, weight and volume, simple control strategy based on One-cycle Control (OCC), and connection between input and output enabling the use of inverter and bypass. A theoretical analysis, simulation results and preliminaries experimental results from a 9kW development stage lab model are presented.
I.
Others topologies were proposed in literature to overcome this problem, using the isolation transformer in a high frequency DC link [3-5]. Although this UPS topology incorporating a high frequency transformer reduces weight of the system, it has increased the number of active switches and power stages, compromising the system’s overall efficiency and reliability.
INTRODUCTION
An equipment that has been highlighting in the power electronics on its ability to supply clean and reliable power to critical loads such as industrial processes, computers, network servers, telecommunications systems, medical systems, even in situations of power outages or anomalies of the mains is the Uninterruptible Power Supply (UPS). An UPS can be classified into three types: On-line, Line-interactive and Stand-by [1]. Among the different types of UPS systems, the on-line UPS system is widely recognized as the superior topology in performance, power conditioning and load protection [2].
Transformerless UPS incorporating a common neutral bus line using a half-bridge converter and inverter has attracted special interest for applications in computer and telecommunication systems. A typical single-phase on-line UPS system is shown in Fig. 1 (b). This type of system is highly cost-effective and acceptable due to its total power conversion efficiency improvement, volume and weight reduction [6-9]. However, some disadvantages are found as: unbalance between the upper and lower side DC link capacitors, AC-DC and DC-AC converters switches are exposed to total DC link voltage [10].
On-line UPS systems consist of a rectifier, a battery set, an inverter, and a bypass. A typical single-phase on-line UPS system based on full-bridge converters is shown in Fig. 1 (a). In this configuration it is normally required an isolating
The single-phase three-level rectifier with a half-bridge inverter can be advantageous for many applications [11-12]. In this converter only half of the DC link voltage is applied across the rectifier switches and the current flows through only
bypass
S1
S2
bypass
Si1
Si2
S1
Si1 C1
S
Lf C
Vs
S3
Battery bank
S4
Cf
Si3
Si4
Isolation Transformer
L
Lf Battery bank
Vs
S2
Cf
Si2 C2
(a) Figure 1.
(b)
A typical single-phase on-line UPS system: (a) based on full-bridge converters; (b) based on half-bridge converters.
This work was supported by CAPES – Higher Education Improvement Coordination
978-1-4244-4783-1/10/$25.00 ©2010 IEEE
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Load
L
Load
S
two or three power semiconductors simultaneously. Therefore, this converter presents less conduction losses, and a common neutral bus line is connected between the middle point of DC capacitors link, input and load, making it possible to realize the bypass operation without an isolating transformer. However, with the intention to work with output power over few kilowatts, this converter has high weight, volume, current stress on the semiconductors devices presenting a high cost of components and low efficiency. These drawbacks are solved by using of three-state switching cell [13] in the single-phase three-level rectifier presented in Fig. 2 [14]. But if the output power arise more than few kilowatts, it’s necessary to work with three-phase topologies. Thus, the single-phase converter presented in Fig. 2 is updated to three-phase topology presented in Fig. 3.
consists of three single-phase rectifier, presented in Fig. 2, star-connected like VIENNA [15] but with three-state switching cell. Every single-phase rectifier has one inductor, one autotransformer with windings T1 and T2, four diodes, two bi-directional controlled switches. The converter operates only in continuous conduction mode (CCM). The converter operation modes are defined by comparison between input voltage and output voltage in function of controlled switches duty cycle of each phase. While the input phase voltage is less than the half of output voltage, the converter operates in overlapping mode (duty cycle > 0.5) and, while the input phase voltage is greater than the half of output voltage, the converter operates in non-overlapping mode (duty cycle < 0.5).
Within this context, this paper presents a three-phase voltage doubler rectifier based on three-state switching cells for UPS application that presents power factor correction (PFC), reduced current stress on semiconductors devices, reduced volume and weight of the magnetic components, simple control strategy based on OCC using FPGA and connection between the middle point of DC link, input and load, enabling the bypass operation without an isolating transformer. The theoretical analysis, simulation results and preliminaries experimental results of a development stage lab model of 9kW output power are presented to validate the proposal.
B. Converter Operation Analysis The operation of proposed three-phase rectifier is similar to single-phase rectifier. Thus, to simplify the analysis, single-
L1
V1
D2
V1
D3
S1
S2
S3
S4
D1
D1
D2
D3
D4
D5
S1 S2
T2
Vo2
VGS1 VGS2 IS1
S1
S2
S3
S4
VS1
S5
S6
ID1
T3
D7
D8
D9
D10
D11
IM
S9
S10
VD1
S11
S12
VL
D12
t
Im Im/2
t
IM/2
Vo
t
t
IM/2 Im/2
S8
T5
T6
t
IL1
C1
S7
C2
D4
Figure 4. Operating stages in non-overlapping mode.
T1
T4 L3
C1
Interval (t1 – t2) and (t3 – T)
D6
T2
D2
Vo1
D3
Figure 2. Single-phase rectifier topology.
L2
L1
V1
C2
D4
C2
D4
T1
Vo1
T2
L1
S2
T2
Interval (t0 – t1), similar to (t2 – t3)
C1
T1
L1
C1 Vo1
D3
Circuit Description The proposed converter is shown in Fig. 3. It basically D1
D2
S1
PROPOSED CONVERTER CIRCUIT
II. A.
D1 T1
t
Vo
t
C2
t
t0 Figure 3. Proposed 3-phase rectifier topology.
t1
t2
t3
T
Figure 5. Main theoretical waveforms in overlapping mode.
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D1 L1
V1
D2
mains to the load. The transfer of the energy stored to the load occurs in time intervals (t1 – t2) and (t3 – T). The operation of the topology in the negative semi-cycle of the input voltage is analogous to the positive one. Note that, for both operating modes, the inductor current frequency is the double of switching frequency enabling the size and volume reduction of magnetic core.
C1 Vo1
T1 S1 S2
T2 D3
C2
D4
The duty cycle in each phase must vary on each commutation period for constant switch frequency in order to control the average value of the output voltages. Departing of the validation relation for the classic boost converter static gain, output voltage by input voltage, it has:
Interval (t0 – t1), similar to (t2 – t3) D1 L1
V1
D2
C1 Vo1
T1 S1
Vo 1 = . Vin 1 − D
S2
T2 D3
D4
(1)
C2
Replacing adequately, it arrives the three-phase variation duty cycle term. The Fig. 8 represents the duty cycle variation expressed by (2).
Interval (t1 – t2) and (t3 – T) Figure 6. Operating stages in overlapping mode.
⎧ 1 ⎪ Da (ω t) = 1 − β ⋅ sin(ω t) ⎪ ⎪ 1 ⎨ D b (ω t) = 1 − ⋅ sin(ω t + 120º ) . β ⎪ ⎪ 1 ⎪ Dc (ω t) = 1 − ⋅ sin(ω t − 120º ) β ⎩
(2)
Being β defined as the relation between output voltage and input peak voltage, by the following expression:
β=
Vo . Vinpk
(3)
1
Figure 7. Main theoretical waveforms in overlapping mode.
The operating stages in the overlapping mode are shown in Fig. 6 according to the main waveforms in Fig. 7. During the time intervals (t0 – t1) and (t2 – t3) occurs the energy storage in the inductor L1 and there is no power transfer from the
D(wt)
phase rectifier operation is presented. The operating stages in non-overlapping mode are shown in Fig. 4 according to the main waveforms in Fig. 5. During the time intervals (t0 – t1) and (t2 – t3) occurs the energy storage in the inductor L1 and the current increases linearly. Half of the load current flows through diode D2 in time interval (t0 – t1) or D1 in time interval (t2 – t3) and half flows through switch S1 in time interval (t0 – t1) or S2 in time interval (t2 – t3). This way, the current stresses of switches are reduced. The transfer of the energy stored in the inductors to the load occurs in time intervals (t1 – t2) and (t3 – T). The operation of the topology in the negative semi-cycle of the input voltage is analogous to the positive one.
0.5
phase A phase B phase C 0
0
60
120
180
240
300
360
wt [degrees]
Figure 8. Three-phase duty cycle variation.
III.
CONTROL STRATEGY
The control goal is to maximize the power factor, adjusting the input current waveform until it is equal to the input voltage waveform. The modulation strategy used is based on the appropriate variation of duty cycle at a constant frequency.
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current reference according to the load level as used in many other control approaches.
The proposed control strategy is based on One-Cycle Control (OCC) technique for VIENNA rectifier [16]. Its main features are: •
Constant switching frequency.
•
Simple and reliable. This controller is composed of one or two integrators with reset along with some flipflops, comparators, and some logic and linear components.
•
No need for multipliers that are required to scale the
•
No three-phase input ac voltage sensors are required.
The schematic of three-PFC controller for the VIENNA rectifier is shown in Fig. 9. However, this controller is very complex for digital implementation. A simple way to achieve the same OCC response is multiplying a traditional saw-tooth carrier with signal vm from voltage compensator. Throughout vm is possible changing the peak value of the saw-tooth carrier without changing your period. To this converter is used two saw-tooth carrier with half phase shifted. The power stage and new control circuit schematic diagram is show in Fig. 10. IV.
DIGITAL IMPLEMENTATION
The digital control is implemented using the Cyclone® II EP2C20F484C7 FPGA, programmed with the software Quartus II®. It has the following features [17]: •
18,752 LEs;
•
52 M4K RAM blocks;
•
315 I/O pins;
•
4 digital PLLs.
The development board has the following hardware features:
Figure 9. Schematic of three-PFC controller for VIENNA rectifier[16].
D1 L1
D2
D3
D4
D5
D6
L2
S1
S2
S3
S4
Altera Cyclone® II EP2C20 FPGA device;
•
50 MHz, 27MHz and 24MHz oscillators;
•
Two 40-pin expansion headers;
•
8-MB SDRAM memory, 512-kB SRAM, and 4-MB flash memory.
The controller was implemented using VHDL language and the block schematic diagram at Quartus® II software. In Fig. 11 is shown the top-level entity, which represents all controller hardware and its submodules for each phase.
C1
T1
T2
•
Vo1
T3 S5
S6
S7
S8
A/D selection bits INPUT VCC INPUT VCC INPUT VCC
s2
T4 L3
s3 entrada18[9..0]
T5
T6 D7
D8
D9
D10
D11
S9
S10
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D12
SIGNAL
VOLTAGE
CONDITIONING
REGULATOR
Sensors data
Vo2
PWM
C2
Phase A
CLK_EXT
X
OUTPUT
PWM
MODULATOR
DRIVER S1-S2
INPUT VCC
SAW-TOOTH CARRIERS
Offset Vc
X
Figure 11. The block schematic diagram in Quartus® II.
Vref
DRIVER S3-S4
Vm
Voltage Compensator
Phase B Phase C
Figure 10. Proposed control block diagram of the 3-phase rectifier topology.
A. Signal Conditioning This block, shown in Fig. 12, is the entity that provides the values of voltage and current, using the A/D samples, generating an error signal, and offset signal between the output voltages to control the unbalanced output voltage in DC link. The “somador” block and the “lpm_add_subX” blocks are megafunctions provided by ALTERA® in Quartus® II software. The “demux” block were made using VHDL language.
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OUTPUT
D. PWM Modulator The block responsible to do the PWM modulation is shown in Fig. 15 and it is composed by two comparators. A voltage control vc from voltage regulator block is compared with two saw-tooth carriers half phase shifted multiplied with vm from saw-tooth carriers block. The comparator output is PWM signal used to control the switches at each phase in converter.
CURRENT[9..0]
lpm_add_sub1 dataa[9..0] datab[9..0]
A A-B
result[9..0]
OUTPUT
OFFSET[9..0]
B
inst12
Offset to unbalanced control of DC link lpm_add_sub0 s0
demux
A/D selection bits
INPUT VCC INPUT VCC INPUT VCC
s1 entrada[9..0]
Sensors data
somador
s0
port_Iin[9..0]
s1
port_Vo1[9..0]
entrada[9..0]
port_Vo2[9..0]
614
Vref
A result[9..0] OUTPUT A A-B result[9..0] datab[9..0] A+B B datab[9..0] inst9 B
dataa[9..0]
inst16
ERROR[9..0]
inst8
modulador
Figure 12. The signal conditioning block in Quartus® II.
compare Vc[9..0] Mout1[9..0]
B. Voltage Regulator In the Fig. 13 is the voltage regulator block, which receives the error signal, offset signal and current signal from the previously block. This error is applied as an input signal, and the control signal is calculated using the following expression:
INPUT VCC INPUT VCC
dataa[9..0] datab[9..0]
aeb
OUTPUT
pwm1
inst13
modulador compare
Mout2[9..0]
dataa[9..0] datab[9..0]
INPUT VCC
aeb
OUTPUT
pwm2
inst14
Figure 15. The PWM modulator block in Quartus® II.
U k = K 4 ⋅ U k −1 − K 3 ⋅ U k − 2 + K 2 ⋅ e k + K1 ⋅ e k −1 − K 0 ⋅ e k − 2 . (4)
V.
Uk represents the current control signal, Uk-1 represents the previously control signal, Uk-2 represents the last control signal, ek is the actual input error, ek-1 represents the previously input error and ek-2 represents the last input error. Constants K4 to K0 are the gains in the controller. Current[9..0]
INPUT VCC INPUT VCC
Of fset[9..0]
INPUT VCC INPUT VCC
clk_ext1
Ventrada[9..0]
A. Converter Specifications The proposed three-phase voltage doubler boost rectifier based on three-state switching cells design specifications are shown in Table I. The converter switching frequency was assumed fs = 20kHz. All following design are made for each phase.
lpm_add_sub1
compensador_v hdl Error[9..0]
dataa[9..0]
Vout[9..0]
somador
clock
TABLE I.
A
datab[9..0] B A result[9..0] inst10 A+B datab[9..0] B
A-B
result[9..0] OUTPUT
Vc[9..0]
OUTPUT
Vm[9..0]
inst15
Figure 13. The voltage regulator block in Quartus® II.
C. Saw-tooth Carriers This block is responsible to generate two saw-tooth carriers with half phase shifted and multiplying these carriers with the vm signal from voltage regulator block and it is shown in Fig. 14. The carriers are made by counters and comparators and the multiplier is made using VHDL.
Vm[9..0]
comparador
inst
compare
up counter
q[9..0] a c lr
clock
dataa[9..0] datab[]=12
aeb
saw -tooth 1
multiplicador
comp2
Vm[9..0]
Mout1[9..0]
OUTPUT
Mout1[9..0]
dadoA[9..0]
Mout2[9..0]
OUTPUT
Mout2[9..0]
cont2 clock
inst1 inst2
compare
up counter
q[9..0] a c lr
contador INPUT VCC
Parameter Value K 32768 K1 1073741824
INPUT VCC
DESIGN SPECIFICATIONS
Output power Mains input voltage Output voltage Mains frequency Output voltage ripple Input current ripple Theoretical efficiency
dataa[9..0]
Parameter Value inst5 K4 49873 K3 17105 K2 5702 Voltage regulator K1 98 K0 5571
dataa[9..0] aeb datab[]=205
Po = 9kW V1 = 110Vac Vo=200+200Vdc fr = 60Hz ΔVo = 5%.Vo ΔI1 = 20%.I1 η = 0,97
1) Inductor: The inductance is calculated by (5), considering Vo = 200V: L1 =
Vo = 62,87 μ H . 16 ⋅ ΔI1 ⋅ f s
(5)
To the project is adopted L1 = 60μH. The rms inductor current and the inductor peak current is determined using (6) and (7), respectively:
dadoB[9..0]
I rmsL1 =
inst11
inst3
Po = 28,12A . 3 ⋅η ⋅ V1
(6)
2 ⋅ I rmsL1 = 39, 76A .
(7)
saw -tooth 2 half phase shifted
comp3 compare
dataa[9..0] aeb datab[]=103 inst4
comp2
count3 sset clock inst7
compare
up counter
q[9..0] a c lr
clk_ext
EXPERIMENTAL RESULTS
I pL1 =
dataa[9..0] aeb datab[]=205 inst6
Figure 14. The saw-tooth carriers block in Quartus® II.
2) Autotransformer: The rms winding current and the peak current is calculated by (8) and (9):
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IrmsT1 =
IpT1 =
IrmsL1 = 14, 06A . 2
(8)
I pL1
(9)
= 19,88A .
2
3) Controlled switches: The switch average current and rms current is given by (10) and (11), respectively: (4 ⋅ β − π ) ⋅ Io = 4, 93A , 3 ⋅ π ⋅η
(10)
2 ⋅ Io β ⋅ (3 ⋅ π ⋅ β − 8) ⋅ = 8,19A , 3 ⋅η 6 ⋅π
(11)
I avgS1 =
I rmsS1 =
Figure 17. Ouput voltage in each capacitor (V01 and V02) and total output voltage (Vototal).
4) Diodes: The diode average current is given by (12): I avgD1 =
Io = 11, 25A . 4
(12)
5) Filter capacitors: The capacitance value of C1 = C2 is defined by (13): C1 ≥
I pL1 2 ⋅ π ⋅ f r ⋅12 ⋅ β ⋅ ΔVo
≅ 1360 μ F .
(13)
The converter parameters are presented in Table II. TABLE II. Inductor L1 Autotransformer Switches S1 – S4 Diodes D1 - D4 Capacitors C1 and C2
Figure 18. Control voltages in each phase and voltage vm waveforms.
currents in each phase waveforms where power factor correction achieved is 99.25%. Fig. 17 shows the output voltages in each capacitor and total output voltage waveforms. Fig. 18 shows the control voltages vc in each phase and the output of voltage feedback regulator vm waveforms.
PARAMETERS OF CONVERTER L = 60μH NEE – 65/33/26 (Thornton Ipec) NL = 16 turns (37 x 22AWG) NEE – 55/28/21 (Thornton Ipec) Np = Ns = 12 turns (15 x 22AWG) IRGP50B60PD1 30EPH06 C = 1360μF (2x680µF/ 350V)
C. Experimental Results A lab model of the proposed converter is actually in development stage. Its picture is shown in Fig. 19. Thus,
B. Simulation Results Fig. 16 shows the input phase voltage (Va) and input
Figure 16. Input phase voltage (Va) and input currents in each phase waveforms.
Figure 19. Lab model picture.
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REFERENCES [1]
[2]
[3]
[4]
[5] Figure 20. Input phase voltage and input currents in each phase (100V/div, 20A/div, 5ms/div). [6]
[7]
[8]
[9]
[10] Figure 21. Output voltage in each capacitor V01 and V02 (100V/div, 2ms/div).
[11]
preliminaries experimental results are presented. Fig. 20 shows the input phase voltage and input currents in each phase waveforms where power factor correction is observed. Fig. 21 shows the output voltage in each output capacitor. VI.
CONCLUSIONS
A three-phase rectifier with PFC characteristics based on three-state switching cell and its theoretical analysis, digital implementation, simulation results, and preliminaries experimental results is presented in this paper. The important features observed in the proposed converter are: high input power factor, new simple control scheme based on OCC using digital control with FPGA, reduced conduction losses, reduced volume and weight of the magnetic components (about 53% if compared with VIENNA topology) and connection between input and output enabling by-pass without isolating transformer.
[12] [13]
[14]
[15]
[16]
[17]
ACKNOWLEDGMENT The authors would like to thank the Energy Processing and Control Group – GPEC and the Electrical Engineering Department for all material, physical and mental support.
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