Threshold Voltage Model for Short-Channel Undoped ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 9, SEPTEMBER 2008

Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs Andreas Tsormpatzoglou, Charalabos A. Dimitriadis, Member, IEEE, Raphaël Clerc, G. Pananakakis, and Gérard Ghibaudo

Abstract—A simple threshold voltage model of an undoped symmetrical double-gate MOSFET has been developed, based on an analytical solution of Poisson’s equation for the potential distribution. The model has been verified by comparing the threshold voltage roll-off with the channel length with simulation results for different silicon thicknesses, gate oxide thicknesses, and drain voltage values. Good agreement between model and simulation results is obtained by calibrating the minimum carrier charge sheet density adequate to achieve the turn-on condition. Index Terms—Double-gate (DG) MOSFET, threshold voltage modeling.

I. INTRODUCTION

T

HE DOUBLE-GATE (DG) MOSFET is one of the most promising architectures for scaling CMOS devices down to nanometer size [1], since they allow a significant reduction of the short-channel effects (SCEs), such as threshold voltage roll-off, drain-induced barrier lowering (DIBL), and subthreshold slope degradation [2]–[4], compared to planar single-gate MOSFETs. Moreover, in DG MOSFETs, the ultrathin channel material is preferred to be undoped. The absence of dopant atoms in the channel material eliminates adverse effects, such as mobility degradation [5] and random microscopic fluctuations of dopant atoms, which can lead to unwanted dispersion in the device characteristics [6]. Because of these advantages, a simple analytic threshold-voltage model for undoped DG MOSFETs is highly desirable in order to facilitate the design of such nanoscale devices. Recently, we have studied SCEs in undoped DG MOSFETs by deriving a simple analytical expression for the 2-D potential distribution along the channel of symmetrical DG MOSFETs in weak inversion [7]. Based on this analytical potential distribution, a simple analytical expression for the threshold voltage is derived for undoped DG MOSFETs, which is verified by comparing the model with numerical results of the threshold

Fig. 1.

Schematic cross section of a symmetrical DG MOSFET.

voltage roll-off against the channel length. Quantum confinement effects will not be considered here for Si thickness smaller than 10 nm, since the quantum correction to the threshold voltage is much smaller in lightly doped devices compared to highly doped ones [8]. II. THRESHOLD VOLTAGE FORMULATION A schematic cross section of a symmetric n-channel DG MOSFET and the definition of the geometrical characteristics are shown in Fig. 1. Considering the depletion charge in Poisson’s equation, when the ratio of channel length/silicon thickness is > 2, in the subthreshold region of undoped (or lightly doped) symmetric DG MOSFETs, the 2-D potential distribution φ(x, y) along the channel can be expressed with good accuracy as follows [7]: 1

φ(x, y) = Vg + Manuscript received October 30, 2007; revised May 21, 2008. The work of A. Tsormpatzoglou and C. A. Dimitriadis was supported by the Greek General Secreteriat for Research and Technology under Contract PENED 2003 (03ED709). The review of this brief was arranged by Editor C. McAndrew. A. Tsormpatzoglou and C. A. Dimitriadis are with the Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece (e-mail: [email protected]). R. Clerc and G. Pananakakis are with the Institut National Polytechnique de Grenoble, 38054 Grenoble Cedex 9, France. G. Ghibaudo is with the Institut de Microélectronique, Electromagnétisme et Photonique Laboratory, MINATEC–Institut National Polytechnique de Grenoble, 38054 Grenoble Cedex 9, France. Digital Object Identifier 10.1109/TED.2008.927394

e

2L λ

−1

Vbi + Vd − Vg

e

L+y λ

−e

L−y λ

2L−y y + Vbi − Vg e λ − e λ

where λ is the natural channel length given by εSi tox tSi εox x2 εox x λ= − 1+ . 2εox εSi tox εSi tox tSi

(1)

(2)

with εSi as the dielectric constant of silicon, εox as the dielectric constant of the oxide, tox as the oxide thickness, tSi as the

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TSORMPATZOGLOU et al.: THRESHOLD VOLTAGE MODEL FOR SHORT-CHANNEL UNDOPED DG MOSFETs

silicon thickness, and L as the channel length. In (1), Vg = Vg − φms , where φms is the gate work function referenced to intrinsic silicon, and Vbi is the built-in potential across the source/drain-channel junctions (Vbi = kT ln(Nd /ni ), where Nd is the donor concentration of the source/drain contacts and ni is the intrinsic carrier concentration. The simple potential distribution (1) can be used to model the threshold voltage in DG MOSFETs. The threshold voltage VT can be defined quantitatively as the gate voltage at which the minimum carrier charge sheet density Qinv reaches a value QTH adequate to achieve the turnon condition [9]. Such a definition is equivalent to the constant drain current method of VT extraction, which is widely used in both numerical simulations and experimental measurements [10]–[12]. The channel position at which the potential reaches its minimum value is called “virtual cathode”. The position of the minimum potential along the longitudinal direction ymin can be calculated from

∂φ(x, y)

= 0. ∂y ymin

(3)

From (1) and (3), we obtained the following expression for ymin :  L L λ − 1 V e − V + Vd e λ g L λ  bi . = − ln L 2 2 Vbi − Vg e λ − 1 − Vd 

ymin

(4)

From (4), it is clear that at Vd = 0, ymin = L/2. When Vd = 0, the position of the potential minimum is located closer to the source end. By substituting (4) into the potential equation (1), we can determine the position of the virtual cathode at different positions along the silicon thickness. The carrier charge sheet density at the potential minimum can be obtained by integrating the spatial density of Qinv throughout the entire channel thickness. For undoped DG MOSFET, it becomes tSi Qinv = ni

e

qφ(x,ymin ) kT

dx.

(5)

0

QTH VT = φms +AVth ln ni tSi 1/2 1/2 QTH QTH −B Vbi −Vth ln Vbi +Vd −Vth ln ni tSi ni tSi −C(2Vbi +Vd )

where Vth is the thermal voltage, and A, B, and C are the parameters given by A=

e

4L λ

(6)

− 2e L λ

2L λ

+1 4

e −1 L L 2e 2λ 1 + e λ B= 2 L eλ − 1 3L λ

2L

L

− 4e λ + 2e λ L 4 eλ − 1 εSi tox tSi εox tSi εox tSi − λ= 1+ . 2εox εSi 4tox εSi 16tox

C=

2e

(7)

(8)

For long enough channel, it is A = 1, and the parameters B and C tend to zero; thus, the threshold voltage expression reduces to QTH (9) VT = φms + Vth ln ni tSi which is similar to the one reported in previous work [3], [4]. Based on simulation results for the dependence of the longchannel threshold voltage on the silicon film thickness, the QTH value has been determined to be about QTH = 3.2 × 1010 cm−2 [3]. The threshold voltage roll-off ∆VT and the DIBL effects, which characterize the SCEs in DG MOSFETs, can be determined from (6)–(9). The parameter ∆VT defined as the threshold voltage measured at a given Vd at any gate length minus the threshold voltage of long channel, using (6)–(9), is calculated by QTH ∆VT = (A−1)Vth ln ni tSi 1/2 1/2 QTH QTH −B Vbi −Vth ln Vbi +Vd −Vth ln ni tSi ni tSi −C(2Vbi +Vd ). (10) The DIBL effect is defined as the decrease in threshold voltage when the drain voltage is increased from a low value Vd,low (e.g., 0.1 V) to a high value Vd,high (e.g., 1 V). From (6), the DIBL parameter can be written analytically as

Since the effective conductive path is located at the position x = tSi /4 from the silicon surface [1], [2], the integral in (5) can be approximated by taking the integrand fixed at its value of x = tSi /4 [3], [4]. The value of Vg at which Qinv = QTH leads to the simple and explicit expression for the threshold voltage VT

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QTH ni tSi

1/2

DIBL = B Vbi − Vth ln 1/2 QTH × Vbi + Vd,high − Vth ln ni tSi 1/2 QTH − Vbi + Vd,low − Vth ln ni tSi + C(Vd,high − Vd,low ).

(11)

III. VERIFICATION OF THE MODEL The threshold voltage model has been verified by comparing the model with the simulation results of ∆VT versus L using the

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Fig. 2. Threshold voltage roll-off versus channel length of undoped DG MOSFET at Vd = 0.1 V and different silicon thicknesses. The symbols are numerical results obtained for gate oxide thickness: (a) tox = 1 nm, (b) tox = 1.5 nm, and (c) tox = 2 nm. The solid lines are accounting for model results obtained from (8).

FlexPDE program. The threshold voltage roll-off ∆VT with L has been calculated from Id –Vg plots in the subthreshold region by determining the Vg shift for a constant drain current Id = 10−8 A. The subthreshold drain current of the short-channel DG MOSFET has been calculated based on the extra potential induced in the silicon film due to SCEs [7]. Figs. 2 and 3 show the simulation results of ∆VT versus L for undoped DG MOSFETs, with the gate oxide and silicon thickness as parameters varying within wide ranges and for drain voltages Vd = 0.1 and 1 V, respectively. The calibrated values of QTH to fit the ∆VT model of (10) with the simulation results in Figs. 2 and 3 were found to be described by the relationship 2 λ cm−2 . QTH = 1011 1 − (5 + Vd ) 2L

(12)

Fig. 3. Threshold voltage roll-off versus channel length of undoped DG MOSFET at Vd = 1 V and different silicon thicknesses. The symbols are numerical results obtained for gate oxide thickness: (a) tox = 1 nm, (b) tox = 1.5 nm, and (c) tox = 2 nm. The solid lines are accounting for model results obtained from (8).

As shown in Figs. 2 and 3, the threshold voltage roll-off with channel length described by (10) and (12) shows a good agreement with the numerical results for all combinations of the device dimensions L, tox , tSi , and applied drain voltages Vd , proving the accuracy of the proposed threshold voltage model. In (12), the value of 1011 corresponds to the Qth of a long channel device (i.e., Qth → 1011 for L λ), which is higher by a factor of about three from the value of reference [3]. Thus, for a short-channel device, QTH is dependent on the device dimensions L, tox , tSi , the applied drain voltage Vd , and also the exact position of the effective conductive path within the channel, located at the position x = tSi /4 from the silicon surface. The variation of the DIBL coefficient with channel length described by (11) shows good agreement with the numerical results for a DG MOSFET with tox = 2 nm and tSi as a parameter as shown in Fig. 4, confirming the accuracy of the VT model. The advantage of the proposed analytical threshold voltage model for short-channel DG MOSFETs relies on its

TSORMPATZOGLOU et al.: THRESHOLD VOLTAGE MODEL FOR SHORT-CHANNEL UNDOPED DG MOSFETs

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[10] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Andersopn, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm p-channel FinFET,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 880–886, May 2001. [11] B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, “High performance fullydepleted tri-gate CMOS transistors,” IEEE Electron Device Lett., vol. 24, no. 4, pp. 263–265, Apr. 2003. [12] A. Kranti and G. A. Armstrong, “Performance assessment of nanoscale double- and triple-gate FinFETs,” Semicond. Sci. Technol., vol. 21, no. 4, pp. 409–421, Apr. 2006.

Fig. 4. Plots of DIBL coefficient versus channel length of DG MOSFETs with tox = 2 nm and the silicon thickness as a parameter.

simplicity, providing an accurate new VT model appropriate for use in circuit simulations. IV. CONCLUSION A simple analytical 2-D model for the threshold voltage of undoped symmetrical DG MOSFET has been derived, based on an analytical solution of the 2-D Poisson’s equation for the potential distribution. The model is compared with the simulation results of the threshold voltage roll-off against the channel length for different values of silicon thickness, gate oxide thickness, and drain voltage and for channel lengths down to 15 nm. Good agreement between model and simulation results has been observed by calibrating the minimum carrier charge sheet density adequate to achieve the turn-on condition. R EFERENCES [1] The International Technology Roadmap for Semiconductors, 2007. [Online]. Available: http://public.itrs.net [2] S.-H. Oh, D. Monroe, and J. M. Hergenrother, “Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs,” IEEE Electron Device Lett., vol. 21, no. 9, pp. 445–447, Sep. 2000. [3] Q. Chen, E. M. Harrell, and J. D. Meindl, “A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1631–1637, Jul. 2003. [4] H. A. El Hamid, J. R. Guitar, and B. Iniguez, “Two-dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1402–1408, Jun. 2007. [5] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, “Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors,” in VLSI Symp. Tech. Dig., Jun. 2000, pp. 174–175. [6] X. Tang, V. K. De, and J. D. Meindl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 369–376, Dec. 1997. [7] A. Tsormpatzoglou, C. A. Dimitriadis, R. Clerc, Q. Rafhay, G. Pananakakis, and G. Ghibaudo, “Semi-analytical modeling of short channel effects in Si and Ge sub-30 nm symmetrical double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1943–1952, Aug. 2007. [8] G. Chindalore, S. A. Hareland, S. Jallepalli, A. F. Tasch, Jr., C. M. Maziar, V. K. F. Chia, and S. Smith, “Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers,” IEEE Electron Device Lett., vol. 18, no. 5, pp. 206– 208, May 1997. [9] Y. Ma, Z. Li, L. Tian, and Z. Yu, “Effective density-of-states approach to QM correction in MOS structures,” Solid State Electron., vol. 44, no. 3, pp. 401–407, Mar. 2000.

Andreas Tsormpatzoglou was born in Thessaloniki, Greece. He received the M.Sc. degree in material science from the Department of Physics, Aristotelian University of Thessaloniki (AUTH), Thessaloniki, in 2004. He is currently working toward the Ph.D. degree, in cosupervison of AUTH and Institut de Microélectronique, Electromagnétisme et Photonique Laboratory, at the Institut National Polytechnique de Grenoble, Grenoble, France. His current research interests include quantum dots, and analytical and numerical simulation of nanoscale MOSFETs.

Charalabos A. Dimitriadis (M’90) was born in Naousa, Greece, in 1950. He received the Honours degree in physics from the Aristotle University of Thessaloniki, Thessaloniki, Greece, in 1974, and the M.Sc. and Ph.D. degrees in solid state electronics from the Institute of Science and Technology, University of Manchester, Manchester, U.K., in 1976 and 1979, respectively. He was elected as a Lecturer in 1985, as an Assistant Professor in 1988, as an Associate Professor in 1992, and as a Professor in 2001 with the Department of Physics, Aristotle University of Thessaloniki. Between June 1988 and February 1989, he spent his sabbatical at the Max-Planck Institute, Stuttgart, Germany, working on the growth and characterization of silicides. Between May 1996 and October 1996, he spent his sabbatical at the Laboratiore de Physique des Composants a Semiconducteurs, Grenoble, France, working on low-frequency noise characterization of semiconductor devices and hot-carrier effects in submicrometer MOSFETs. Between May 1998 and July 1998, he was an Invited Professor with the Laboratiore de Physique des Composants a Semiconducteurs, Grenoble, working on low-frequency noise characterization and hot-carrier effects in polysilicon TFTs. During the academic years 2001–2003, he was the Director of the Solid State Physics Group, Physics Department, Aristotle University of Thessaloniki. He has authored or coauthored more than 200 articles in international refereed journals and conferences and three book chapters. He is the holder of one patent. His current areas of research are in nanodevices, polysilicon TFTs, and low-frequency noise in semiconductor devices.

Raphaël Clerc was born in Thionville, France, in 1975. He received the M.S. degree in physics and engineering and the Ph.D. degree in electrical engineering from the ENSPG School [Institut National Polytechnique de Grenoble (INPG)], Grenoble, France, in 1998 and 2001, respectively. During 2001–2002, he was with L. Selmi and E. Sangiorgi’s group in the University of Udine, Udine, Italy, as Postdoc student, working on Monte Carlo device simulation. He has been an Associate Professor with INPG since September 2002. His field of experience covers the area of the modeling, simulation, and characterization of advanced MOS devices, and more specifically, quantum effects, transport in dielectrics, compact modeling, electrical characterization and parameter extraction, transport in the quasi-ballistic regime, and Monte Carlo simulation. He has authored or coauthored more than 30 publications in international journals and conferences. Dr. Clerc is a member of the ESSDERC technical committee.

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G. Pananakakis received the degree in engineering from the Technical University of Athens, Athens, Greece, in 1968, the degree from the Ecole NationaleSupérieure d’Electrotechnique, Electronique, Informatique et Hydraulique de Toulouse, France, in 1969, and the Dr. Eng. and Doctorat d’Etatin degrees from the Institut National Polytechnique de Grenoble (INPG), Grenoble, France, in 1974 and 1979, respectively. He is currently a Professor with the INPG, where he is interested in the reliability issues of thin dielectric layers, particularly in the degradation features of nonvolatile memories and scaled-down novel dielectrics, in the transport phenomena in tunnel dielectrics, as well as in device modeling. He has authored more than 100 publications in referred international scientific reviews and more than 150 communications to national or international conferences. Prof. Pananakakis has been a member of several councils and commissions (Scientific, Administration Council, Organization of Data Banks) of the INPG. He is also responsible for European Research Programs.


Gérard Ghibaudo was born in France in 1954. He received the B.S. degree, the Ph.D. degree in electronics, and the State Thesis degree in physics from the Institut National Polytechnique de Grenoble (INPG), Grenoble, France, in 1979, 1981, and 1984, respectively. He was an Associate Researcher with the Centre National de la Recherche Scientifique in 1981. He is currently a Director of Research with the Institut de Microélectronique, Electromagnétisme et Photonique Laboratory located at MINATEC–INPG. During his academic year 1987–1988, he spent a sabbatical year at Naval Research Laboratory, Washington, DC, where he worked on the characterization of MOSFETs. He has surpervised over 41 Ph.D. students in his career. He was or is involved in several European research projects (Joint coordinator of BRANOISE, participant to APBB, ADEQUAT 1-2-+, PROPHECY, ADAMANT, NANOCMOS, PULLNANO, FOREMOST. . .) or national programs (coordinator of RMNT-Ultimox, participant to RMNT-CMOS-DALI. . .). During his career, he has authored or coauthored over 238 articles in international refereed journals, 408 communications, and 45 invited presentation in international conferences and 17 book chapters. His main research activities have been in the field of electronics transport, oxidation of silicon, MOS device physics, fluctuations and low-frequency noise, and dielectric reliability. Dr. Ghibaudo was or is a member of several technical/scientific committees of International Conferences (ESSDERC 93&99&03-06, WOLTE, ICMTS 96–2004, MIEL 95-2006, ESREF 96-98-00-03-04-05-06, SISC1996–2000, MIGAS, ULIS, IEEE/IPFA, ICMTD, FaN 2006, ICNF 2005). He was a Cofounder of the First European Workshop on Low Temperature Electronics (WOLTE ’94) and an Organizer of 12 Workshops/Summer School during the last ten years. He is also a member of the Editorial board of Solid State Electronics and Microelectronics Reliability Journals.