Thyristor Input-Protection Device Suitable for CMOS ... - Springer Link

Analog Integrated Circuits and Signal Processing, 43, 5–14, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.

Thyristor Input-Protection Device Suitable for CMOS RF IC’s JIN-YOUNG CHOI,∗ WOO SUK YANG, DONGMIN KIM AND YOUNGJU KIM School of Electrical, Electronic, & Computer Engineering, Hongik University, Jochiwon, Yongi Gun, Chungnam, 339-701, South Korea E-mail: [email protected]; [email protected]; [email protected]; [email protected]

Received July 14, 2003; Revised August 28, 2003; Accepted April 21, 2004

Abstract. Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF IC’s. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/45 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD. Key Words:

1.

ESD, protection, thyristor, CMOS, RF IC

Introduction

In recent years, there has been a strong trend to utilize standard CMOS processes for RF IC fabrication to benefit from their technological maturity and low cost. However CMOS chips are more vulnerable to electrostatic discharge (ESD) due to thin gate oxide used, and therefore protection devices such as NMOS transistors are required at input pads. Large device size is essential to reduce discharge current density and thereby to protect themselves against thermal-related problems, while providing ESD protection for internal circuits. Usage of large protection devices adds parasitic capacitances to the input nodes to generate another problems such as gain reduction and poor noise characteristics [1], which are critical in low noise amplifier designs, for example. To reduce the added capacitances, an ESD sensing technique was suggested [2], but still the added parasitic may be too large for RF applications. A distributed ESD protection scheme was suggested to utilize it for impedance matching purpose as well, which however is considered as useful for restricted applications due to larger area required [3]. To eliminate the ∗ Corresponding

author.

added parasitics, other solution was suggested, where an on-chip inductor is used without any active protection devices [1]. However this method is frequencydependent and therefore it may not be a proper solution against all possible ESD modes including human body model (HBM), machine model, and charged device model. Other researchers had suggested using a thyristor structure to reduce the protection device size and the related parasitics [4], which however should utilize a more expensive technology other than standard CMOS processes. Therefore solutions are still solicited for RF IC’s to really benefit from utilizing the CMOS technology. In this paper, based on simulation results and accompanying analysis, we suggest a pnpn thyristor structure suitable for implementation in standard CMOS processes to reduce the added parasitics while maintaining robustness against ESD. In Section 2, ESD protection mechanisms are explained and the relation between DC breakdown characteristics and transient discharge behavior referring to a simple protection scheme is discussed to show that ESD robustness of protection devices can be estimated from DC breakdown characteristics. Simulated DC breakdown characteristics of a suggested pnpn device structure are examined in

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comparison to those of a conventional NMOS protection transistor. In Section 3, characteristics of three variants are examined to define an optimal pnpn structure. In Section 4, AC device simulation results are given to estimate the amount of reduction in the parasitic capacitance value when utilizing the suggested protection device. Additional issues relating the device design are also discussed.

2.

NMOS Transistor vs. PNPN Thyristor Device

We first mention about the requirements of protection devices referring to HBM ESD events. Figure 1 shows an example of protection schemes, where one grounded-gate NMOS protection transistor (M1 ) is connected between the input node and the ground VSS , and the other protection NMOS (M2 ) is connected between VDD and VSS as a clamp device. When a positive ESD voltage is applied to the input pin relative to the VSS pin, the parasitic npn bipolar transistor in M1 limits the voltage applied to the gates of the internal circuits protecting them against ESD. When a negative ESD voltage is applied to the input pin relative to the VSS , the forward-biased pn (p-sub/n+ drain) diode in M1 limits the voltage. When a positive ESD voltage is applied to the input pin relative to the VDD pin, the parasitic npn bipolar transistor in M1 in series with the forward-biased pn diode in M2 limits the voltage. When a negative ESD voltage is applied to the input pin relative to the VDD , the npn bipolar transistor in M2 in series with the forward-biased pn diode in M1 limits the voltage.

Fig. 1. Simple ESD protection scheme utilizing NMOS protection transistors.

Therefore the protection scheme shown in Fig. 1 protects the internal circuits against all possible ESD combinations. However the protection device itself should be strong enough to sustain the large ESD current. The NMOS protection transistor can experience a severe stress when the drain-source voltage is positive, and the weakest point is known to be the region near the gate side of the n+ drain junction, where the product of the bipolar current density and the induced electric field is largest [5]. To reduce the current density, a large device width is mandatory, which is usually more than 400 µm. Reducing the DC holding voltage of the npn bipolar transistor is desirable to reduce the electric field and thereby alleviate thermal-related problems. The DC snapback voltage, where the parasitic npn bipolar transistor is triggered, represents the voltage applied between the gate and the substrate of the internal circuits at the ending stage of the ESD event, since the discharging current level through the NMOS protection transistor becomes too low to turn on the parasitic bipolar transistor. Therefore reducing the snapback voltage is also important to protect the internal circuits. Generally speaking, we can use DC breakdown characteristics of protection devices to estimate robustness of a protection scheme against ESD. Figure 2 shows the NMOS protection device structure chosen as a reference in this work. It represents a conventional protection device incorporating n+ source and drain ESD implants, which is implied by the relatively deep junctions. Considering the fact that the lattice heating during the most critical ESD incident peaks around the region near the gate side of the drain junction, the gate-drain contact spacing is chosen large as 3 µm to alleviate drain-contact melting problems, which is actually regarded as a minimal spacing [5]. Note that the added parasitic capacitance with this protection device attached to an input node comes mainly from the large n+ -drain/p-sub junction capacitance together with the gate-drain overlap capacitance. Table 1 summarizes the principal structure parameters. The n+ junctions shown in Fig. 2 are assumed to have a Gaussian doping profile with 1020 cm−3 of peak concentration. DC simulations were performed using the 2dimensional device simulator ATLAS [6], which is a commercial version of PISCESIIB, incorporating the lattice heating model including Joule heat, generationrecombination heat, and Peltier Thomson heat. The

Thyristor Input-Protection Device Suitable for CMOS RF IC’s

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Table 1. Principal structure parameters of the NMOS protection transistor. Parameters Effective channel length Gate oxide thickness Substrate and channel doping n+

drain depth, length

n+ source depth, length

Values 0.45 µm ˚ 75 A 1016 cm−3 , 1017 cm−3 0.3 µm, 3.38 µm 0.3 µm, 1.38 µm

Gate-drain contact spacing

3 µm

Gate-source contact spacing

1 µm

Fig. 3. Drain current vs. voltage characteristics of the NMOS transistor in a semi-log scale.

Fig. 2.

Cross section of the NMOS protection transistor.

source, the gate, and the substrate are grounded, and the drain bias is varied for simulation. Figure 3 shows the simulated drain current vs. voltage characteristics of the NMOS transistor in Fig. 2 in a semi-log scale. As shown in Fig. 3, when increasing the drain voltage, the leakage current through the reversebiased n+ -drain/p-sub junction increases slowly, and the junction starts to breakdown by avalanche when the drain voltage is increased to about 9.2 V. The generated hole current by avalanche flows to the substrate terminal to increase the body potential. With suffi-

cient hole current flowing, the body potential near the source junction gets high enough to forward-bias the n+ -source/p-sub junction triggering the parasitic lateral npn (source/body/drain) bipolar transistor. The source, body, and drain acts as the emitter, base, and collector, respectively. Generation of holes around the drain junction is augmented due to the impact ionization caused by the injected electrons from the source, and thereby the required drain-source voltage is reduced to show the snapback characteristics in Fig. 3. After the snapback, the drain-source voltage drops to 4.2 V of holding voltage. In this situation, the generated hole current near the high-field drain junction provides the base current to the lateral npn bipolar transistor. In Fig. 3, the 2nd breakdown [7] occurs when the drain current is about 6 × 10−4 A/µm, and the required drain-source voltage is reduced further to cause device failures relating drain-contact melting in real devices. The protection devices should not enter the 2nd breakdown regime during any ESD events. Therefore the current level where the 2nd breakdown occurs is an important measure for device failure. The simulation shows that the 2nd breakdown in the device

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Choi et al. Table 2. Principal structure parameters of the pnpn0 device. Parameters

Values

n+ anode depth, length

0.1 µm, 1 µm

p+ anode depth, length

0.1 µm, 0.8 µm

n+ cathode depth, length

0.1 µm, 0.8 µm

n well depth, length p substrate doping

Fig. 4.

Cross section of the pnpn0 protection device.

occurs when the peak lattice temperature exceeds about 850◦ K. Figure 4 shows the pnpn device structure suggested in this work. The device can be easily fabricated using standard CMOS processes, and does not incorporate ESD implant steps, which is implied by the relatively shallow junctions. We call this structure as the pnpn0 device, which is the one most optimized in performance compared to the other pnpn devices to be discussed later. In Fig. 4, the contacts in the n+ and p+ junction inside the n well are connected together to serve as the anode of the device, and the n+ junction outside the well serves as the cathode. This device can replace the NMOS protection transistor at the input in Fig. 1 by connecting its anode and cathode to the input pad and the ground, respectively. It is easy to show that this modified protection scheme also provides the discharging paths for all possible ESD combinations. Table 2 summarizes the principal structure parameters. The n+ and p+ junctions are assumed to have a Gaussian doping profile with 1020 cm−3 of peak concentration, and the n well is assumed similarly with 3 × 1017 cm−3 of peak concentration. The cathode and the substrate are grounded and the anode bias is varied for simulation.

1 µm, 4.3 µm 1016 cm−3

n well-cathode spacing

0.8 µm

n+

1.8 µm

anode −

p+

anode spacing

Figure 5 shows the simulated DC anode current vs. voltage characteristics of the pnpn0 device in Fig. 4 in a semi-log scale. As shown in Fig. 5, when increasing the anode voltage, the anode current increases slowly due to the leakage current through the reverse-biased nwell/p-sub. And then the anode current starts to increase noticeably when the anode voltage is increased above 7 V, which is confirmed as a result of punchthrough between the n well and the n+ cathode. The injected electrons from the cathode by punchthrough cause holes to be generated by impact ionization at the

Fig. 5. Anode current vs. voltage characteristics of the pnpn0 device in a semi-log scale.


reverse-biased n-well/p-sub junction, which flow to the p substrate increasing the body potential. As the anode voltage increases, with sufficient hole current flowing, the body potential near the cathode junction gets high enough to forward-bias the p-sub/ n+ -cathode junction triggering the lateral npn (n+ -cathode/p-sub/n-well) bipolar transistor. The n+ cathode, p substrate, and n well act as the emitter, base, and collector, respectively. At this situation, a snapback is monitored as indicated as the point A in Fig. 5. The bipolar current from the n+ anode flows through n-well, which decreases the potential of the region under the p+ anode by ohmic drop. When the bipolar current is large enough, the p+ -anode/n-well junction is forward-biased to trigger the pnpn (p+ anode/n well/p sub/n+ cathode) thyristor, which causes the another decrease in the anode voltage, as indicated as the point B in Fig. 5. The resulting holding voltage drops to about 1 volt, which is much smaller compared to that of the NMOS transistor in Fig. 3. It was confirmed that, in this situation, about 75% of the anode current flows through the p+ anode and the rest of the current flows through the n+ anode to support the pnpn thyristor action. In Fig. 5, the 2nd breakdown occurs when the anode current is about 94×10−4 A/µm, which is about 16 times of that in the NMOS transistor. The simulation shows that the 2nd breakdown occurs when the peak lattice temperature exceeds about 850◦ K again. When examining the temperature distribution of the device near the 2nd breakdown, it shows that the peak temperature occurs in the relatively large n-well area near the n+ anode junction, where the product of the current density and the electric field is largest. Lattice heating near the forward-biased p+ anode is restrained since the electric field strength is low there even though the current density is high. The result mentioned above implies that the width of the pnpn protection device required to provide a similar level of ESD robustness can only be 1/16 of that Table 3.

of the NMOS protection device, which can reduce the added parasitic capacitance a lot. Note that the added parasitic capacitance comes mainly from the n-well/psub junction capacitance. It is anticipated that heating of the n+ anode contact can be further reduced by increasing the n+ anode junction length and/or depth. The longer junction helps to decrease the current density, and the deeper junction helps to reduce contact heating. Increasing the junction length will increase the overall n-well area and therefore the associated junction capacitance will increase accordingly.

3.

Structural Dependencies

In this section, we examine the variations in device characteristics with varying device structure. We define three variants, the pnpn1, pnpn2, and pnpn3 devices, and compare the characteristics of them to those of the pnpn0 device to define the optimal device structure. By moving the location of the p+ anode to the left, the pnpn1 device has a decreased distance between the n+ anode and the p+ anode when compared to the pnpn0 device. The pnpn2 device has an increased distance between the n well and the cathode when compared to the pnpn0 device. The pnpn3 device is identical to the pnpn0 device except that it has the n+ anode and the p+ anode interchanged in location. Table 3 compares the differences in device structures. We first examine the characteristics of the pnpn1 and pnpn2 devices, and look at the pnpn3 device later. Figure 6(a) shows the anode current vs. voltage characteristics of the pnpn0, pnpn1, and pnpn2 devices in comparison in a semi-log scale. Figure 6(b) shows the characteristics in a linear scale. In Fig. 6(b), we can see that decreasing the distance between n+ anode and p+ anode (S1 ) has an effect to increase the current level, where the pnpn thyristor is triggered. As S1 decreases, the voltage drop between the n+ anode and p+ anode is

Comparison of the structure parameters of pnpn devices.

Name

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pnpn0

pnpn1

pnpn2

pnpn3

Distance between n+ anode and p+ anode (S1 )

1.8 µm

0.6 µm

1.8 µm

Same as pnpn0, but n+ anode and p+ anode interchanged

Distance between n-well and n+ cathode (S2 )

0.8 µm

0.8 µm

1.8 µm

Overall device length

6.0 µm

6.0 µm

7.0 µm

Parameter

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reduced while the npn bipolar transistor current is flowing, and thereby more current is needed to forward-bias the p+ -anode/n-well junction large enough to trigger the pnpn thyristor. After the thyristor being triggered, the pnpn1 device requires more current through the n+ anode to sustain the thyristor on, which will increase lattice heating around the n+ anode junction. The corresponding holding voltage gets somewhat larger, and the current level where the 2nd breakdown occurs drops significantly as listed in Table 4. From Fig. 6(a) and (b), we can also see that increasing the distance between n well and n+ cathode (S2 ) has an effect to increase the snapback voltage. As S2 increases, punchthrough ceases to occur and the bipolar transistor is triggered by breakdown of the reverse-biased n-well/p-sub junction, which requires much higher voltage, near 50volt in the pnpn2 device. This device will certainly have a high anode voltage at the ending stage of the ESD event, which is bad for internal circuit protection. Figure 7 shows the peak lattice temperature vs. anode current characteristics of the devices. Decreasing S1 significantly enhances lattice heating in the pnpn1 device as shown in Fig. 7, which significantly lowers the current level where the 2nd breakdown occurs.

Fig. 6. Anode current vs. voltage characteristics of the pnpn0, pnpn1, and pnpn2 devices, (a) in a semi-log scale, (b) in a linear scale.

Fig. 7. Peak lattice temperature vs. anode current characteristics of the pnpn0, pnpn1, and pnpn2 devices.

Thyristor Input-Protection Device Suitable for CMOS RF IC’s Table 4. Device name

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Principal parameters of the protection devices. Snapback voltage

Holding voltage

Current at the 2nd breakdown

Added capacitance to the input

NMOS

9.4 V

4.20 V

0.0006 A/µm

3.39 fF/µm

pnpn0

16.8 V

1.01 V

0.0094 A/µm

1.22 fF/µm

pnpn1

16.8 V

1.08 V

0.0065 A/µm

pnpn2

45.2 V

1.06 V

0.0087 A/µm

pnpn3

16.8 V

1.46 V

0.0038 A/µm

The pnpn2 device also has somewhat worse characteristics compared to the pnpn0 device in terms of lattice heating. It is worth noting that the characteristics in Fig. 7 show temperature peaking at a low current level, which is a result of lattice heating by the bipolar transistor current flowing before the thyristor is triggered. The lattice temperature drops as soon as the thyristor is triggered since the anode voltage drops. Table 4 summarizes the principal characteristic parameters, which are critical for ESD robustness of the protection devices. Those of the NMOS protection device are also shown for comparison. In Table 4, the holding voltage of the pnpn device is defined as the anode voltage where the anode current is 2 mA/µm, just for comparison purpose. We now consider the characteristics of the pnpn3 device, whose structure is identical to the pnpn0 device structure but with the n+ and p+ anodes interchanged in location. Figure 8 shows the simulated anode current vs. voltage characteristics of the pnpn0 and pnpn3 devices in a semi-log scale. As shown in Fig. 8, the snapback characteristics are same for two devices since the device structures outside the n well are same. However the current level, where the pnpn thyristor is triggered, is increased significantly when interchanging the location of two anode junctions. In the pnpn3 device, the n+ anode is located at the right hand side of the p+ anode, and therefore it is difficult to lower the potential of the region under the p+ anode and thereby forward-bias the p+ -anode/n-well junction while the bipolar transistor current is flowing. Therefore a larger current is needed to trigger the thyristor. After the pnpn thyristor is triggered, the resulting holding voltage is also increased to support the thyristor action with a larger portion of the anode current flowing through the n+ anode rather than through the p+ anode. It was confirmed that the

Fig. 8. Anode current vs. voltage characteristics of the pnpn0 and pnpn3 devices in a semi-log scale.

lattice heating at the same current level is increased significantly. The resulting current level where the 2nd breakdown occurs is reduced a lot as listed in Table 4. It is very clear that interchanging the anode locations has a fatal effect in terms of ESD robustness of the pnpn device. 4.

Discussions

The analysis in Section 3 defines the optimum device structure for the suggested protection device. Locating

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the n+ anode to the left of the p+ anode is very important. Increasing the distance between the n+ and p+ anodes has a desirable effect by facilitating the thyristor triggering, which however tends to increase the added parasitic capacitance due to the increased nwell junction area. It is important to decrease the distance between the n well and the n+ cathode to utilize the punchthrough phenomenon and tune the snapback voltage to a wanted value, which changes the device length, however without increasing the added parasitic capacitance. Recall that the snap voltage represents the voltage applied between the gate and the substrate of the internal circuits at the ending stage of the ESD event. Using ATLAS, we performed some mixed-mode transient simulations set up for a HBM test situation to confirm the feasibility of the suggested device. Figure 9 illustrates the set up. The 1.5 K of resistor and the 100 pF capacitor are the standard-valued components for a HBM test. Cgate simulates the gate oxide capacitor of the internal buffer, and Rline the metal-line resistance. L s , Cs , and Ct represent the parasitic elements added by the test environment. The switch S1 charges the 100 pF capacitor to a specified voltage Vs , and then S2 initiates the discharge. We confirmed the robust discharging behavior of the pnpn0 device in accordance with the DC analysis results. However additional information was found from the mixed-mode analysis. From the DC simulation results of the pnpn0 device, we found that the peak temperature point is the n-well area near the n+ anode junction. However the mixedmode simulation results show that lattice heating is the most near the n+ cathode junction. We figured out that in the early stage of ESD event the discharging current level is quite higher than that in the DC simulations. A lot more current flows through the pnpn thyristor when

Fig. 9.

Mixed-mode simulation set up for a HBM test.

compared to the DC simulation results. Therefore the current density near the cathode junction is quite higher than that near the n+ anode even though the electric field near the n+ anode junction is higher, which results in more lattice heating near the cathode junction. The current density in the n-well area near the p+ anode is also high, but the well doping there is higher than that in the p substrate, and therefore the lattice heating there is lower. The weakest points in contact-melting problems in order are the cathode, the n+ anode, and the p+ anode. Therefore increasing the n+ cathode area and/or depth seems also important, which will increase the overall device length, however without increasing the added parasitic capacitance. We also performed AC simulations using ATLAS to compare the magnitude of the added parasitic capacitance with the suggested pnpn0 device to that with the NMOS transistor. The results are listed in the last row of Table 4. As mentioned in Section 2, the added parasitic capacitances with the pnpn devices are all the same since the added parasitic capacitance comes mainly from the n-well/p-sub junction capacitance and the nwell/p-sub junction remains unchanged. The parasitic capacitance per unit device width with the NMOS device in Fig. 2 is 3.39 × 10−15 F/µm, while that with the pnpn0 device is 1.22 × 10−15 F/µm, which is about 1/2.8. From the DC simulation results, we showed that the device width of the pnpn0 device required to provide a similar level of ESD robustness is only 1/16 of the NMOS device width. This implies that the added parasitic capacitance with the pnpn0 device will be only 1/45 of that resulting when using the NMOS protection device. However as mentioned in the above, we need to increase the n+ anode junction length somewhat, which will increase the capacitance accordingly. Also considering the temperature increase near the cathode junction, we may need some more device width, which will reduce the difference between the added parasitic capacitances of the two devices. However the difference will be still quite large, which implies that the advantage of using the suggested pnpn device is really beneficial. The proposed device connected between the input node and VSS does not cause a latch-up problem since the pnpn path does not exist between VDD and VSS . However if the proposed device is used as the clamp device illustrated in Fig. 1, it may cause a latch-up problem in normal operation conditions. Therefore it will be safer to use the conventional NMOS protection transistor as the clamping device. Fortunately adding


a large capacitance between the power buses gives no harm.

5.

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rameters.” IEEE Trans. Electron Devices, vol. 38, pp. 2161–2168, Sep. 1991.

Summary

We suggested a pnpn thyristor protection device, which can be easily implemented utilizing the standard CMOS processes. Based on 2-dimensional device simulations, we compared the DC breakdown characteristics of the suggested device to those of the conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements were demonstrated and the corresponding mechanisms were explained. Structure dependencies were examined to define the optimal structure and provide a guideline for device design. The mixed-mode transient simulations were performed to support the DC analysis results. The AC simulation results were introduced to estimate the magnitude of the reduction in the added parasitic capacitance when using the suggested device for ESD protection. Adopting the suggested devices for ESD protection in CMOS RF IC’s is expected to reduce the parasitic capacitance added to the input node considerably while maintaining robustness against ESD.

Jin-Young Choi was born in Seoul, Korea in 1956. He received the B.S. degree in electrical engineering from the Seoul National University, Korea, in 1979, and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, USA, in 1986 and 1991, respectively. In 1991, he joined Samsung Electronics Memory Division, Korea, where he was engaged in high-speed SRAM development. In 1992, he moved to the Hongik University, Jochiwon, Korea, where he is now an associate professor. His recent research interests include the high-frequency modeling of CMOS devices, CMOS RF circuit design, and analysis & design for ESD protection.

References 1. P. Leroux and M. Steyaert, “High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection.” Electronics Letters, vol. 37, pp. 467–469, March 2001. 2. M.-D. Ker, T.-Y, Chen, C.-Y. Wu, and H.-H. Chang, “ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications.” IEEE J. SolidState Circuits, vol. 36, pp. 1104–1199, Aug. 2000. 3. B. Kleveland, T.J. Maloney, I. Morgan, L. Madden, T.H. Lee, and S.S. Wong, “Distributed ESD protection for high-speed integrated circuits.” IEEE Electron Devices Lett., vol. 21, pp. 390–392, Aug. 2000. 4. H. Feng, K. Gong, and A.Z. Wang, “A comparison study of ESD protection fro RF IC’s: Performance vs. parasitics,” in IEEE MTT-S Digest, 2000, pp. 143–146. 5. S. Aur, A. Chatterjee, and T. Polgreen, “Hot-carrier reliability and ESD latent damage.” IEEE Trans. Electron Devices, vol. 35, pp. 2189–2193, Dec. 1988. 6. ATLAS II Framework, Version 5.0.0.R, Silvaco International, 1999. 7. A. Amerasekera, L. van Roozendaal, J. Bruines, and F. Kuper, “Characterization and modeling of second breakdown in nMOST’s for extraction and ESD-related process and design pa-

Woo Suk Yang was born in Seoul, Korea in 1957. He received the B.S. degree in electrical engineering from the Seoul National University, Korea, in 1979, and the Ph.D. degree in electrical and computer engineering from the North Calorina State University, USA, in 1990. His doctorial research was in the area of signal processing. In 1990, he joined LG Electronics Co. Korea. In 1991, he moved to the Hongik University, Jochiwon, Korea, where he is now a professor. His recent research interests include the high-frequency modeling and various topics in signal processing area.

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Dongmin Kim was born in Korea in 1956. He received the B.S. and M.S. degrees in electrical engineering from the Seoul National University, Korea, in 1979 and 1984, respectively and the Ph.D. degree in ECE from the University of Michigan, USA, in 1996. Now, he is an assistant professor of the Hongik University, Jochiwon, Korea. His recent research interests include circuit design and analysis.

Youngju Kim was born in Seoul, Korea in 1957. He received the B.S. and M.S. degrees in electrical engineering from the Seoul National University, Korea in 1980 and 1985, respectively and the Ph.D. degree in electrical engineering from the Polytechnic University of New York, USA, in 1995, respectively. In 1996, he joined the Hongik University, Jochiwon, Korea, where he is now an assistance professor. His recent research interests include the RF circuit design and LIN wireless systems.