Transceiver with inductive coupling for wireless chip

Microelectronics Journal 44 (2013) 852–859

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Transceiver with inductive coupling for wireless chip-to-chip communication using a 50-nm digital CMOS process$ Changhyun Lee a, Jonghoon Park a, Jinho Yoo a, Hyungjun Cho b, Jungi Choi c, Jeongho Cho b, Changkun Park a,n a

School of Electronic Engineering, College of Information Technology, Soongsil University, 551 Sangdo-Dong, Dongjak-Gu, Seoul 156-743, Republic of Korea Advanced Product Engineering Team, DRAM Development Division, SK Hynix Inc., 2091 Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, Republic of Korea c Advanced Design Team, DRAM Development Division, SK Hynix Inc. 2091 Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, Republic of Korea b

art ic l e i nf o

a b s t r a c t

Article history: Received 7 November 2012 Received in revised form 25 July 2013 Accepted 26 July 2013 Available online 13 August 2013

A wireless type of chip-to-chip communication (WCC) technology is proposed as the next generation of 3D semiconductor technology. To demonstrate the feasibility of this technology, we designed a coil, transmitter and receiver for wireless chip-to-chip communication using a 50-nm digital CMOS process. The coil is designed using inductive coupling with design parameters that include the number of turns, the metal width, and the space between adjacent metal lines. A differential transceiver structure is proposed for the WCC technology. The transmitter of the transceiver acts as a termination and bias circuit for the receiver while the transceiver is operating as a receiver. The receiver is designed with a typical differential amplifier and a latch to recover the transmitted original digital signal. The proposed transceiver and coil for the proposed WCC technology is implemented using commercial 50-nm digital CMOS technology. Experimental results successfully demonstrate the feasibility of the WCC technology. & 2013 The Authors. Published by Elsevier Ltd. All rights reserved.

Keywords: 3D semiconductor Coil LATCH Wireless communication

1. Introduction Recently, three-dimensional (3D) semiconductors have been studied vigorously as researchers seek to reduce system sizes and enhance operating frequencies. While the 2D semiconductor shown in Fig. 1(a) serves to interconnect each of the other chips in the two-dimensional plane via a PCB line, the 3D semiconductor technology uses vertically stacked multi-chips. Because data or signal transmission is performed through a bonder-wire and PCB line for the 2D semiconductor technology as shown in Fig. 1(b), the inductance established by the bonder-wire and PCB line limits the data or signal transmission speed. Even when the signal processing speed increases continuously, the offchip characteristics, for example the bonder-wire and the PCB inductance, determine the speed of the system overall. The 3D semiconductor was introduced to solve the problems associated with the 2D semiconductor described above. The physical path between the I/O PADs of each chip can be minimized compared to 2D semiconductor cases. In general, because there are no PCB lines between the chips, there is therefore no parasitic

☆ This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. n Corresponding author. Tel: +82 2 822 7155. E-mail address: [email protected] (C. Park).

inductance created by the PCB lines to enhance the signal or data transmission speed of the entire system. Typically, there are two types of 3D semiconductor technologies: multi-chip-package (MCP) technology and through-siliconvia (TSV) technology. Detailed descriptions, including the pros and cons of each, are given in Section 2 below. In this work, we propose wireless chip-to-chip communication technology which mitigates the disadvantages of conventional 3D semiconductor technologies using 50-nm digital CMOS technology. The proposed technology is described in Section 3. In Section 4, the structure of the transceiver component of the proposed technology is described. Finally, we verify the feasibility of the proposed technology experimentally, as discussed in Section 5.

2. Typical 3D semiconductors 2.1. Multi-chip package (MCP) technology MCP technology is one of the most commonly used types of 3D semiconductor technologies. MCP technology has been adapted to commercial DDR2 and DDR3 memory products. Fig. 2(a) shows the typical processes of MCP technology. The several chips are stacked vertically and the signal and power supply PADs of each chips are connected to a printed circuit board (PCB) using several bonderwires to communicate with each other, as shown in Fig. 2(a).

0026-2692/$ - see front matter & 2013 The Authors. Published by Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.07.006

C. Lee et al. / Microelectronics Journal 44 (2013) 852–859

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Fig. 1. 2D semiconductor: (a) conceptual diagram and (b) parasitic components.

parasitic capacitance C induced by the transistors of the I/O circuit of the chip generate LC resonance. As shown in Fig. 2, given that the number of LC resonators connected to a single node is proportional to the number of stacked chips, the transmitted signal or data experiences various resonance frequencies, which degrade the quality of these signals or data. As described above, although MCP technology has a number of advantages compared to typical 2D semiconductor technology, several factors can degrade the data or signal quality and limit the data transmission speed. 2.2. Through silicon via (TSV) technology

Fig. 2. MCP technology: (a) conceptual diagram and (b) parasitic couplings and undesired resonators.

The advantages of MCP technology compared to a typical 2D semiconductor are the compact size of the system and the absence of inductance induced by the PCB lines to enhance the data transmission speed. However, as MCP technology uses many long bonder-wires, as shown in Fig. 2(a), the inductances of the bonder-wires limit the data transmission speed, and the inductive and capacitive interactions between adjacent bonder-wires distort the data, as shown in Fig. 2(b). Additionally, the bonder-wire inductance L and the

Recently, TSV technology has been studied intensely in different digital semiconductor industries to solve the problems related to MCP technology as described above [1–4]. TSV technology uses a ‘via’, through which data communication is possible between the top and bottom chips of this component, as shown in Fig. 3. Using TSV technology, the inductances induced by the PCB lines are therefore removed during the communication of data between stacked chips. This enhances the data transmission speed compared to MCP technology. The problems of LC resonance and interaction between adjacent wires associated with MCP technology are removed due to the absence of long bonder-wires in TSV technology However, for TSV technology, the required additional process development cost is expensive. Additionally, even if the process was to be developed successfully, the low yield of TSV may become a serious problem. In fact, cracking of the TSV material is a crucial obstacle for the mass production. As described above, although TSV technology solves various problems associated with 2D semiconductor and MCP technologies, there are problems related to the development cost and the low yield of this technology. 3. Wireless chip-to-chip communication (WCC) technology In this study, we propose wireless chip-to-chip communication technology which can solve various problems arising from the use of

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Fig. 3. TSV technology: (a) conceptual diagram and (b) cross-section.

2D semiconductor, MCT, and TSV technologies. The proposed WCC technology represents the next generation of technology for 3D semiconductors. As described above, the 2D semiconductor, MCP, and TSV technologies maintain communication by wire for data transmission. For wire communications, the 2D semiconductor, MCP, and TSV technologies use PCB lines, bonder-wires, and silicon vias, respectively. However the proposed WCC technology relies instead on inductive coupling for data transmission. There are therefore no PCB lines, bonder-wires, or silicon vias to generate a low data transmission speed, increase the development cost, or generate low yields. Fig. 4 shows the concept of the proposed WCC technology. As shown in the figure, several chips are attached vertically to form a stacked-chip structure. Data communication is performed by means of inductive coupling in WCC technology. A bonder-wire or silicon via can be adapted for the power supply and the ground. However, because the power supply and ground are not data components but DC components, there are no problems arising from the bonder-wire and the silicon via, as described above for data communication. Thus, the proposed wireless chip-to-chip communication method can serve as a solution to realize high-speed I/O.

Fig. 4. WCC technology: (a) conceptual diagram and (b) applications for multi-chip solutions.

4. Design of the proposed wireless chip-to-chip communication transceiver We devised a transceiver to verify the feasibility of the proposed wireless chip-to-chip technology. The transceiver is designed with a differential structure using commercial 50-nm digital CMOS technology. We describe the proposed transceiver for the proposed WCC technology using four separate sections, as follows: (A) transmitter, (B) receiver, (C) whole transceiver, and (D) inductive coupling coil.

4.1. Transmitter The transmitter for the WCC technology is designed using differential structure. The load for the transmitter is designed with an inductor pattern and the final stage of the transmitter is function as an inverter type.

Fig. 5. Simplified schematic of the transmitter for the proposed WCC technology.

(1) Operating as a transmitter. If the TxENV signal becomes ‘HIGH’, the transmitter part shown in Fig. 5 is vitalized. The input data, VIN+ and VIN , can then drive the final stage of the transmitter. (2) Operating as a termination point. If the TxENV signal becomes ‘LOW’, the transmitter part shuts down and the input data VIN+ and VIN cannot drive the final stage of the transmitter. However, if the ODTENV signal becomes ‘HIGH’, all of the pull-up (PU) parts and pull-down (PD) parts are


Fig. 6. Simplified schematic and voltage waveforms of the receiver.

Fig. 7. Simplified schematic of the entire transceiver.

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turned on and the voltage of the output node, which should be the input node for the receiver, becomes half of the VDD on the assumption that the on-resistances of the PU and PD parts are identical to each other. In contrast, if the ODTENV signal becomes ‘LOW’, all of the PU parts and PD parts are turned off and the voltage of the output node, which should be the input node for the receiver, becomes the floating node.

Key design parameters for the transmitter are the total gate width of the main driver transistor, which determines the current strength entered into the inductor. In this work, we designed the main driver transistor with an on-resistance of 34 Ω, which is a general specification in the DDR3 I/O design. The resistors in the main driver are used to meet the required linearity of the main drivers. 4.2. Receiver

Table 1 Function according to the transceiver operation. Physical block

Transmitter Receiver

Operates as Transmitter

Receiver

Enable Disable

Termination Enable

A schematic of the proposed receiver is shown in Fig. 6. If the RxENV signal, which is reciprocal to the TxENV signal, becomes ‘HIGH’, the sink transistors are turned on and the receiver of the transceiver is vitalized. During the receiver operation of the transceiver, the transmitter acts as the bias circuit for the first amplifier stage of the receiver so as to amplify the signal entering through the coil effectively. The signal entering through the coil is amplified at the first amplifier stage, which is a typical differential type of amplifier. The amplified signal then enters into a latch to

Fig. 8. Designed inductive coupling coil for the proposed WCC technology.

Fig. 9. Cross-section of the substrate used for the 2.5D EM simulations.


recover the original digital signal [5–9]. We locate the typical amplifier as the first amplification stage and the latch as the second amplification stage because if the input signal of the latch is weak, the probability of recovering the original signal may be degraded. The node voltage waveforms are presented in Fig. 6.

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the transceiver operates. Additionally, the Tx part functions as the termination of the receiver input. The operations of the transmitter and receiver according to the functions of the transceiver are summarized as Table 1. In our transceiver, termination using the transmitter to receive the data from the coil is used as the bias voltage of the first amplifier of the receiver.

4.3. Whole transceiver Fig. 7 shows a simplified depiction of the overall transceiver architecture for the designed WCC technology. In our transceiver, data can be transmitted and received through a single coil. (1) Operating as a transmitter. If a Tx-enable signal is entered into the transceiver, the Rx function of the transceiver is turned off and only the transmitter part of the transceiver operates. The circuit for the Rx building block therefore has Rx enable/disable switches. (2) Operating as a receiver. If an Rx-enable signal is entered into the transceiver, the Tx function of the transceiver is turned off and the receiver part of

Fig. 10. Simulated maximum available gain (MAG) of the coils.

Fig. 12. Experiment results: entered input voltage waveform and transferred output voltage waveform using the chip-to-chip wireless communication method (VDD ¼2.0 V).

Fig. 13. Experiment results: duty cycles according to the CLK period.

Fig. 11. Measurement setup for chip-to-chip wireless communication.

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Fig. 14. Experiment results according to the gate bias of the first amplification stage (VDD ¼2.0 V): (a) successful case, (b) partial failure case, and (c) failure case.

4.4. Inductive coupling coil The coil is designed using a differential structure, as shown in Fig. 8. A 2.5D EM-simulation is used to determine the performance of the coil. The physical substrate information is used for the 2.5D EM simulation. Because the 50-nm digital CMOS process used here has two metal layers, simplified substrate layer information for the 2.5D EM-simulation is established, as shown in Fig. 9. In Fig. 9, one of the two coils belongs to the bottom chip and the other coil belongs to the top chip. The coils are designed with a M2 layer to minimize the eddy currents generated at the substrate under the inductor pattern. A M1 layer is used partially where the metal lines cross over. However, the usage of an M1 layer is minimized to prevent the degradation of the quality factor of the inductor pattern induced by the ‘via’ which connects the M1 and M2 layers. In general, the resistance of the ‘via’ is on the order of tens of ohms (Ω). Various EM simulations according to the distance between the two coils are performed while controlling the parameter entitled ‘Distance’ in Fig. 8. As shown in Fig. 8, the inductor pattern of the coil is designed with a symmetric structure to ensure the differential operation of the transmitter and receiver circuits. The key design parameters for the inductor pattern are as follows: a metal width of 2.6 μm, a spacing distance between adjacent metal lines of 0.8 μm, eight turns, and a default distance of 50 μm. Most of the design parameters for the inductor pattern are determined in consideration of the process design rules. The remaining key parameter for the pattern of the outer size is determined from the overall simulation results. Our final goal as regards the outer size is to make it identical to the typical PAD size used in the IC for typical memory. To check the losses of the coils itself, the maximum avail gain (MAG) of the coils with outer size of 80 80 μm2 were simulated as shown in Fig. 10. The inductor pattern was designed using a 2.5D electromagnetic simulation to extract the s4p files. The maximum available gain, quality factor, S11, S22, S21, and other parameters are simulated using the extracted s4p files to search for the optimum design parameters. In general, the maximum available gain is proportional to the outer size and the number of turns and is inversely proportional to the distance between the chips and the spacing between adjacent metal lines [10–14].

5. Experimental results Fig. 11 shows the pin setup for chip-to-chip wireless communication. In our measurement, two identical chips are used. One of the chips was operated as the receiver and the other was operated as the transmitter. The roles of the receiver or transmitter are determined using RxEVN and TxENV pins. There are no wire connections between the two chips. The clock (CLK) signal is used as the input signal and the VOUT of the receiver is measured. We fabricated the proposed transceiver and coil for the proposed WCC technology using a 50-nm digital CMOS process. Two metal

Fig. 15. Experiment results according to the gate bias voltage of the first amplification stage: (a) successful case, (b) partial failure case, and (c) failure case.

layers are provided for the CMOS process. Fig. 12 shows the input and output voltage waveforms using the chip-to-chip wireless communication method. From the experimental results, the possibility of wireless chip-to-chip communication was verified. Fig. 13 shows the measured duty cycles according to the CLK periods. The duty cycle is distorted when the CLK period is shorter than 1.6 μs. However, distortion is induced by the wire inductance and by the capacitance of the measurement equipment. Thus, a proper measurement method must be developed to improve the measurement accuracy at a high-speed data rate. Fig. 14 shows the output voltage waveforms according to the gate bias of the first amplification stage at the receiver. The gate bias is one of the most critical parameters to determine successful wireless communications. The ‘PASS ZONE’ of the gate bias is summarized in Fig. 15. From the experimental results, the ‘PASS ZONE’ is expanded as the supply voltage increases. For this measurement, the ODTENV of the Rx part of the chip is set to ‘LOW’ to make the input node of the first amplification stage a floating input node.

6. Conclusion In this work, we proposed a type of wireless chip-to-chip communication (WCC) technology as the next generation of 3D semiconductor technology. Coil and transceiver blocks are designed and implemented using the commercial 50-nm digital CMOS process. The coil and transceiver are designed using a differential structure. The possibility of the technology is proved experimentally.

Acknowledgments This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2012–044627).


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