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JOURNAL OF APPLIED PHYSICS 97, 064505 共2005兲

Transparent thin-film transistors with zinc indium oxide channel layer N. L. Dehuff, E. S. Kettenring, D. Hong, H. Q. Chiang,a兲 and J. F. Wager School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, Oregon 97331-3211

R. L. Hoffman Hewlett-Packard Company, 1000 NE Circle Boulevard, Corvallis, Oregon 97330-4239

C.-H. Park and D. A. Keszler Department of Chemistry, Oregon State University, Corvallis, Oregon 97331-4003

共Received 10 September 2004; accepted 5 January 2005; published online 11 March 2005兲 High mobility, n-type transparent thin-film transistors 共TTFTs兲 with a zinc indium oxide 共ZIO兲 channel layer are reported. Such devices are highly transparent with ⬃85% optical transmission in the visible portion of the electromagnetic spectrum. ZIO TTFTs annealed at 600 °C operate in depletion-mode with threshold voltages −20 to −10 V and turn-on voltages ⬃3 V less than the threshold voltage. These devices have excellent drain current saturation, peak incremental channel mobilities of 45–55 cm2 V−1 s−1, drain current on-to-off ratios of ⬃106, and inverse subthreshold slopes of ⬃0.8 V / decade. In contrast, ZIO TTFTs annealed at 300 °C typically operate in enhancement-mode with threshold voltages of 0 – 10 V and turn-on voltages 1 – 2 V less than the threshold voltage. These 300 °C devices exhibit excellent drain–current saturation, peak incremental channel mobilities of 10– 30 cm2 V−1 s−1, drain current on-to-off ratios of ⬃106, and inverse subthreshold slopes of ⬃0.3 V / decade. ZIO TTFTs with the channel layer deposited near room temperature are also demonstrated. X-ray diffraction analysis indicates the channel layers of ZIO TTFTs to be amorphous for annealing temperatures up to 500 °C and polycrystalline at 600 °C. Low temperature processed ZIO is an example of a class of high performance TTFT channel materials involving amorphous oxides composed of heavy-metal cations with 共n − 1兲d10ns0 共n 艌 4兲 electronic configurations. © 2005 American Institute of Physics. 关DOI: 10.1063/1.1862767兴 I. INTRODUCTION

Amorphous zinc indium oxide 共ZIO兲 is emerging as a commercially viable transparent conducting oxide because of its excellent optical transmission, high electrical conductivity, chemical stability, thermal stability, film smoothness, and low compressive stress.1–6 The purpose of the work reported herein is to demonstrate the utility of ZIO as a channel material for transparent thin-film transistor 共TTFT兲 applications. Most TTFTs reported to date have employed polycrystalline ZnO as a channel material.7–15 Recently, materials such as a single crystal InGaO3共ZnO兲5 superlattice,16 polycrystalline SnO2,17 and amorphous zinc tin oxide18 have emerged as alternative TTFT channel layer options. Zinc tin oxide and ZIO constitute two members of a class of TTFT channel materials involving amorphous oxides composed of heavy-metal cations with 共n − 1兲d10ns0共n 艌 4兲 electronic configurations.18–21 II. EXPERIMENTAL TECHNIQUE

ZIO TTFTs are prepared on Nippon Electric Company glass substrates 共NEG OA2兲 coated with a 200 nm sputtered indium tin oxide 共ITO兲 gate electrode film and a 220 nm atomic layer deposited superlattice of AlOx and TiOx 共ATO兲.22 The ITO and ATO layers constitute the gate contact a兲

Author to whom correspondence should be addressed; electronic mail: [email protected]

0021-8979/2005/97共6兲/064505/5/$22.50

and insulator, respectively, of a bottom-gate TTFT. The ZIO channel layer 共typically ⬃85 nm兲 is deposited by rf sputtering, using a target purchased from Cerac, Inc. 共ZnO: In2O3 molar ratio is 2:1兲. Three different process recipes are employed for the ZIO channel layer deposition, as specified in Table I. ITO 共typically ⬃250 nm兲 source and drain electrodes are deposited via rf magnetron sputtering in Ar 共100%兲. Both the ZIO channel and the ITO source and drain electrodes are deposited with no intentional heating of the substrate. After ITO source/drain deposition, devices are furnace annealed in air at either 300 or 600 °C for 1 hour; alternatively, the room temperature 共RT兲 devices are not subjected to a post-deposition anneal. Six devices with W / L = 7100 ␮m / 1500 ␮m 共⬃4.7/ 1兲 are fabricated on each TABLE I. rf sputtering and post-deposition annealing process parameters for the three types of zinc indium oxide channel layers used in the fabrication of transparent thin-film transistors. RT indicates near room temperature, indicating that no intentional substrate heating or post-deposition annealing is employed. Anneal temperature 共°C兲 Ar gas flow 共sccma兲 O2 gas flow 共sccma兲 Target–substrate distance 共cm兲 Pressure 共mTorr兲 Power density 共W cm−2兲 a

600

300

RT

30 3 7.5 5 2.5

45 2 7.5 5 2.5

15 5 10 1–2 4.9

Standard cubic centimeters per minute.

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FIG. 1. XRD patterns obtained from ⬃200– 250 nm zinc indium oxide thin films deposited by rf sputtering. The RT sample is not annealed, whereas the 500 and 600 °C samples are post-deposition furnace annealed. The RT and 500 °C samples are amorphous, while the 600 °C sample has transformed into a crystalline form. 共Inset兲 Optical transmittance through the channel region of a ZIO TTFT.

1 in. ⫻ 1 in. glass substrate. Channel and source/drain electrode layers are patterned through the use of shadow masks. An alternative process utilizing photolithography patterning yields devices with channel lengths as small as 25 µm and electrical performance similar to that of shadow maskpatterned devices. X-ray diffraction data are obtained by using Cu K␣ radiation on a Rigaku R-Axis Rapid diffractometer, which is equipped with a curved imaging plate. The radiation is directed through a 0.3 mm pinhole collimator onto the sample at an incident angle of 10° relative to the face of the substrate. Data are corrected for the scattering from the substrate. III. RESULTS AND DISCUSSION A. Optical transmittance and x-ray diffraction

The optical transmittance through the channel region of a ZIO TTFT is shown in the inset of Fig. 1. The average transmittance in the visible portion of the electromagnetic spectrum 共400–700 nm兲 is ⬃85%; this value represents raw transmission through the entire structure, including the substrate, i.e., the measured transmission is reduced by both absorption and reflection. As seen in Fig. 1, x-ray data are consistent with amorphous 共or nanocrystalline兲 films for annealing at temperatures as high as 500 °C. In the patterns from the films produced at RT and annealed at 500 °C the broad peak near 32° corresponds to scattering at dimensions representing metal– metal interatomic distances, while the peak near 58° corresponds to metal–oxygen interatomic distances. Clearly, at 600 °C the film has transformed into a crystalline form. There is no evidence in the pattern to indicate that separate phases of ZnO and In2O3 have crystallized from the amorphous precursor. The pattern has been compared with those of all known phases in the ZnO– In2O3 system,23–25 but no simple match to these phases can be made. This result may not be too surprising, as all of the known materials have been produced from bulk reactions at temperatures above 1000 °C. Based on x-ray data shown in Fig. 1 and the Scher-

J. Appl. Phys. 97, 064505 共2005兲

FIG. 2. Drain current–drain voltage 共ID – VDS兲 characteristics of a TTFT in which the ZIO channel layer is subjected to a 600 °C post-deposition furnace anneal. VGS is decreased from 0 V 共top curve, showing maximum current兲 to −10 V in 2 V steps. TTFTs processed at this higher temperature of 600 °C are depletion-mode, exhibit high currents, and display excellent saturation.

rer equation, crystallite sizes for ZIO films are estimated to be smaller than 5 nm and 25–85 nm for films annealed below 500 and at 600 °C, respectively. Atomic force microscopy is used to confirm crystallite size of 600 °C-annealed films. B. Current–voltage characteristics

Figure 2 illustrates the drain current, drain-to-source voltage 共ID – VDS兲 curves of a TTFT in which the ZIO channel layer is subjected to a 600 °C post-deposition furnace anneal; these curves exhibit qualitatively ideal transistor characteristics. Note that this device operates in depletionmode, i.e., appreciable drain current flows at zero gate voltage, as evident from the VGS = 0 V drain current shown in Fig. 2. Figure 3 shows ID – VDS curves of a TTFT in which the ZIO channel layer is subjected to a 300 °C post-deposition furnace anneal. The curves shown in Fig. 3 exhibit qualitatively ideal transistor characteristics. In contrast to the device subjected to a 600 °C anneal, this device operates in enhancement-mode 共i.e., negligible drain current flows at zero gate voltage; a positive gate voltage is required to turn on the drain current兲, as evident from the fact that VGS for this figure decreases from +20 V 共top curve, showing maximum current兲 to 0 V in 2 V steps. ID decreases to a negligible value on the scale used in Fig. 3 for VGS ⬍ + 8 V. Additionally, the decreasing separation between ID curves at larger currents witnessed in the ID – VDS characteristic shown in Fig.

FIG. 3. Drain current–drain voltage 共ID – VDS兲 characteristics of a TTFT in which the ZIO channel layer is subjected to a 300 °C post-deposition furnace anneal. VGS is decreased from 20 V 共top curve, showing maximum current兲 to 0 V in 2 V steps. TTFTs processed at this lower temperature of 300 °C are enhancement-mode, exhibit moderately high currents, and display excellent saturation.

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FIG. 4. Log共ID兲 – VGS characteristics 共VDS = 20 V兲 of TTFTs in which the ZIO channel layer is subjected to either a 600 or a 300 °C post-deposition furnace anneal. The high temperature 600 °C processed device is clearly depletion mode, with a turn-on voltage of −12 V, a threshold voltage 共extracted from linear extrapolation of an ID – VGS curve兲 of −9 V, a drain current on-to-off ratio of ⬃106, and an inverse subthreshold slope of 0.8 V / decade. Similar values for the the low temperature 300 °C processed enhancement-mode device are +6 V, +7 V, ⬃106, and 0.3 V / decade, respectively.

3 is a non-ideal effect. This “crowded” characteristic is attributed to either an electron injection barrier at the source electrode26 or to mobility degradation associated with the increasing effect of interface roughness scattering as channel electrons are brought into closer physical proximity to the channel/insulator interface with increasing VGS.27 Figure 4 shows a comparison between the log共ID兲 – VGS characteristics 共at VDS = 20 V兲 of ZIO TTFTs annealed at 600 and 300 °C. The depletion- and enhancement-mode nature of devices processed at 600 and 300 °C, respectively, is clearly evident from this figure. The high temperature 600 °C processed device is depletion-mode with a turn-on voltage of −12 V, where turn-on voltage is defined as the gate voltage corresponding to the onset of the initial sharp increase in current in a log共ID兲 – VGS characteristic.14 Additionally, the threshold voltage is approximately −9 V for this device, as obtained from linear extrapolation of a ID – VGS curve 共not shown兲.27 Finally, Fig. 4 indicates that the device processed at 600 °C has a drain current on-to-off ratio of ⬃106 and an inverse subthreshold slope of 800 mV/ decade. The low temperature 300 °C processed enhancement-mode device has a turn-on voltage of +6 V, a threshold voltage of +7 V, a drain current on-to-off ratio of ⬃106, and an inverse subthreshold slope of 300 mV/ decade. The charge density in the channel layer, NT, corresponding to the turn-on voltage, Von, is estimated as28 NT =

CiVon , qtc

共1兲

where Ci is the gate insulator capacitance per unit area, q is the elementary charge, and tc is the thickness of the channel layer. For the TTFTs employed, Ci = 60 nF cm−2 and tc = 85 nm, so that NT ⯝ −7.1⫻ 1017 cm−3 for the depletionmode TTFT with VT = −9 V, and NT ⯝ + 3.2⫻ 1017 cm−3 for the enhancement-mode TTFT with VT = + 7 V. The negative charge responsible for the negative threshold voltage of the depletion-mode device is ascribed to delocalized electrons from shallow donors in the channel, which must be depleted from the channel layer by a negative gate voltage in order to turn off the TTFT drain current. The positive charge respon-

FIG. 5. Incremental mobility 共␮inc兲 and average mobility 共␮avg兲 vs gate voltage 共VGS兲 for ZIO TTFTs post-deposition annealed at: 共a兲 600 °C and 共b兲 300 °C. The higher annealing temperature yields a higher peak mobility and a lower threshold voltage.

sible for the positive threshold voltage of the enhancementmode device is attributed to deep traps in the channel or at the interface, which must be filled by electrons injected from the source electrode into the channel under the application of a positive gate voltage, which confines these injected electrons to a near-interface accumulation layer. C. Mobility assessment

A channel mobility comparison of ZIO TTFTs annealed at 600 and 300 °C is provided in Fig. 5. Two types of channel mobility are included in this figure, average mobility 共␮avg兲 and incremental mobility 共␮inc兲. These types of channel mobility are derived from the basic charge transport model without neglecting the gate voltage dependence of channel mobility.14 For this reason, ␮avg and ␮inc are preferred to the more commonly known effective and fieldeffect mobilities,27 which are based on extractions from the ideal metal–oxide–semiconductor field effect transistor equation. Consider the mobility characteristics shown in Fig. 5. First, note that the maximum mobilities of the ZIO TTFT processed at 600 °C are higher than those of the device processed at 300 °C. X-ray diffraction 共XRD兲 analysis suggests that the higher mobility of the ZIO TTFT processed at 600 °C may be associated with increased crystallinity. Additionally, the mobility difference may be a result of decreased defect density at the interface and/or in the bulk. Nonetheless, the magnitude of the channel mobility difference between polycrystalline and amorphous ZIO is rather small compared to polycrystalline and amorphous Si. This is attributed to a conduction band derived primarily from spherical s orbitals rather than anisotropic p or d orbitals.18–21 Next, consider the ␮inc – VGS curve shown in Fig. 5共a兲 for the TTFT annealed at 600 °C. At VGS values above a threshold voltage of ⬃−11 V, ␮inc increases to a peak mobility of 53 cm2 V−1 s−1 and then decreases. The initial rise in mobility corresponds to initiation of electron injection from the source electrode into the channel. The very first electrons injected into the channel are trapped in bulk and/or interface traps. As these trap states fill, a higher percentage of the injected channel electrons are free to drift, to the drain electrode, thereby resulting in an increase in ␮inc.29 The ␮inc – VGS curve shown in Fig. 5共a兲 decreases at larger VGS values as a consequence of either an electron in-

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jection barrier at the source electrode or due to mobility degradation associated with channel/insulator interface roughness scattering, as discussed in the context of Fig. 3. More work is required to conclusively establish the relative contributions of the source electrode injection barrier and interface scattering to the mobility reduction seen in Fig. 5. In any event, it is clear from a comparison of Figs. 5共a兲 and 5共b兲 that the mobility decrease with increasing gate voltage is much more pronounced 共for the VGS range shown兲 for the device processed at 300 °C. This is also evident from the fact that the separation between ID curves at larger currents decreases appreciably with increasing VGS in the saturation region for Fig. 3 but not for Fig. 2. Now compare ␮inc and ␮avg characteristics shown in Fig. 5; considering the origin of both mobilities helps illustrate the observed differences. Both ␮inc and ␮avg are estimated from the linear 共or triode兲 region of ID – VDS characteristics. However, ␮inc is extracted from the differential channel conductance with respect to gate voltage while ␮avg is extracted from the channel conductance. Thus, ␮inc corresponds to the incremental mobility of induced channel charge as it is gradually added to the channel with increasing VGS.14 This corresponds to the previously discussed physical description of the ␮inc – VGS trend in which the rising portion of the curve corresponds to incremental trap filling and the decreasing portion of the curve corresponds to either source injectionlimited behavior or interface roughness scattering. In contrast, ␮avg corresponds to the average mobility of all induced charge in the channel at a given VGS. For these reasons, ␮inc is the mobility of greater physical significance. In contrast, ␮avg is the mobility of greater practical significance, i.e., ␮avg is more directly related to actual device and circuit performance, and is thus the more important application-related figure-of-merit. In summary, ZIO depletion-mode TTFTs processed using an annealing temperature of 600 °C have peak incremental mobilities of 45– 55 cm2 V−1 s−1 and maximum average mobilities of 25– 35 cm2 V−1 s−1. Similarly, ZIO enhancement-mode TTFTs processed using an annealing temperature of 300 °C have peak incremental mobilities of 10– 30 cm2 V−1 s−1 and maximum average mobilities of 5 – 20 cm2 V−1 s−1. Both types of devices exhibit a decrease in mobility at large VGS, possibly due to an electron injection barrier at the source electrode or interface roughness scattering. These estimated channel mobilities of our ZIO TTFTs compare to incremental mobilities of ⬃25 cm2 V−1 s−1 for the best polycrystalline ZnO TTFT reported to date,14 ⬃80 cm2 V−1 s−1 for an engineered superlattice singlecrystal TTFT prepared by pulsed laser deposition and a hightemperature anneal of 1400 °C16, and 5–15 and 20– 50 cm2 V−1 s−1 for zinc tin oxide TTFTs annealed at 300 and 600 °C, respectively.18 D. Room temperature ZIO TTFTs

ZnO TFTs and TTFTs have recently been reported in which the ZnO channel layer is deposited by rf sputtering at near room temperature, i.e., with no intentional substrate

FIG. 6. Drain current–drain voltage 共ID – VDS兲 characteristics of a TTFT in which the ZIO channel layer is not subjected to a post-deposition anneal. VGS is decreased from 10 V 共top curve, showing maximum current兲 to 0 V in 1 V steps. This TTFT is enhancement-mode.

heating or post-deposition annealing.9,15 We have successfully fabricated ZIO TTFTs using this same basic procedure. The channel layer deposition process recipe employed for these near room temperature ZIO TTFTs is specified in Table I. As evident from Table I, our near room temperature process recipe differs from that of the other two process recipes in that the oxygen flow rate, the target–substrate distance, and the power density are all larger, while the pressure is lower. Figure 6 illustrates the ID – VDS curves of a TTFT in which the ZIO channel layer is deposited by rf sputtering near room temperature and is not subjected to a postdeposition anneal. This device operates in enhancementmode, as evident from the fact that VGS for this figure decreases from 10 V 共top curve, showing maximum current兲 to 0 V in 1 V steps. ID decreases to a negligible value on the scale used in Fig. 6 for VGS ⬍ 6 V. Our best ZIO TTFT results to date demonstrate a peak incremental mobility of 8 cm2 V−1 s−1共17 cm2 V−1 s−1兲 and a drain current on-to-off ratio of 104 共3 ⫻ 103兲 for enhancement-mode 共depletionmode兲 operation. IV. CONCLUSIONS

Zinc indium oxide 共ZIO兲 is demonstrated as a high mobility, n-type TTFT channel material. ZIO is found to be amorphous for post-deposition annealing temperatures up to at least 500 °C and polycrystalline at 600 °C. Thus, low temperature processed ZIO is an example of a class of high performance TTFT channel materials involving amorphous oxides composed of heavy-metal cations with 共n − 1兲d10ns0 共n 艌 4兲 electronic configurations. Although mobility is higher for ZIO TTFTs with a polycrystalline channel layer, the enhancement-mode nature, smoother surface texture, and lower processing temperature of an amorphous channel layer favors its use in future transparent or flexible electronics applications. ACKNOWLEDGMENTS

The authors would like to thank Arto Pakkala for supplying ITO / ATO coated substrates. This work was funded by the U.S. National Science Foundation under Grant No. DMR-0245386 and by the Army Research Office under Contract No. MURI E-18-667-G3.

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