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2012 24th International Conference on Microelectronics (ICM)

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TSV Impact on Circuit Performance and Recommended Design Methodologies Khaled Salah Mentor Graphics Cairo, Egypt [email protected]

Alaa El Rouby Mentor Graphics Cairo, Egypt [email protected]

Abstract— In this paper, a lumped element model for a through silicon via (TSV) is proposed based on the TSV physics. The proposed model is compact and compatible with SPICE simulators, hence it allows fast investigation of the TSV impact on 3-D circuits’ performance. Exploiting this attractive feature of the proposed model, it is shown that the TSV has a negligible effect on high-impedance device characteristics, and in such cases the TSV can be modeled a capacitance-dominated structure. In contrary, in case of low-impedance devices, the TSV has a significant effect on the device characteristics and the full TSV model need to be used. Moreover, this paper shows that the capacitive coupling between TSVs is significant and larger than the self capacitance while the inductive coupling is small and can be neglected. Some design methodologies are also presented here for signal integrity (SI), power integrity (PI), and thermal integrity (TI). Index Terms—Three-Dimensional ICs, Through Silicon Via, Modeling, TSV, Design Methodologies.

I. INTRODUCTION 3D Integration is now considered as a new paradigm in IC design enabling to overcome the actual limitations of 2D-ICs, improve performance, and enable heterogeneous stacking of different layers [1]. Today, many 3D technologies are existing, but TSV is one of the key points and is considered an excellent candidate for 3D integration. Therefore, finding a compact electrical model for the TSV and analyzing its impact on circuit performance to make design recommendations and to determine what physical parameters have to be tuned to enhance the TSV electrical performance is an important issue. So far, many published work regarding electrical modeling of TSVs has been focusing on 3D EM models of TSVs to extract their parasitic elements and to find its equivalent circuit model, [2]- [4]. Despite all these contributions, there is still a need for compact, wideband and SPICE-compatible model of the TSV taking into consideration nonlinearities effects and to study its impact on circuit performance to come up with recommended design methodologies. In this paper, a lumped element model for the TSV is presented. The impact of each lumped element of the proposed model on signal integrity will be investigated through SPICE simulations. Based on these investigations, design recommendations will be provided.

978-1-4673-5292-5/12/$31.00 ©2012 IEEE

Hani Ragai Ain-Shams University Cairo, Egypt [email protected]

Yehea Ismail AUC University Cairo, Egypt [email protected]

This paper is organized as follows; in Section II, the TSV is physically modeled and characterized and a wide-band proposed lumped element model for a TSV is introduced. In Section III, impact of the TSV on device performance is presented for single and multiple TSVs. Also, guidelines for design methodologies in TSV-Based 3D-ICs are presented. Conclusions are given in Section IV. II.

PORPOSED PHYSICS-BASED LUMPED ELEMENT MODEL

TSVs can be modeled using lumped or distributed circuit model. However, since the TSV size is much less than the wavelength of the considered frequency range, lumped circuit model is adapted [2]. Equivalent circuit model is the most popular one. The equivalent lumped element model of the TSV is proposed in Fig.1. The model contains series impedances of copper conductors, shunt oxide capacitances, and shunt silicon admittances including depletion region admittance where TSVs have a MOS-like transistor structure as the TSV metal behaves similar to a gate and the silicon substrate behaves similar to the bulk of a MOS [2]-[4]. The proposed coupling network between TSVs is shown in Fig. 2 where it includes resistive, capacitive and inductive coupling to neighboring TSVs. Each element and it is physical interpretation is summarized in Table I. Port1

Port2 Fig. 1 .The proposed lumped model for a TSV based on a single The model is composed of , , , , , , , , and

structure. .

2 TABLE I THE PROPOSED MODEL LUMPED ELEMENTS AND ITS PHYSICAL INTERPRETATION Circuit Physical meaning element Ohmic loss of the conductor. , Skin effect of the conductor: to capture the effect of , different current densities in different conduction layers, additional RL branches can be introduced in parallel to to represent each conduction layer across the TSV depth [23, 24]. For the model simplicity, we only bring in one extra RL branch ( , ), which models the surface layer resistance and inductance (skin effect). Capacitance of the oxide. Silicon substrate depletion region capacitance and , resistance. Silicon substrate capacitance and resistance. , Capacitive, resistive, and inductive coupling. , , Signal TSV

1

,

.5

. 5

Therefore, the coupling network between TSVs can be reduced to only capacitors as shown in Fig. 9. Port 1





Port 2

Fig. 3 Simplified circuit model for the TSV with all inductors short-circuited, substrate resistors open-circuited, and TSV resistors are short-circuited. Vout_actual

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III.

IMPACT OF THE TSV ON DEVICE PERFORMANCE

The proposed lumped element model of the TSV is simulated using SPICE to evaluate its impact on the 3-D integrated circuit performance. A pulse voltage source, with a Ω internal resistance, is applied to the actual model of the cylindrical TSV shown in Fig.1 and the resultant waveform were compared against the simplified model shown in Fig. 3 (where all inductors and resistors of the metal are shortcircuited and all resistors of silicon are open-circuited, i.e. , the TSV metal is approximated as a perfect conductor neglecting the ohmic loss and skin effect). This simulation was performed using the ELDO simulator [5]. From the waveforms shown in Fig. 4, the error between the complete model and the simplified model is small, hence the simplified model can be used in this case. Another experiment were performed for the case of Ω (i.e. representing a low impedance device), where the considerable performance difference, shown in Fig. 5, recommends the use of the actual model. Hence, for high impedance devices such as small drivers the simplified model can be used while in case of large cascaded buffers, i.e., low impedances devices, the complete model shown in Fig.1 has to be used for better accuracy. For the eye-diagram simulation, which is used to examine the signal integrity, 1Gbps pseudo random data was applied to the lumped element model of the TSV. As shown in Fig. 6, the eye diagram keeps its opening well. As capacitive and inductive coupling can have large effects on signal integrity, the crosstalk between TSVs must be examined. Simulations are performed for a variety of TSV arrangements to provide a clearer picture of the crosstalk effect. The crosstalk between two signals straightly arranged TSVs is investigated and the results are shown in Fig. 7. The inductive and resistive coupling between TSVs can be neglected as shown in Fig. 8.

4 3 2 1 0 49.98 50.00 50.02 50.04 50.06 50.06 50.08 50.10 50.12 50.14

Time (ns) Fig. 4 Simulated voltage waveforms of the actual output voltage (Vout which is measure from port 2 in Fig. 1) vs. the output from the simplified model (Vout_simplified which is measured from port 2 in Fig. 3) when a 5v pulse voltage source (VSource) is applied with an internal resistance R Ω. Vout_actual

Vout_simplified

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Fig. 2 The proposed coupling network between TSVs.

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Time (ns) Fig. 5 Simulated voltage waveforms of the actual output voltage (Vout which is measure from port 2 in Fig. 1) vs. the output from the simplified model (Vout_simplified which is measured from port 2 in Fig. 3) when a 5v pulse voltage source (VSource) is applied with an internal resistance Ω.

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Fig. 6 Simulated eye-diagram for the proposed lumped element model (for a single TSV) at 1 Gb/s.

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Fig. 8 Simulated voltage waveforms of the proposed model (taking mutual inductance into consideration, but neglecting self resistance and inductance) vs. the output from the proposed model (neglecting the mutual inductance effect, self resistance and inductance).

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Fig. 7 Simulated eye-diagram for the proposed lumped element model (including crosstalk effect) at 1 Gb/s.

Fig. 9 The simplified proposed coupling network between TSVs, where C = C || . 5C , referring to Fig. 2,

Problems How to fill? How to size? How to space? How to drive? Others

TABLE II GUIDELINES FOR DESIGN METHODOLOGIES IN TSV-BASED 3D-ICS Solutions for Signal Integrity (SI), Power Integrity (PI), Thermal Integrity (TI) -HRS: (high resistivity substrate) [6]. -Large SIO2: Increase the barrier oxide thickness during the process [6]. - Increase pitch: based on the case studies and mathematical models, TSV pitch should be greater than 2.5 diameters [7]. -CM signaling: current mode signaling is the most effective one in alleviating coupled noise and increasing data rates [8]-[11]. -Shielding: A solution consists in guarding the TSV using another TSV connected to the ground (both neighboring TSVs acts as shield, alleviate crosstalk). This solution will be probably more efficient than a guard ring using body contact (less deep) [6]. -Body contacts: As TSVs introduce resistive and inductive voltage drop in 3D ICs. This voltage drop at high frequency causes supply noise in 3D chips. The BCs make the inductive loop shorter [6]. -Thermal TSVs: Vertical vias are good thermal conductors. They can be used as thermal vias to remove the heat from each die. As high temperature can affect the interconnect reliability [9].

Guidelines for design methodologies in TSV-Based 3D-ICs for signal integrity (crosstalk noise, EMI, timing, noise, jitter, delay), power integrity (supply voltage noise, power delivery), and thermal integrity (reliability issue) are summarized in Table II and described below: 1) Impact of LRS, MRS and HRS: the insertion loss of the TSV in (high resistivity substrate) HRS is higher than in LRS and MRS (Fig.10). 2) Impact of thickness of SiO2: there is a reduction in power loss when the thickness of SiO2 is increased. (Fig.11).

3) Impact of increasing pitch: there is a reduction in power loss when the pitch is increased (Fig. 12). 4) Impact of signaling mode: current mode signaling is the most effective one in alleviating coupled noise and increasing data rates. 5) Impact of shielding: alleviate crosstalk. 6) Impact of body contact: alleviate crosstalk. 7) Impact of thermal TSVs: alleviating heat and improve thermal integrity.

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CONCLUSIONS

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In this paper, a lumped element model for the TSV is proposed. The proposed model allows modeling of TSV bundles without the need for computationally expensive electromagnetic field-solvers, within an acceptable error. The proposed model is used to study the impact of a typical TSV on a 3D circuit performance. This paper shows that the selfresistance and inductance of the TSV has negligible effect on high-impedance device characteristics, hence in such case the TSV can be considered a capacitance-dominated structure. Moreover, this paper shows that the TSV self-inductance and resistance have a significant effect on low-impedance device characteristics. Also, it has been shown that the capacitive coupling is significant and larger than the self capacitance while the inductive coupling is small and can be neglected. Guidelines for design methodologies in TSV-Based 3D-ICs are also presented.

Fig. 10 Impact of (low resistivity substrate) LRS, (high resistivity substrate) HRS, and (medium resistivity substrate) MRS on insertion loss.

REFERENCES

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[1] R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and LR.Zheng, "Compact Modelling of Through-Silicon Vias (TSVs) in Three Dimensional (3-D) Integrated Circuit", in Proc. IEEE International Conference on 3D System Integration (3D IC), 2009, San Francico, USA, 2009.

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[2] T.Bandyopadhyay, R.Chatterjee, D.Chung, M.Swaminathan and R. Tummala, "Electrical Modeling of Through Silicon and Package Vias," IEEE International Conference in 3D System Integration, 2009. 3DIC 2009. [3] C.Xu, H.Li, R.Suaya, and K.Baner-jee, "Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs," in IEDM09-521, 2009.

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[4] M.Stucchi, K.Meyer, and W.Dehaene, G. Katti, "Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 57, no. 1, January 2010. [5] http://www.mentor.com/products/ic_nanometer_design/analog-mixedsignal-verification/eldo/. [6] M. Rousseau, O. Rozeau, G. Cibrario, G. Le Carval, M.-A. Jaud, P. Leduc, A. Farcy, A. Marty, "Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology," in IMAPS Device Packaging Conference, Phoenix, AZ : United States, 2008.

Fig. 11 Impact of thickness of SiO2 on insertion loss.

[7] http://www.allvia.com.

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[8] R.Weerasekera, M.Grange, D.Pamunuwa “On Signalling Over ThroughSilicon Via (TSV) Interconnects in 3-D Integrated Circuits”Date, 2010.

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[9] H.Yu, J.Ho, and L.He “Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs” Electrical Engineering Dept. UCLA, 2009 .

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[10] K.C. Chillara, J.Jang, W.P. Burleson ” Robust signaling techniques for through silicon via bundles” . In Proceedings of ACM Conference Great Lakes Symposium on VLSI'2011. pp.383~386.

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[11] B. Wu and L. Tsang, "Full-wave modeling of multiple vias using differential signaling and shared antipad in multilayered high speed vertical interconnects," Progress In Electromagnetics Research, Vol. 97, 129-139, 2009.

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Fig. 12 Impact of increasing pitch between two TSVs on insertion loss.

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