Ultrafast Safety System to Turn-Off Normally On SiC JFETs Fabien Dubois*,**, Dominique Bergogne **, Damien Risaletto**, Rémi Perrin**, Abderrahime Zaoui**, Hervé Morel**, Régis Meuret* *
Hispano-Suiza - Safran Power Division SAFRAN Group, France Rond Point René Ravaud Moissy Cramayel, 77551, France E-Mail:
[email protected] URL: http://www.hispano-suiza-sa.com
**
Université de Lyon INSA Lyon, UCBL Lab Ampere Villeurbanne, France E-Mail:
[email protected] URL: http://www.ampere-lyon.fr
Acknowledgment This work was supported primarily by Hispano-Suiza (SAFRAN Group), Ampere Laboratory and in part by the CPES (Center for Power Electronics Systems) Industrial Consortium at Virginia Tech.
Keywords «Safety», «JFET», «Switch Mode Power Supply», «Protection Device», «Aerospace»
Abstract The use of normally on Silicon Carbide (SiC) JFET devices poses the question of safety and reliability in Voltage Fed Inverter (VFI) applications. Indeed, when a JFET is not driven with a sufficient negative voltage, the JFET is conducting and the VFI may be short-circuited. Therefore, it is needed to generate a negative voltage to turn-off the JFET to protect the VFI in case of gate driver failure. The settling time of this negative voltage must be inferior to the power system constant time to reduce the rise time of the short-circuit current. In this paper, a solution to protect the JFET and the system is proposed. A circuit description of an innovative topology using a Forward-Flyback topology with Primary Side Sensing (PSS) technique and an Output Voltage Estimation based on the Time Constant Matching (OVETCM) is presented. Moreover, the converter protects the VFI for an input range from 3 V to 610 V and up to 150 °C. Experimental results are provided and validate the design of the safety system.
Introduction Recently, normally on SiC JFET power switches have demonstrated advantages of SiC devices in high temperature and high efficiency applications [1-5]. These components allow fast switching, low onresistance, high breakdown voltage and high thermal conductivity [6]. SiC power switches can be found in VFI in aerospace, Photo-Voltaic systems, automotive or Oil Drilling applications. However, the fact that the power device is conducting when not biased with a sufficient negative voltage involves an obvious safety issue during start-up or shut-down of the DC power bus. In [7], a solution to the self turn-off the JFET is proposed: the DC power bus voltage is firstly fed to a linear regulator and in a non-isolated switched capacitor DC/DC converter. This solution provides a response time of about 200 μs during a short-circuit test, which corresponds to a dissipated energy in the JFET of 230 mJ at 25 °C. According to results provided in [8], normally on 1.2 kV 0.3 Ω JFET from SiCED withstands a short-circuit condition for 660 μs for a DC bus voltage of 540 V, which corresponds to a critical energy of 1.5 J at 25 °C. In [9], ageing of the SiC JFET from SiCED under repetitive short-circuit condition have been performed and shows that the JFET cannot sustain more than 10 000 short-circuits of 300 μs at a DC level of 540 V and ambient temperature of 25 °C. In addition, recent investigations indicate that the critical energy under short-circuits decreases roughly by a factor of two from 25 °C to 200 °C. Therefore, the protection circuit should respond in less than 100 μs to avoid any degradation of the VFI made with normally on SiC JFETs from SiCED at high
temperatures. So, the previously proposed solution is not fast enough to protect in an efficient way the system. Moreover, for some applications, isolation between the converter and the JFET protection circuit is mandatory. Therefore, the non-isolated switched capacitor converter is no longer the preferred solution. However, the linear regulator presented in [7] (JFET in series between the DC power bus and the DC/DC converter) that decreases the input voltage to approximately the pinch-off voltage of the JFET (J1) is used in the proposed solution. The complete system, which consists of an all-SiC JFET three-phase inverter, an EMI filter and normally on protection circuit is represented in Fig.1. The normally on protection circuit turns off only the low side JFETs.
Fig. 1: Normally On protection circuit. A negative voltage (Vout) is obtained from the DC bus. The proposed converter wakes up at very low input voltage (3V) to protect the VFI in case of a low charge or discharge time of the DC-link capacitor Cbus. The efficiency is not a design constraint since the protection operates only when a failure occurs. The paper presents an innovative ultrafast and reliable DC/DC converter that will replace the solution proposed in [7]. The operating principle and the design of the new converter are discussed in the following section. A prototype has been built and experimental results have been obtained. The prototype has been heated up to 150 °C for validation purposes.
Circuit selection, construction and operation As mentioned in the introduction, the converter should respond in less than 100 μs. Furthermore, high rate of change of the output voltage is needed in order to reduce the energy dissipated in the JFET. DC/DC converter falls into two general categories: 1) direct transfer of the energy, like Buck and Forward topologies, or 2) indirect transfer of the energy like Buck-Boost, Ck, Switched Capacitor and Flyback topologies. As a negative output voltage should be provided as quickly as possible to fully turn-off the JFET, the use of converter with direct transfer of energy is the more appropriate choice. The Forward topology is the selected topology since the Buck converter is not able to provide a negative voltage neither the insulation.
Fig. 2a: Typical Forward converter with L-C output filter
Fig. 2b: Modified Forward converter with R-C output filter
In a typical Forward converter, the chopped voltage is filtered by an L-C filter. This topology is represented in Fig. 2a. For an L-C filter, the rate of change of the output voltage is Vsec ⋅ 2π ⋅ f c ⋅sin(2π ⋅ f c ⋅ t ) , where Vsec represents the voltage at the secondary of the transformer and
fc is the cutoff frequency. For an R-C filter, the rate of change of the output voltage is Vsec ⋅ 2π ⋅ f c ⋅ e −2π ⋅ f c ⋅t . For the same cutoff frequency, the rate of change for an R-C filter is higher than for a L-C filter if t < α f switching
5 6 ⋅ π ⋅ fc
. As the reflected input voltage is applied to the output filter during
(α is the duty cycle), the rate of change of the output voltage is higher for an R-C filter than
for an L-C filter if the switching frequency is greater than
6⋅π ⋅ f c ⋅ α , which is always the case. 5
Therefore higher output voltage response can be achieved with the modified Forward structure depicted in Fig. 2b. The resistor will dissipate some power but the efficiency is not a major design constraint. The freewheeling diode is removed, which leads to a simpler and safer circuit The main issue with the Forward topology is the demagnetization of the core, however this drawback is used as an advantage. Indeed, usually this energy is wasted or recycled to the primary. For our application, a smarter way is to feed the output capacitor with the demagnetizing current, and so increase the output voltage when the switch is turned off. To do so, a third winding is connected to the output capacitor via a Flyback diode (D2) a shown in fig. 3. This configuration, represented in Fig. 3., is called Forward-Flyback and is discussed in papers [9-15]. D1
Rl
Cout
Rload
Cin D2
S1
Fig. 3: Improvement of the circuit of fig.1. This ultra-fast Forward-Flyback converter replaces the switched capacitor DC/DC converter. The operating principle are divided into three modes. The equivalent circuits of each operating mode are illustrated in figs. 4, 5 and 6. ip
Rl
vp
is
D1
Rl
D1 Cout
vs
vp
Rload vout
Cout
vs
Rload vout
Cin
Cin S1
vr
D2
vr
S1
D2 ireset
Fig. 5: Flyback Mode, S1 is turned-off
Fig. 4: Forward Mode, S1 is turned-on D1
Rl vp
Cout
vs
Rload vout
Cin S1
vr
D2
ireset
Fig. 6: Idle Mode, no current in S1, D1 and D2 Forward Mode [0~αT]: S1 is turned on as shown in Fig. 4. A positive voltage vp is applied across the magnetizing inductor Lmp, which leads to an increase of the primary current ip. A positive voltage vs is generated at the secondary of the transformer and the diode D1 is forward biased. The resistor Rl limits the secondary current is. The Flyback diode D2 is reverse biased. The output voltage increase, ΔVfrw , during the Forward mode is given by, ΔV frw = m p / s ⋅ 1− e
duty cycle
−
α f switching ⋅R l ⋅C out
, where mp/s is the transfer ratio primary to secondary and α is the (1)
Flyback Mode [αT~α'T]: S1 is turned off as shown in Fig. 5. The flux circulating in the core cannot be stopped instantaneously; therefore the Flyback diode D2 is forward biased to discharge the magnetizing current. Thus, the energy stored in the magnetizing inductance is transferred to the output and no power is wasted. Moreover, the output voltage response is improved. The output voltage increase ΔVfly during the Flyback mode is given by: 1 V ⋅α ΔV fly = ⋅ in , where Vin is the input voltage (2) Lmp ⋅ C out
f switching
Depending on the magnetizing inductance of the reset winding, the output capacitor and the duty cycle α , the output voltage increase ΔVout during the Flyback mode yields an improvement compared to a classical Forward structure. To avoid excessive voltage stress of S1 during turn-off because of the resonance between the leakage inductance of the transformer Lleakage and the sum of parasitic capacitor Coss of S1 and the primary winding input capacitance Cp, the maximum reverse voltage should be calculated. The overvoltage across the switch S1 is given by: VS1max = Vin + Vout ⋅ m p / r + I p max ⋅
Lleakage C oss + Cp
, where mp/r is the transfer ratio primary to reset
(3)
Idle Mode [α’T~T]: S1 is off as shown in fig. 6. The magnetizing current flowing through the Flyback diode D2 reaches 0 at t = α ' ⋅t = I pm max ⋅
np n reset
⋅
Lmreset . Thus, the diode is reverse biased and the Vout
voltage across S1 is equal to the input voltage. The output capacitor discharges into the resistive load. As the converter is a Forward topology, the core should be demagnetized before the next cycle begins. To insure a complete demagnetization of the core, the following relationship should be respected. I s max ⋅
Vout (1− α ) < Lmreset Fswitching
(4)
Design of the ultrafast Forward-Flyback converter Innovative Control Solution To decrease the power consumption, increase the power density, and improve reliability (higher MTBF) and isolation, an innovative control method based on a Primary Side Sensing (PSS) [16-18] and an Output Voltage Estimation with the Time Constant Matching (OVETCM) is presented. The output voltage can be monitored with an extra winding connected directly to the control circuit on primary side. To do so, it is necessary to get a reflected voltage from the secondary, which occurs during the Flyback Mode (S1 is in the off state). The reflected voltage is rectified by the diode Dcontrol and used to regulate the output voltage. The sensing technique is depicted in Fig. 7. The load is constant but the input voltage varies so some kind of voltage regulation is required.
Fig. 7: Forward-Flyback with Primary Side Sensing Technique The regulation of the output voltage is achieved via a hysteretic control, which simplifies the design of the control loop. The hysteretic control works such that the converter is turned to idle mode when the output voltage is above the expected output voltage and turned on again when the output voltage is below the expected voltage (i.e. discharge of the output capacitor) as shown in fig. 8. When the
converter is activated, the controller drives S1 with a fixed frequency and fixed duty cycle. The switching frequency is much higher than the ripple frequency during steady state. The output voltage ripple frequency due to the control is determined by: f output _ voltage _ ripple = Rout ⋅C out ⋅ ln
1 Vout _ exp ected
(5)
Vout _ max
Fig. 8: Hysteretic Control Technique When the converter is idle, the output voltage is estimated using a time constant matching method. This method consists in matching a R-C filter located in the control side with the same time constant that the output filter. A schematic of the method is presented in Fig. 9.
Fig. 9: Circuit Diagram of the Output Voltage Estimation based on Time Constant Matching method (OVETCM) As the load is mainly capacitive and known (i.e. gate-to-source capacitance of the JFET), good estimation of the output is achievable. To decrease the estimation error, a resistor is added at the output of the converter with a value at least ten times lower than the value of the equivalent resistance corresponding to the leakage current. The accuracy of the control technique is presented in the following. Fig. 10 represents the deviation of the control voltage due to a mismatch of the two time constants (e.g. variation of parameter with initial tolerances of components). Vctlr represents the control voltage across the control load, Vespected corresponds to the desired output voltage and Vout is the output voltage of the converter. The overvoltage plays an important role also. The overvoltage is due to the fact that the output voltage is monitored only during the Flyback Mode. Thus, when the converter is turned-on, the Forward Mode increases the output voltage.
Fig. 10: Qualitative estimation of the Primary Side Sensing error From Fig. 10, it can be noticed that when the time constant of the control load is lower than the time constant of the output load, the output voltage is higher than the expected value. In contrary, when the time constant of the control load is greater than the one of the output stage, the output voltage is lower than the expected value. In this particular case, the JFET can be turned on, which will lead to high dissipation in the JFET.
Transformer Design The transformer is the key element of the design and special winding technique is used to enhance the coupling between primary winding and secondary winding, and control winding and reset winding. The magnetizing inductance should be high enough in order to reduce the energy stored in the core. To avoid many turns, which may lead to high leakage inductance, medium to high permeability materials are preferred. For design up to 120 °C, ferrite core is the preferred choice. Ferrite provides medium initial permeability (1000 to 5000) with low remanent flux density (e.g. 0.1 T for MnZn material) and low maximum density flux (e.g. 0.5 T for MnZn material). The maximum density flux is 0.5 T. Table I provides the magnetic characteristics for an EFD 25 shape and N87 materials from EPCOS. Parasitic components and magnetizing inductances have been assessed using the impedance analyzer 4294A from Agilent. The switching frequency is chosen at 200 kHz. To insure a complete demagnetization of the core a duty cycle of 32 % is chosen.
Table I: Forward-Flyback transformer characteristics Value
Unit
Symbol
Parameter
Bmax
Maximum Flux Density
0.5
Τ
Br
Remanent Flux
0.11
T
ΔB
Flux Density Swing
0.15
T
Np
Turns of the Primary Winding
4
Ns Nr
Turns of the Secondary Winding Turns of the Reset Winding
14 3
Nc
Turns of the Control Winding
3
Lpm
Magnetizing Inductance (Primary)
30
Lsm
Magnetizing Inductance (Secondary)
270
μH
Lrm
Magnetizing inductance (Reset)
16.88
μH
Lcm
Magnetizing Inductance (Control)
16.86
μH
Kp/s
Coupling Primary/Secondary
0.998
Kr/c
Coupling Reset/Control
0.995
Cp/s
Inter-Winding Capacitance Primary-tosecondary
8
pF
Cr/c
Inter-Winding Capacitance Reset-toControl
10
pF
μH
High coupling Kp/s and Kr/c have been obtained with the interleaved winding technique. Thus, good regulation with low noise on the control side is achieved, as the reader will see in the section dealing with experimental results.
Circuit Schematic The controler is a well-known and reliable timer TLC555 (CMOS technology) from Texas Instrument. The timer exhibits very low power consumption (< 1mW @2 V), low wake up voltage (2 V) and high output current capability (100 mA). No external driver is needed to drive the low threshold voltage and low gate charge MOSFET IRL530N from International Rectifier. 1% accuracy resistors and 5% accuracy capacitors are used. The TLC555 is powered from a 4.7 V zener regulator. The control circuit is connected to the reset pin of the TLC555 in order to activate or put to idle the converter. The complete DC/DC converter is depicted in Fig. 11.
Fig. 11: Circuit diagram of the Forward-Flyback Converter with PSS and OVETCM techniques
Experimental results For experimental validation of the proposed Forward-Flyback converter shown in Fig. 11, a prototype circuit was built and tested in the laboratory. The prototype is shown in Fig.12. The switching frequency is chosen at 200 kHz and the duty cycle at 32 %. The hysteresis control frequency is approximately 5.5 kHz. Figs. 13 to 18 show the measured waveforms when the proposed converter is supplied by a laboratory power supply of 30 V-5 A. For sake of readability, the output voltage of the ultrafast converter is depicted in the positive side instead of negative side; no electrical difference since the output voltage is isolated . Fig. 19 shows the measured waveforms of the JFET (drain-source voltage, drain current) when the proposed converter is connected to the HVDC bus via the linear regulator as shown in Fig. 1.
Fig. 12: Forward-Flyback converter prototype used for validation and measurements Figs. 13 to 15 illustrate the measured waveforms during a power-up sequence for an input voltage slew rate of 10 V/μs.
10 μs/div Fig. 13: Output voltage during Power-Up (5 V/div)
4 μs/div 4 μs/div (a) (b) Fig. 14: Output voltage (2 V/div) and primary current during Power-Up. (a) Second Period Forward Mode (b) Second Period Flyback Mode Globally, the output voltage reaches 20 V in 60 μs. From Fig. 14.a, the output voltage increases during the Forward Mode (second period) is 1.08 V. From Fig. 14.b, the output voltage increases during the Flyback Mode is 1.8 V, which represents an improvement of more than 150 % during a switching cycle compared to a standard Forward topology.
4 μs/div
Fig. 15: Drain-to-source voltage in brown (20 V/div), output voltage in blue (2 V/div) and source current in green (1 A/div)
100 μs/div Fig. 16: Output voltage response (5 V/div) for an input voltage (5 V/div) slew rate of 10 V/ms
From Fig. 15, it can be noticed that the magnetizing current reaches 0 during the Flyback Mode since the drain-to-source voltage reaches Vin after the Flyback Mode. Thus, the transformer is not saturated before the next cycle begins. Fig. 16 illustrates that the converter wakes up for an input voltage of 2.5 V.
10 μs/div 10 μs/div (a) (b) Fig. 17: Primary Side Sensing Validation; output voltage in blue (5 V/div), control voltage in brown (5 V/div). (a) Power-Up (b) Steady-State The control voltage of the OVETCM and the output voltage Vout are plotted in Figs. 17a and 17b. The discrepancy is below 2 %, which corresponds to the expectation. The mean value is 21.3 V. The peakto-peak ripple voltage is equal to 3.4 V. This is fine since the JFET is off between 17 V and 24 V. The converter is heated up to 150° C. The variation of the output voltage with temperature is represented in Fig. 18 .The temperature coefficient is equal to 76 mV/°C. The high temperature coefficient is due to the simple comparison circuit which uses the Vbe of a bipolar transistor, an improved version is under test up to 200 °C. For application with ambient temperature as high as 80 °C, the JFET remains off.
Fig. 18: Variation of output voltage (V) with temperature (°C) Fig. 19 illustrates waveforms of one of the JFET (0.3 Ω 1200 V 20 A) of the VFI during Power-up when no gate driver voltage is present. The drain current reaches 0 A after 45 μs, which is better than the requirement of 100 μs. The energy dissipated in the JFET is equal to 60 mJ, which is much below than the critical energy of the JFET of 0,8 J at 200 °C as defined in [6].
20 μs/div Fig. 19: VFI Power-Up (600 V) with a gate driver failure, the JFETs are normally on. The ultrafast turn off circuit operates and saves the system. Drain-to-source voltage in red (250 V/div), gate-tosource voltage in green (5 V/div) and drain current in pink (5 A/div)
Conclusion Recent study on ageing of normally on SiC JFET from SiCED demonstrates that the response time to protect the JFET against short-circuit condition should be lower than 100 μs. At power up, a VFI using normally on switches, such as JFETs, is a short-circuit in the event of a JFETs gate driver failure. In this paper, an improved ultrafast DC/DC converter was presented and results were proposed. A specific control technique based on a Primary Side Sensing and an Output Voltage Estimation based on the Time Constant Matching (OVETCM) has also been validated on a prototype. The measured response time of the safety system is equal to 60 μs, which prevents any degradation of the normally on SiC JFET when the DC/DC converter is implemented in a safety system. The proposed ultrafast solution allows the use of normally on devices in VFIs that are directly connected to a DC bus.
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