IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 1, JANUARY 2013
129
Ultralow-Voltage Solution-Processed Organic Transistors With Small Gate Dielectric Capacitance Linrun Feng, Wei Tang, Xiaoli Xu, Qingyu Cui, and Xiaojun Guo, Member, IEEE
Abstract—In this letter, ultralow-operation-voltage (< 2 V) solution-processed organic thin-film transistors were achieved at small gate dielectric capacitance of only 12.2 nF/cm2 in the bottom-gate bottom-contact configuration. In the devices, 6,13-bis(triisopropylsilylethynyl)-pentacene blended with polystyrene was used as the channel layer, and ultraviolet cross-linked polyvinyl alcohol was used as the gate dielectric layer. The maximum processing temperature was 100 ◦ C. The devices showed promising performance with a mobility value of about 1.0 cm2 /(V · s), a subthreshold swing of about 100 mV/dec, and negligible hysteresis. The mechanism of achieving such a low operation voltage without needing large gate dielectric capacitance for the devices was discussed. Index Terms—Low temperature, organic thin film transistors (OTFTs), solution processed, ultralow voltage.
I. I NTRODUCTION
T
HE rapid progress of soluble organic semiconductors opens up the possibility of printing organic thin-film transistors (OTFTs) and circuits onto arbitrary substrates for highthroughput and low-cost manufacturing of large-area, flexible/ rollable, or conformal electronics [1]–[3]. However, the operation voltage of OTFTs, currently with a typical value of a few tens of volts, needs to be greatly reduced for practical applications. In the past, significant efforts have been devoted to this purpose by using solution-processed ultrathin dielectric films [4], [5] or high-dielectric-constant (high-k) polymer dielectric films [6] to increase the gate dielectric capacitance. However, ultrathin dielectric films are thought to be incompatible with printing processes over large-area and flexible substrates. With regard to high-k dielectrics, it has been reported that they could be unfavorable for carrier transport due to the broadening of the trap density of states at the semiconductor/dielectric interface by the formed dipole disorder [7]. There is also a lack of suitable solution-processable dielectric materials of high enough k values. Recently, Yan et al. have demonstrated that a low operaManuscript received September 18, 2012; revised October 26, 2012; accepted October 28, 2012. Date of publication December 13, 2012; date of current version December 19, 2012. This work was supported in part by the National Natural Science Foundation of China under Grant 60906039, by the Program for Professor of Special Appointment (Eastern Scholar), Shanghai Institutions of Higher Learning, by the Program for New Century Excellent Talents in University, and by the Shanghai Pujiang Program under Grant 11PJ1404700. The review of this letter was arranged by Editor C. V. Mouli. The authors are with the Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai 200240, China (e-mail:
[email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2012.2227236
Fig. 1. Schematic of the bottom-gate bottom-contact (BGBC) structure OTFT and the chemical structures of the used materials.
tion voltage could be achieved by using a 160-nm-thick high-k ferroelectric polymer (k of ∼60) without obviously affecting the charge transport, but only working for conjugated polymer semiconductors with side chains [6]. Moreover, since large overlaps are normally formed between the source/drain and gate electrodes of OTFTs due to the process limitations, smaller gate capacitance will be helpful to decrease the parasitic capacitance for higher circuit speed and lower power consumption. In this letter, a strategy of decreasing the operation voltage without relying on the increase of the gate dielectric capacitance for OTFTs was demonstrated. Solution-processed OTFTs with an ultralow operation voltage (< 2 V) were achieved with the maximum processing temperature of 100 ◦ C. II. E XPERIMENTAL P ROCEDURE The device structure and used materials are illustrated in Fig. 1. A 40-nm aluminum metal layer was thermally evaporated onto the glass substrate as the gate electrode. Polyvinyl alcohol (PVA) was dissolved in deionized water at a concentration of 40 g · L−1 . Subsequently, the cross-linking reagent ammonium bichromate was mixed into the solution at a mass ratio of 1:6 to PVA. The mixed solution was then spin coated onto the sample at 3000 r/min for 1 min, followed by a cross-linking process through ultraviolet (UV) exposure (λ ∼ 195 nm) for 5 min and then heating at 100 ◦ C for 1 h. A 407-nm-thick film was finally formed as the gate dielectric layer. Silver source/drain electrodes (60 nm) were then thermally evaporated with a shadow mask, defining the channel width and length
0741-3106/$31.00 © 2012 IEEE
130
IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 1, JANUARY 2013
TABLE I C OMPARISON OF THE E XTRACTED C APACITANCE VALUES FOR THE D EVICES IN T HIS W ORK W ITH T HOSE OF P REVIOUSLY R EPORTED L OW-VOLTAGE OTFT S
Fig. 2. (a) Transfer and (b) output characteristics of the fabricated TIPSpentacene/PS blended channel OTFT. (c) Transfer characteristics showing negligible hysteresis. (d) Measured unit area gate dielectric capacitance CG as a function of the inverse of the gate insulator thickness tGI .
of 1200 and 70 μm, respectively. The electrodes were then modified by immersing in a 5 × 10−3 mol · L−1 solution of perfluorobenzenethiol (PFBT) in ethanol for 2 min and then rinsed with ethanol. The semiconducting layer was spin coated from a solution made by mixing 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) and polystyrene (PS) at 10 g · L−1 concentration of solids in chlorobenzene (3:1 ratio by volume). Spin coating was carried out at 600 r/min for 1 min and was followed by annealing at 100 ◦ C for 30 min in a nitrogen environment. The devices with TIPS-pentacene-only channels were fabricated through the same procedure as above except using a solution of TIPS-pentacene in chlorobenzene at 10 g · L−1 . The thickness of the semiconductor layers was measured to be 75 nm (TIPS-pentacene-only) and 110 nm (TIPS-pentacene/ PS), respectively. Electrical properties were characterized with a Keithley 4200 system. Film thickness was measured by a KLA-Tencor D-120 profiler, and the surface roughness was measured using a BioScope Veeco atomic force microscope. All measurements were performed at room temperature in air. III. R ESULTS AND D ISCUSSIONS Fig. 2 shows the measured electrical characteristics of the devices. An operation voltage below 2 V is achieved. Fieldeffect mobility of about 1.0 cm2 /(V · s) is extracted in the saturation regime at a gate–source voltage of −1.0 V. Negligible hysteresis can be observed in the ID –VGS characteristics, as shown in Fig. 2(c). The measured subthreshold swing (SS) value is about 100 mV/dec, which is similar to that of OTFTs using the self-assembled monolayer gate dielectric [5] and using a 160-nm-thick high-k (∼60) polymer gate dielectric [6].
Fig. 3. (a) AFM image of the PVA dielectric surface. (b) Comparison of the measured ID –VGS characteristics for the two types of devices with the TIPSpentacene/PS blended channel and the TIPS-pentacene-only channel. (Inset) Measured capacitance as a function of gate-to-source/drain voltage for the two types of devices (the source and the drain are connected together).
As a key parameter for realizing a low-voltage operation, the classical SS expression developed for a metal–oxide– semiconductor field-effect transistor (MOSFET) is described as [8] kb T Cch SS = ln 10 · (1) 1+ q CG where kb is the Boltzmann’s coefficient, q is the electron charge, CG is the gate dielectric capacitance, and the effective channel capacitance Cch is a sum of the depletion capacitance Cdep and Cit being related to the charging of the semiconductor–dielectric interface traps. Although (1) was originally developed for inversion-mode MOSFETs, it was also shown to be a good approximation for accumulation-mode devices [9] and thus suitable for OTFTs. The difference is that, for OTFTs, Cdep is contributed by charging of bulk traps in the channel [10]. Based on (1), with the measured CG of 12.2 nF/cm2 [the measured k is about 5.6, as shown in Fig. 2(d)], the value of Cch was extracted for the devices in this work and compared with those of previously reported low-voltage OTFTs [5], [6] in Table I. Obviously, it is the significantly reduced Cch contributing to the low SS value and, thus, the realization of a low operation voltage in this work with a much smaller CG . The atomic force microscopy (AFM) image in Fig. 3(a) shows a very smooth PVA surface with a root-mean-square roughness of about 0.3 nm, which is the prerequisite to form a low trap-state interface between the channel and the gate dielectric layer for a small Cit . The negligible hysteresis in Fig. 2(c) also indicates this. However, since low interface trap states were also achieved in the previous work [6], it is believed that the reduction of Cdep plays a more dominant role in achieving such a small SS.
FENG et al.: ULTRALOW-VOLTAGE OTFTs WITH SMALL GATE DIELECTRIC CAPACITANCE
To significantly reduce Cdep , an effective way that has been used for inorganic devices is to design the devices to be operated in a fully depleted mode with ultrathin channels [11]. In this mode, the less variation of the depletion charges with the gate voltage induces a negligible Cdep . Similarly, in OTFTs, considering that Cdep is mainly contributed by charging of bulk traps in the channel, a strategy for significantly reducing Cdep would be to form a thin channel of low bulk trap states to allow the trap charges in the channel to be less than the maximum gate controllable charges [11]. It has been reported that a solution of the TIPS-pentacene blended with a polymer dielectric material, which has a solubility parameter quite different to TIPS-pentacene and a large enough molecule mass (normally more than 20 000 g · mol−1 ), could result in a trilayer film composed of a TIPS-pentacene layer on the top, a mixed layer of TIPS-pentacene/polymer dielectric in the middle, and a TIPS-pentacene layer at the bottom interface [12], [13]. The neutron reflectivity and grazingincidence X-ray diffraction measurement results show that a TIPS-pentacene layer as thin as 10 nm could be obtained at the bottom interface with a highly crystalline structure with the π−π stacked molecular layers oriented parallel to the film surface [12]. In this letter, PS with a molecule mass of 35 000 g · mol−1 is used, and thus based on the previous study [12], similar phase separation is expected to occur in the film to form a thin and highly crystalline channel structure of low bulk charge traps, which, in turn, could enable achieving small Cdep as analyzed earlier. Fig. 3(b) compares the measured ID –VGS characteristics for the two types of devices with the TIPSpentacene/PS blended channel and the TIPS-pentacene-only channel. The extracted threshold voltages VT of the devices are −0.15 V (TIPS-pentacene/PS) and −1.6 V (TIPS-pentaceneonly), respectively. The steep SS of the TIPS-pentacene/PS transistor results in a much lower operating voltage compared with the TIPS-pentacene-only transistor. This phenomenon clearly states the importance of the formed highly crystalline thin-channel structure with the blended material system on the reduction of SS. The capacitance–voltage (C–V ) characteristics were also measured based on the gate-to-source/drain (the source and the drain are connected together) capacitor structure for the two types of devices and are consistent with the ID –VGS characteristics, as shown in the inset in Fig. 3(b). With the BGBC structure OTFT, a small Cit and vastly reduced Cdep can be achieved. Therefore, the devices can be operated with ultralow voltages even with a relatively small CG . Additionally, in the BGBC structure, the active layer is finally deposited, which could avoid damages to the active layer during the processes. Moreover, in the BGBC structure, the surface properties of the source/drain electrodes and the gate dielectric can be tailored to form controllable metal/semiconductor and semiconductor/dielectric interfaces.
131
IV. C ONCLUSION In summary, this letter demonstrates a strategy for realizing low-voltage OTFTs without relying on large gate dielectric capacitance. The device presents a mobility value of about 1 cm2 /(V · s), a small SS of 100 mV/dec, and VT of −0.15 V. An ultralow operation voltage down to 2 V is achieved with small gate dielectric capacitance down to 12.2 nF/cm2 . The developed BGBC device architecture with a relatively thick gate dielectric layer (about 400 nm) and a low-temperature process (≤ 100 ◦ C) is able to fit into an integration scenario for development of low-voltage printed organic integrated circuits on cheap plastic substrates. R EFERENCES [1] M. Berggren, D. Nilsson, and N. D. Robinson, “Organic materials for printed electronics,” Nat. Mater., vol. 6, no. 1, pp. 3–5, Jan. 2007. [2] A. C. Arias, J. D. MacKenzie, I. McCulloch, J. Rivnay, and A. Salleo, “Materials and applications for large area electronics: Solution-based approaches,” Chem. Rev., vol. 110, no. 1, pp. 3–24, Jan. 2010. [3] G. H. Gelinck, H. Edzer, A. Huitema, E. van Veenendaal, E. Cantatore, L. Schrijnemakers, J. B. P. H. vanderPutten, T. C. T. Geuns, M. Beenhakkers, J. B. Giesbers, B.-H. Huisman, E. J. Meijer, E. MenaBenito, F. J. Touwslager, A. W. Marsman, B. J. E. vanRens, and D. M. deLeeuw, “Flexible active-matrix displays and shift registers based on solution-processed organic transistors,” Nat. Mater., vol. 3, no. 2, pp. 106–110, Feb. 2004. [4] X. Cheng, M. Caironi, Y.-Y. Noh, J. Wang, C. Newman, H. Yan, A. Facchetti, and H. Sirringhaus, “Air stable cross-linked Cytop ultrathin gate dielectric for high yield low-voltage top-gate organic field-effect transistors,” Chem. Mater., vol. 22, no. 4, pp. 1559–1566, Feb. 2010. [5] P. H. Wöbkenberg, J. Ball, F. B. Kooistra, J. C. Hummelen, D. M. deLeeuw, D. D. C. Bradley, and T. D. Anthopoulos, “Low-voltage organic transistors based on solution processed semiconductors and selfassembled monolayer gate dielectrics,” Appl. Phys. Lett., vol. 93, no. 1, p. 013303, Jul. 2008. [6] J. Li, Z. Sun, and F. Yan, “Solution processable low-voltage organic thin film transistors with high-k relaxor ferroelectric polymer as gate insulator,” Adv. Mater., vol. 24, no. 1, pp. 88–93, Jan. 2012. [7] J. Veres, S. D. Ogier, S. W. Leeming, D. C. Cupertino, and S. M. Khaffaf, “Low- k insulators as the choice of dielectrics in organic field-effect transistors,” Adv. Func. Mater., vol. 13, no. 3, pp. 199–204, Mar. 2003. [8] S. M. Sze and K. N. Kwok, Physics of Semiconductor Devices. Hoboken, NJ: Wiley, 2007. [9] J. P. Colinge, D. Flandre, and F. Van de Wiele, “Subthreshold slope of long-channel, accumulation-mode p-channel SOI MOSFETs,” Solid State Electron., vol. 37, no. 2, pp. 289–294, Feb. 1994. [10] S. Scheinert, G. Paasch, and T. Doll, “The influence of bulk traps on the subthreshold characteristics of an organic field effect transistor,” Synth. Metals, vol. 139, no. 2, pp. 233–237, Sep. 2003. [11] T. Kawamura, H. Uchiyama, S. Saito, H. Wakana, T. Mine, M. Hatano, K. Torii, and T. Onai, “1.5-V Operating fully-depleted amorphous oxide thin film transistors achieved by 63-mV/dec subthreshold slope,” in Proc. IEEE IEDM, 2008, pp. 77–80. [12] J. Kang, N. Shin, D. Y. Jang, V. M. Prabhu, and D. Y. Yoon, “Structure and properties of small molecule–polymer blend semiconductors for organic thin film transistors,” J. Amer. Chem. Soc., vol. 130, no. 37, pp. 12 273– 12 275, Sep. 2008. [13] J. Smith, R. Hamilton, I. McCulloch, N. Stingelin-Stutzmann, M. Heeney, D. D. C. Bradley, and T. D. Anthopoulos, “Solution-processed organic transistors based on semiconducting blends,” J. Mater. Chem., vol. 20, no. 13, pp. 2562–2574, 2010.
