IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 10, OCTOBER 1998
367
Ultrathin Nitride/Oxide (N/O) Gate Dielectrics for p -Polysilicon Gated PMOSFET’s Prepared by a Combined Remote Plasma Enhanced CVD/Thermal Oxidation Process Yider Wu and Gerald Lucovsky
Abstract—Ultrathin nitride-oxide (N/O1.5/2.6 nm) dual layer gate dielectrics have been incorporated into PMOSFET’s with boron-implanted polysilicon gates. Boron penetration is effectively suppressed by the top plasma-deposited nitride layer leading to improved short channel performance as compared to PMOSFET’s with oxide dielectrics. In addition, improved interface characteristics and hot carrier degradation immunity are also demonstrated for the devices with the N/O dual layer gate dielectrics. Index Terms—Boron penetration, gate dielectrics, nitride, N/O.
I. INTRODUCTION
A
S the aggressively scaling of CMOS technology continues, nitride/oxide dual layer gate dielectrics have become promising candidates as alternatives to thermal oxide gate dielectrics in dual gate CMOS devices. One of their advantages is the ability of the nitride layer to act as a boron diffusion barrier. It has been shown that 0.8 nm of a plasma-deposited nitride effectively suppresses boron transport out of p gates during a high thermal budget dopant activation [1]. High temperature nitridation of thermal oxides has also been used to suppress boron diffusion; however, because the nitrogen concentration is peaked at oxide/substrate interface, this results in boron accumulation in the bulk oxide, increasing electron trapping and degrading oxide reliability [2]. With the diffusion barrier located at polysilicon/oxide interface, the N/O dual layer dielectrics have shown improved reliability by preventing boron diffusion into oxide layer [1]. In addition, because silicon nitride provides almost twice the dielectric constant of silicon dioxide, lower tunneling currents in the direct tunneling regime can be obtained for the same equivalent oxide thickness [3]. In this work, we have investigated p -poly gated PMOSFET’s with N/O dual layer gate dielectrics in which the nitride layer was prepared by remote plasma enhanced chemical vapor deposition (RPECVD) [4], [5] and the oxide layer by thermal oxidation. This paper is the first report of the Manuscript received May 4, 1998; revised June 19, 1998. This research was supported in part by the National Science Foundation, the Semiconductor Research Corporation, and the Office of Naval Research. The authors are with the Department of Electrical and Computer Engineering, and the Department of Physics, North Carolina State University, Raleigh, NC 27695-8202 USA (e-mail:
[email protected]). Publisher Item Identifier S 0741-3106(98)07388-1.
application of RPECVD nitride films to PMOSFET’s. Previous publications addressed the incorporation RPECVD nitride into NMOSFET’s with phosphorus doped poly gates [3]. The use of RPECVD nitride films to suppress boron diffusion from p poly gates represents a complementary processing approach to plasma-assisted top-surface nitridation [6], [7]. II. EXPERIMENTAL PMOSFET’s, without LDD drains, but with p -poly gates m/20 m were fabricated on 1–10 and substrates. Channel doping was increased cm n-type Si 10 /cm by phosphorus implantation. A 2.6 nm to 6.7 oxide was grown in dry oxygen at 800 C This was followed by the deposition of a 1.5 nm nitride by RPECVD using SiH and N as source gases [4]. The nitride thickness was estimated from the deposition rate, and confirmed to 0.1 nm by Auger electron spectroscopy [8] and ellipsometry. Postdeposition annealing of the dual layer was performed in He at 900 C for 30 s to reduce the hydrogen concentration in plasma deposited nitride, and thereby produce device-quality electrical characteristics [4]. The nitride films of this study were deposited from SiH and N sources gases, and have essentially the same electrical properties after a 30 s 900 C RTA as thin nitride films prepared from SiH and NH [3], [4]. Polysilicon was deposited and then implanted with boron 10 cm ); the boron was activated at 950 C (20 keV, 5 of for 60 s. An equivalent oxide electrical thickness 3.5 0.05 nm was obtained from analysis of high-frequency – data. III. RESULTS
AND
DISSUSION
Fig. 1 shows nitrogen SIMS profiles for N/O 0.8 nm/4.0 nm dielectrics including the effect of the post-deposition annealing. The plasma deposited nitride film is clearly evident. The tailing of the nitrogen signal into the oxide is an artifact of the SIMS analysis method. After annealing at 900 C for 30 s, a nitrogen peak appears at the oxide/silicon interface, showing that N-atoms diffuse into, and pile up at the oxide/silicon interface during the anneal. Si-N bonds at the interface replace Si-O bonds, relieving interface strain due to the smaller effective size of the nitrogen atoms, and additionally provide a physically smoother interface [9]. This means that the
0741–3106/98$10.00 1998 IEEE
368
IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 10, OCTOBER 1998
Fig. 1. Nitrogen profile of N/O ( 0.8 nm/4.0 nm) dual layer gate dielectrics with and without RTA at 900 C for 30 s. The N-atom profile is broadened into the oxide region by the SIMS ion bombardment technique.
Fig. 2. C –V and subthreshold Id –Vg characteristics for devices with N/O and oxide gate dielectrics with boron-implanted polysilicon. The capacitor size is 100 m 100 m and the transistor geometry (L/W) is 0.8 m/20 m. The shift of the curves to more positive voltages for the devices with the oxide dielectrics is a result of boron penetration to the channel.
2
dielectrics used in these devices can be described as NON stacks. Suppression of boron diffusion from the gate electrode has been monitored by – and – characteristics. As shown traces are shifted to more in Fig. 2, both – and – positive voltages for the thermal oxide device, indicative of a significant penetration of boron to the Si channel. The
Fig. 3. Id –Vd characteristics of N/O dual layer (solid line) and oxide (dashed line) p+ -poly PMOSFET’s with a 0.8 m channel length. The absence of saturation for the devices with oxide dielectrics is due to boron penetration to the channel region.
data in Fig. 2 demonstrate that the top nitride layer of N/O structure is effective in suppressing boron diffusion out of the gate electrode. In addition, because the separation of the high-frequency and quasistatic – curves at the onset of inversion is determined by the interfacial defects, it is clear that N/O dual layer dielectrics have a reduced density of interface defect states. This is assumed to be due to the incorporation of nitrogen at oxide/substrate interface during the post-deposition anneal. Fig. 3 shows the – characteristics of 0.8 m channel length PMOSFET’s with N/O dual layer and single layer oxide gate dielectrics. The N/O dual layer device shows better saturation characteristics than the device with oxide. The curve in the saturation region increased slope of the – for the oxide is indicative of an enhanced short channel effect associated with boron penetration. The effective mobility of N/O dual layer and oxide devices were extracted form m m to avoid the large transistors effects of uncertainties in the source/drain series resistance. As shown in Fig. 4, essentially the same effective mobilities were obtained for N/O dual layer and oxide devices, indicating an advantage of the low temperature RPECVD process in maintaining the oxide/substrate interface integrity. Also, due to the nitrogen incorporation at oxide/substrate interface during the post-deposition anneal, the PMOSFET with N/O dual layer during hot carrier stressing, dielectrics shows a reduced implying a more robust Si/SiO interface. The stressing in Fig. 4 was performed at peak substrate current. This improved interface immunity against hot carrier stressing is believed to be due to interfacial strain relaxation that occurs for the substitution of interfacial Si-O bonds by Si-N bonds, and is similar to what has previously been reported for NMOSFET’s [10], [11].
WU AND LUCOVSKY: ULTRATHIN NITRIDE/OXIDE GATE DIELECTRICS
369
improving hot carrier stress degradation. Since the PMOSFET’s of this paper display the same effective mobility as oxide devices as well as improved reliability, the N/O dual layer gate dielectrics show good promise for sub-0.25 m dual-gate CMOS technology. REFERENCES
0
Fig. 4. Stress-time dependence of Gm degradation (Vg –Vth = 2:1 V, Vd = 7:5 V) and effective hole mobility verses effective normal field of PMOSFET’s for oxide and N/O dual layer gate dielectrics. The stressing is done at maximum substrate current.
0
IV. CONCLUSIONS N/O dual layer gate dielectrics prepared by a combined RPECVD/oxidation process with equivalent oxide thickness of 3.5 nm have been fabricated for p -poly PMOSFET’s. The top nitride layer reduces boron penetration into the oxide and channel, thereby eliminating some short channel effects, and
[1] Y. Wu and G. Lucovsky, “Improvement of gate dielectric reliability for + poly MOS devices using remote PECVD top nitride deposition on p thin gate oxides,” in Proc. IEEE Int. Reliability Physics Symp., 1998, p. 70. [2] D. Wristers, L. Han, T. Chen, H. H. Wang, and D. Kwong, “Degradation of oxynitride gate dielectric reliability due to boron diffusion,” Appl. Phys. Lett., vol. 68, p. 2094, 1996. [3] C. Parker, G. Lucovsky, and J. Hauser, “Ultrathin oxide-nitride gate dielectric MOSFET’s,” IEEE Electron Device Lett., vol. 19, p. 106, 1998. [4] Y. Ma, T. Yasuda, and G. Lucovsky, “Ultrathin device quality oxidenitride-oxide heretostructure formed by remote plasma enhanced chemical vapor deposition,” Appl. Phys. Lett., vol. 64, p. 2226, 1994. [5] S. V. Hattangady, H. Niimi, and G. Lucovsky, “Integrated processing of silicon oxynitride films by combined plasma and rapid thermal processing,” J. Vac. Sci. Technol. A, vol. 14, p. 3017, 1996. [6] S. V. Hattangady, H. Niimi, and G. Lucovsky, “Controlled nitrogen incorporation at the gate oxide surface,” Appl. Phys. Lett., vol. 66, p. 3495, 1995. [7] S. V. Hattangady, R. Kraft, D. T. Grinder, M. A. Douglas, G. A. Brown, P. A. Tiner, J. W. Kuehne, P. E. Nicollian, and M. F. Pas, in IEDM Tech. Dig., 1996, p. 495. [8] C. Chang, “General formalism for quantitative Auger analysis,” Surf. Sci., vol. 48, p. 9, 1975. [9] M. L. Green, D. Bransen, K. W. Evans-Lutterodt, L. C. Feldman, K. Krisch, W. Lennard, H. T. Tang, L. Manchanda, and M. T. Tang, “Rapid thermal oxidation of silicon in N2 O between 800 and 1200 C: Incorporated nitrogen and interfacial roughness,” Appl. Phys. Lett., vol. 65, p. 848, 1994. [10] M. Moslehi, K. Sarawat, and S. Shatas, “Rapid thermal nitridation of SiO2 for nitroxide thin dielectrics,” Appl. Phys. Lett., vol. 47, p. 1113, 1985. [11] D. R. Lee, C. G. Parker, J. R. Hauser, and G. Lucovsky, “Reliability of nitrided Si-SiO2 interfaces formed by a new, low temperature remoteplasma process,” J. Vac. Sci. Technol. B, vol. 13, 1778, 1995.
